艾斯特拉股份有限公司 Astera Labs Taiwan Limited

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.Role Overview Are youpassionate about pushing the boundaries ofsystem,memory,software,andchiparchitecture? Do youthrive whenpitchingcutting-edge technology solutions tocustomersandindustrypartners? We are seekinga creative customer facingTechnologistto help facilitateAstera’s developmentofdata centermemorysolutions.In this role, you will play a pivotal role in driving thearchitecture and definitionof future products by leveraging your expertise insystem architecture,SOCmemory sub-systemarchitecture, PCIe/CXLtechnologies,DRAM/memory architecture,andhardware-softwareco-design. You will have the opportunity to directly engage with customers,influence product features and roadmap,and help drive innovation to better solve ourcustomers’bottlenecks in hyperscale data centers. This role is fully in person, inSan Jose.Some travel may be required. Basic qualifications  BS in Electrical or computer engineering, MS or PhD preferred. ≥10 year’s experience developing memory-related solutions and integrating them into systems/racks for data centers Deep experience with PCIe 5/6, and CXL including protocol level depth Expertise in OS software integration including memory allocation/management Recent experience with silicon architecture and development especially SOCs with memory controllers (DDR*, LPDDR*, HBM, etc) Deep expertise and understanding of memory components (DRAM, etc) Strong understanding of datacenter system architecture and design challenges Strong understanding of “full stack” solutions from silicon to application integration Experience working in a customer-facing role with the ability to articulate technical concepts, influence decision-making, and build business cases Ability to dig deeply into technical challenges and use cases Excellent communication and interpersonal skills with the ability to collaborate effectively with internal teams and external partners. Demonstrated leadership capabilities with a track record of driving cross-functional technical initiatives and delivering results in a fast-paced environment. Willingness to travel occasionally for customer meetings and industry events. Preferred experience  Expertise inJEDEC-defined memory interface specifications Expertise in memory ECC and error handling Experience in product integration with BIOS, kernel, OS, tooling, and BMCs Experience with board and system design Existing engagement and robust network within industry organizations such as PCI-SIG, OCP, JEDEC, CXL, etc. Hands-on silicon development experience Salary range is $205,000 to $255,000 depending on experience, level, and business need. This role is eligible for discretionary bonus, incentives and benefits.We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com. Job Description The mission of this role is to architect and develop firmware and microcontroller subsystems for Astera Labs’ SoC and systems products. Firmware is responsible for implementing the major differentiating features of Astera Labs’ products. As such, firmware is considered equally important to the hardware, and the firmware team is often customer-facing accordingly to ensure the needs of the customer are fully comprehended. Basic Qualifications Strong academic and technical background in electrical engineering. At a minimum, a Bachelor’s in EE or Computer Science is required, and a Master’s is preferred. 5+ years of experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications. Experience developing firmware to execute in on-chip microcontrollers as well as C-language software development kits (SDKs) to execute on system management controllers (e.g. BMC). Experience working with logic designers to architect and verify HW-SW interfaces on complex SoCs. Professional attitude with the ability to prioritize a dynamic list of multiple tasks, to plan and prepare for customer meetings in advance, and to work with minimal guidance and supervision. Entrepreneurial, open-minded behavior and can-do attitude. Think and act fast with the customer in mind! Required Experience Experience developing embedded firmware for PCIe products. MQX RTOS or ThreadX Development or enablement. High level of proficiency in C (preferred) or C++, including development of C-based SDKs. High level of proficiency in Python for automating pre-processors/post-processors and FW QC. Working knowledge of software/firmware build environments, gcc/Make, Doxygen, and GitHub. Hands-on experience with Server, Storage, and/or Networking equipment (e.g. Network Switches). Familiarity with SoC interfaces to common IP blocks such as PCIe Controllers, NVME Controllers, AMBA/AHB interfaces, on-chip memory interfaces, and other similar interfaces Direct experience working on products with high-speed interfaces common in Data Center equipment: PCI- Express (Gen-3 and above), 100/400G Ethernet, Infiniband, NVMe, etc Preferred Experience Experience developing firmware to execute in on-chip microcontrollers as well as C-language SDKs to execute on system management controllers (e.g. BMC) Experience with industry forums and collaboration workgroups such as OCP and OpenBMC The base salary range is $160,000.00 USD – $190,000.00 USD. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com. We are seeking to hire an Optical Firmware Engineer, Principal develop, optimize, and maintain embedded firmware for optical engines, photonic integrated circuits (PICs) optical modules. This includes control of lasers, modulators, photodetectors, thermal management, calibration, and high-speed link optimization in optical / silicon photonics systems. The role sits at the intersection of embedded systems, photonics, and hardware. Key Responsibilities: Design, develop, and debug real-time firmware for optical transceivers or PIC/EIC engines (e.g., in C/C++ for microcontrollers or embedded processors). Implement algorithms for laser control, automatic power control (APC), temperature compensation, wavelength locking, and link training/adaptation. Integrate firmware with hardware (DSP, drivers, ADCs/DACs) and higher-level software (e.g., via I2C, SPI, or custom interfaces). Develop diagnostic, calibration, and telemetry features for manufacturing test, field monitoring, and reliability. Optimize for low latency, power efficiency, and high reliability in high-speed (400G/800G/1.6T+) optical links. Collaborate with optical, electrical, DSP, and system validation teams to characterize and tune performance. Support bring-up, debugging, and qualification of silicon photonics prototypes. Handle firmware updates, version control, and compliance with standards (e.g., OIF, CMIS). Required Qualifications: BS/MS/PhD in Electrical Engineering, Computer Engineering, Physics, or related field + 12+ years of industry experience. Strong experience in embedded firmware development (bare-metal or RTOS) for optical or high-speed communication systems. Knowledge of photonics concepts: lasers, modulators, photodiodes, TIA, thermal tuning. Proficiency in C/C++, Python (for scripting/tools), and debugging tools (JTAG, oscilloscopes, optical test equipment). Experience with high-speed SerDes, signal integrity, or optical link optimization is a plus. Familiarity with silicon photonics, or pluggable optics (QSFP, OSFP) is highly valued. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com. Role Overview Astera Labs is seeking a Tech Lead Field Application Engineer to serve as the technical bridge between our customers and engineering teams, supporting our industry-leading connectivity solutions across the Aries PCIe retimer, Scorpio Ethernet fabric switch, and Leo CXL memory connectivity platforms. This is a high-impact, customer-facing role where you'll be embedded with hyperscaler and OEM partners, helping them design, validate, and deploy Astera Labs silicon into the AI infrastructure systems that are reshaping the data center landscape. As AI clusters scale to tens of thousands of GPUs and accelerators, the connectivity fabric binding compute, memory, and networking together has never been more critical. You'll operate at the intersection of cutting-edge silicon and real-world system deployment—solving complex signal integrity, interoperability, and performance challenges that directly influence product roadmaps and customer success. This role demands a self-starter who thrives in ambiguity, can independently drive technical engagements, and is energized by frequent travel to customer sites. Key Responsibilities Customer Technical Engagement Serve as the primary technical point of contact for strategic customers, providing deep application support for Aries, Scorpio, and Leo product families Drive board design reviews, schematic reviews, and system-level debug sessions with customer hardware and system development teams Deliver technical presentations, training sessions, and product demonstrations tailored to customer architectures and use cases System Debug Enablement Lead hands-on debug of PCIe, Ethernet, and CXL/DDR memory connectivity issues in customer server and rack-scale platforms Collaborate with internal silicon, firmware, and applications engineering teams to resolve field issues and drive root cause analysis Develop and maintain application notes, reference designs, and technical collateral based on field learnings Strategic Feedback Product Influence Capture and communicate customer requirements, competitive insights, and system architecture trends to product management and engineering Represent the voice of the customer in internal roadmap discussions, helping shape next-generation connectivity solutions Identify new use cases and expansion opportunities within existing accounts Basic Qualifications Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field 5+ years of experience in server hardware design, cloud system development (SysDev), or field application engineering Hands-on experience with PCIe protocol/physical layer including signal integrity fundamentals, link training, and debug Working knowledge of DDR memory subsystems and memory interface design or validation Self-starter mentality with the ability to work independently and drive customer engagements with minimal supervision Willingness to travel up to 40-50% to customer sites Preferred Qualifications Experience with CXL protocol or CXL-enabled memory architectures Familiarity with Ethernet switch or NIC silicon in data center environments Experience working directly with hyperscaler or Tier-1 OEM customers Proficiency with lab equipment (oscilloscopes, protocol analyzers, BERT) and signal integrity tools Strong presentation and communication skills with the ability to convey complex technical concepts to diverse audiences Prior experience at a semiconductor company in an FAE or applications engineering capacity We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com. Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions grounded in open standards. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. Discover more atwww.asteralabs.com. Job Description: As member of Astera Labs Hardware Engineering team you will be responsible for building diagnostics and manufacturing software to allow design, test, and manufacture cutting edge high speed datacenter products. You will be working on project from conception to the final production stage at contract manufacturer. The role requires strong and broad software background and good understanding of hardware design and manufacturing practices. At the same time we welcome candidates with deep experience in smaller areas and desire to learn. Depending on your experience you may be focusing on design/validation or automation/manufacturing. Key Responsibilities Design, implement test production-grade diagnostics for high-speed digital boards and ASICS to help with hardware validation. Design, implement test manufacturing tests to validate mass production of digital boards used in data center networking product Bring-up newly manufactured boards. Isolate and perform root-cause analysis of reported failures Support new platform software and hardware features Coordinate with the hardware engineering team on bring-up schedules and feature delivery Participate proactively in design discussions, design review, and project management Work independently as well as in team roles, mentor younger team members Business travel to China will be required as needed Basic Qualifications/Required Experience Bachelor’s in CS/CE or equivalent experience. 2+ years of Experience in subset of diag, hardware bring-up, test or manufacturing automation Knowledge of modern software development Proficiency in Python Preferred experience Experience working with datacenter-level complex electronic equipment bring-up/diagnostic/manufacturing Ability to read schematic/layout System debug experience Embedded programming and good knowledge of OS internals (Linux/Unix) Has knowledge of common inter connecting buses and interfaces such as PCIe, I2C, XAUI, 10G Ethernet drivers, FPGA, Switch chips, SSL offload, TCAM programming. Experience with DDR5 We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.Role Overview Astera Labs is seeking a Senior Director of Product Marketing to lead go-to-market strategy for our industry-leading fabric switch and memory controller solutions. This is a high-impact leadership role at the intersection of technology and market strategy, where you'll shape how the world's largest hyperscalers and AI infrastructure builders understand and adopt our connectivity products. As a senior leader on the product marketing team, you'll drive positioning, messaging, and competitive strategy for products enabling the next generation of AI and cloud data centers. You'll partner closely with engineering, sales, and executive leadership to translate customers’ needs into competitive roadmaps and compelling value propositions that resonate with decision-makers. This role requires someone who can move fluidly between silicon-level technical discussions and strategic market conversations. With AI infrastructure demand accelerating and Astera Labs at the forefront of solving critical connectivity bottlenecks, this is an opportunity to shape the narrative for technologies like PCIe, UALink, CXL and emerging high-speed protocols that are powering rack-scale AI systems worldwide. Key Responsibilities Go-to-Market Strategy Execution Lead product strategy, positioning, and go-to-market strategy for fabric switch and controller product lines Define and execute product launches that drive awareness, demand, and adoption with hyperscaler and enterprise customers Develop compelling content including presentations, blogs, datasheets, and technical collateral Market Competitive Intelligence Own competitive analysis and market intelligence for fabric switch controller product lines Identify market trends, customer needs, and emerging opportunities in AI infrastructure connectivity Translate market insights into actionable product and positioning recommendations Cross-Functional Leadership Partner with engineering to deeply understand product capabilities and drive roadmap Enable sales teams with training, tools, and competitive positioning to win strategic accounts Collaborate with executive leadership to align product marketing initiatives with corporate strategy Team Stakeholder Management Build and mentor a high-performing product marketing team Serve as a technical spokesperson at industry events, customer meetings, and analyst briefings Drive alignment across marketing, product, and sales organizations Basic Qualifications Bachelor's degree in Electrical Engineering, Computer Engineering, or related technical field 12+ years of experience in product marketing, product management, or technical marketing roles Demonstrated experience with PCIe technology or high-speed switching/interconnect products Strong understanding of semiconductor products and silicon development lifecycle Proven track record of leading successful product launches in the data center or infrastructure market Experience presenting to and influencing technical audiences including engineers and architects Preferred Qualifications MBA or Master's degree in a technical discipline Experience marketing to hyperscaler and enterprise customers (AWS, Google, Microsoft, Meta, etc.) Familiarity with high speed connectivity protocols, such as UALink, PCIe, and CXL Background in AI/ML infrastructure or data center architecture Experience building and leading product marketing teams at high-growth technology companies Strong executive presence and public speaking skills for industry events and analyst engagements Salary range is $240,000 to $300,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.Role Overview Astera Labs is seeking a Quality Engineer to join our Product Quality Engineering team in San Jose, CA. This is an exciting opportunity for an early-career engineer to dive into the heart of AI infrastructure connectivity, working hands-on with cutting-edge semiconductor devices that power the world's most advanced data centers. In this role, you will be instrumental in driving root-cause analysis of failures across circuit, package, firmware, and protocol layers — directly impacting the reliability and quality of our PCIe and Ethernet connectivity solutions. You'll work with state-of-the-art lab instrumentation, build infrastructure to accelerate failure analysis, and collaborate across engineering disciplines to ensure Astera Labs continues to deliver best-in-class silicon to hyperscale customers. If you're passionate about high-speed SERDES, signal integrity, and solving complex hardware problems at the intersection of AI and connectivity, this is the role for you. Key Responsibilities Failure Analysis Root-Cause Infrastructure Enable and develop infrastructure such as databases to optimize and reduce time to root-cause failures in circuit, package, firmware, or protocol-level iterations Participate in the new product development process to enable improvements and capabilities for failure analysis Document product quality engineering processes and methodologies to ensure repeatability and scalability Lab Measurement Debug Perform measurements on high-speed SERDES, PCIe, and Ethernet devices to characterize and debug quality issues Set up and use advanced lab instrumentation including BERT, high-bandwidth oscilloscopes, protocol analyzers, VNAs, TDR, and spectrum analyzers to support debug and root-cause activities Cross-Functional Collaboration Collaborate with design, validation, hardware, and system engineering teams to resolve quality issues and drive continuous improvement Support cross-functional efforts to improve product reliability and manufacturing quality Basic Qualifications Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field Understanding of high-speed serial interfaces (PCIe, Ethernet, SERDES) Familiarity with lab instrumentation such as oscilloscopes, BERT, TDR, or spectrum analyzers Strong analytical and problem-solving skills Excellent documentation and communication skills Preferred Qualifications Internship or project experience in semiconductor quality, product engineering, or hardware validation Exposure to signal integrity concepts and high-speed measurement techniques Experience with database tools or scripting languages (Python, SQL) for data analysis and infrastructure development Familiarity with failure analysis methodologies in a semiconductor environment Knowledge of PCIe or Ethernet protocol specifications The salary range for this position is $120,000 to $140,000 depending on experience and education level. This role may be eligible for discretionary bonus, incentives and benefits. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.Job Description: As an Analog/Mixed-Signal IC Design Engineer Intern, you will be part of a key team designing sophisticated advanced node CMOS products. Your responsibilities will include developing and verifying circuits such as PLL, DLL, ADC, regulators, amplifiers, TX, RX, and CDRs to meet performance targets. You will also work on analog and clocking blocks for connectivity applications, using industry-standard tools like Spectre and MATLAB. The company seeks a highly motivated designer for this role Basic Qualifications: Pursuing a Master’s or PhD degree in EE is preferred Desired Experience: Hands-on experience in designing high-speed mixed-signal circuits including ADC/DAC data converters, RX front-end, TX driver/serializer, low-jitter PLLs, TX/RX calibration, low-jitter CLK distribution are other high-speed analog circuits is a must Have a deep understanding of biasing, band-gaps, reference circuits, opamps, comparators and other analog circuits Solid track-record for implementation of analog circuits high-speed data transmission. Design and tapeout experience in advanced CMOS nodes (ex. 20nm or newer) is a must Solid fundamentals in detailed transistor-level design, feedback/stability analysis, and noise/jitter analysis. Knowledge of TIA design and drivers for optical applications is highly desirable Experience in RFIC design for wireless or wireline communication systems is highly desirable. Strong technical independent contributor with a proven ability to drive results. Excellent teamwork, presentation, and documentation skills. Ability to collaborate with global teams across multiple time zones and deliver under pressure with strict deadlines. Strong experience in lab chip bring-up and debugging efforts. Relevant research publications and/or patents in analog or RF IC design. Familiarity in programming/scripting languages such as Python, Matlab, or C. Experience with PCB design. Familiarity with Verilog RTL or DSP design concepts. Knowledge of optical transceivers. Expertise in ESD protection techniques and IC packaging methodologies. The pay range for this role is $55-65/hour + $500 housing stipend + cash relocation bonus (dependent on location) We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.Job Description: As an Analog/Mixed-Signal IC Design Engineer , you will be part of a key team designing sophisticated advanced node CMOS products. Your responsibilities will include developing and verifying circuits such as PLL, DLL, ADC, regulators, amplifiers, TX, RX, and CDRs to meet performance targets. You will also work on analog and clocking blocks for connectivity applications, using industry-standard tools like Spectre and MATLAB. The company seeks a highly motivated designer for this role Basic Qualifications: Pursuing a Master’s or PhD degree in EE is preferred Desired Experience: Hands-on experience in designing high-speed mixed-signal circuits including ADC/DAC data converters, RX front-end, TX driver/serializer, low-jitter PLLs, TX/RX calibration, low-jitter CLK distribution are other high-speed analog circuits is a must Have a deep understanding of biasing, band-gaps, reference circuits, opamps, comparators and other analog circuits Solid track-record for implementation of analog circuits high-speed data transmission. Design and tapeout experience in advanced CMOS nodes (ex. 20nm or newer) is a must Solid fundamentals in detailed transistor-level design, feedback/stability analysis, and noise/jitter analysis. Knowledge of TIA design and drivers for optical applications is highly desirable Experience in RFIC design for wireless or wireline communication systems is highly desirable. Strong technical independent contributor with a proven ability to drive results. Excellent teamwork, presentation, and documentation skills. Ability to collaborate with global teams across multiple time zones and deliver under pressure with strict deadlines. Strong experience in lab chip bring-up and debugging efforts. Relevant research publications and/or patents in analog or RF IC design. Familiarity in programming/scripting languages such as Python, Matlab, or C. Experience with PCB design. Familiarity with Verilog RTL or DSP design concepts. Knowledge of optical transceivers. Expertise in ESD protection techniques and IC packaging methodologies. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.Join Astera Labs as aSenior Digital Design Engineer to drive the design and implementation of next-generation digital designs for high-performance AI connectivity solutions. In this role, you'll focus on CPU subsystem development and security architecture, working on complex blocks from micro-architecture through silicon bring-up. You'll collaborate closely with verification, physical design, and DFT teams to deliver industry-leading products that power the world's most advanced data centers. This is an opportunity to shape the security and compute foundations of connectivity solutions enabling rack-scale AI infrastructure at hyperscale. Key Responsibilities RTL Design Implementation Own the RTL implementation of complex digital designs from micro-architecture through sign-off Design and implement CPU subsystems and embedded processor interfaces Develop security-focused digital blocks including secure boot, cryptographic engines, and trusted execution environments Verification Quality Collaborate with verification teams to review test plans and debug issues Support efforts to achieve timing closure and implement Design-for-Test (DFT) features Accountable for quality and overall design success with the support of senior engineers Methodology Automation Scripting and automation for ASIC methodology improvement Contribute to design infrastructure that improves team productivity and design quality Basic Qualifications Bachelor's degree in Electrical Engineering or equivalent 3+ years of experience developing SoC/silicon products in Server, Storage, and/or Networking markets Expertise in RTL coding with SystemVerilog and synthesis with Synopsys or Cadence Experience with CPU subsystem design or embedded processor integration (RISC-V, ARM, or similar architectures) Understanding of security fundamentals in silicon design (secure boot, root of trust, cryptographic implementations) Experience with clocking, CDC, and RDC methodologies Proficiency in SystemVerilog and Python in a production environment Preferred Qualifications Experience designing or integrating security IP (cryptographic accelerators, secure enclaves, key management) Familiarity with high-speed protocols—PCIe Gen 6/7, Ethernet, UALink, or UCI Experience with CMOS nodes (≤7nm) Exposure to embedded firmware development or secure firmware boot flows Experience with functional and formal verification at block and chip level Familiarity with UVM-based verification methodologies Base salary range is $135,000 to $195,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.