Find out how well you fit this job.

Job updated about 22 hours ago
The employer was active 2 days ago

Job Description

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.

Role Overview

Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we are seeking a motivated Physical Design Student to join our founding local engineering team.

This is a unique opportunity to kickstart your career in the semiconductor industry. Working alongside senior industry veterans, you will gain hands-on experience in backend execution and advanced methodologies for cutting-edge chips that power the world's largest AI clusters. If you are passionate about silicon hardware, eager to learn, and thrive on solving complex engineering challenges, this role offers the perfect bridge between your academic studies and a high-impact career.

Key Responsibilities

Guided Implementation & Learning

  • Partner with and learn from senior engineers to support the physical implementation journey, including synthesis, floorplanning, Place & Route (P&R), and Clock-Tree Synthesis (CTS)
  • Assist in macro-level implementation and develop hands-on skills in complex layout routing
  • Participate in deep-submicron process challenges under close professional mentorship

Signoff & Design Integrity Support

  • Assist in running engineering checks for design integrity, including Static Timing Analysis (STA), Physical Verification (DRC/LVS), and Reliability analysis (EMIR)
  • Learn to apply Logic Equivalence Checking (LEC) to help guarantee design correctness
  • Gain exposure to the rigorous flows required to ensure first-pass silicon success

Scripting & Cross-Functional Collaboration

  • Leverage and develop scripting tools to automate repetitive tasks and optimize the engineering environment
  • Collaborate with Architecture, Design, and DFT teams to understand how different chip design disciplines intersect
  • Actively participate in team reviews and technical discussions to ramp up backend methodologies

Basic Qualifications

  • Pursuing a Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related technical field
  • Strong academic foundation in digital systems, VLSI design, or semiconductor devices.
  • Familiarity with Python, TCL, Bash, or Perl.
  • Ability to work at least 2 days per week at our Haifa/Tel Aviv Center
  • A "can-do" attitude with a passion for solving complex technical challenges
  • Fluent in Hebrew and English with the ability to work effectively in a team environment

 Preferred Qualifications

  • Prior experience from a previous VLSI/Hardware student position or a significant academic project in physical design/VLSI
  • Hands-on university lab experience with industry-standard EDA tools (e.g., Synopsys Fusion Compiler/ICC2, Cadence Innovus)
  • Understanding of basic verification concepts (STA, DRC, LVS)
  • Fast learner with a proactive attitude and a passion for deep-tech hardware infrastructure

We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

View all jobs

Find out how well you fit this job.

View all jobs

Find out how well you fit this job.

Find out how well you fit this job.

1
No requirement for relevant working experience
Negotiable
Personal Invitation Link
This is your personal referral link for job invitation. You'll receive an email notification when someone applied for the position via your job link.
Share this job

About us

||About Astera Labs||

Astera Labs is a global leader in purpose-built connectivity solutions for rack-scale AI, redefining the future of data center infrastructure. Our pioneering software-defined architecture delivers unmatched scalability and customization to meet the evolving demands of AI workloads. By leveraging advanced PCIe®, CXL®, Ethernet, and UALink semiconductor-based technologies, we eliminate critical data, memory, and networking bottlenecks with exceptional efficiency. Trusted by hyperscalers and deeply integrated within the data center ecosystem, we empower next-generation performance and innovation at scale.

||Our coporate values||

Act With Intent
Take ownership with a day-one mindset and entrepreneurial spirit.

Stay Customer Focused
Relentlessly prioritize the customer’s needs, perspective and their trust in us.

Deliver Results
Have a strong bias for action, stay flexible and embrace change to relentlessly drive success.

Invent & Simplify
Innovate with a platform mindset, exponentially rather than incrementally.

Nurture Trust
Operate with integrity and the highest ethical standards to uphold trust.

Raise the Bar Together
Support, empower, and collaborate to continuously elevate expectations.