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Create your job-winning resume using our free resume builder.
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Showcase your skills and projects with a professional portfolio.
Cake AI
Utilize our Cake AI-powered products to accelerate job search and talent match.
Resume
Create your job-winning resume using our free resume builder.
Resume Builder
Make a resume for free.
Resume Templates
Access our extensive library of professional & ready-to-use templates.
Resume Examples
Get inspired by real resume examples to create your own.
Occupation Guide
Access resume writing guides tailored for different professions.
Resume Help
Get expert advice on all things resume from our team of recruitment specialists.
Cake AI Resume CheckerNew
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The employer was active about 19 hours ago
1. ASIC Design or IP Integration 2. Familiar with Digital front-end EDA tool.
1. ASIC Design or IP Integration 2. Familiar with Digital front-end EDA tool.
Hsinchu City, Taiwan 300, New Taipei City, Taiwan
1.8M ~ 2.5M TWD / year
3 years of experience required
No management responsibility
• 面板驅動IC 或 SoC 設計
• 面板驅動IC 或 SoC 設計
East District, Hsinchu City, Taiwan, 300
2.5M ~ 3.5M TWD / year
5 years of experience required
No management responsibility
面板驅動IC或SOC設計 影像處理與影像壓縮設計 高速介面數位控制(如MIPI/ISP等)
面板驅動IC或SOC設計 影像處理與影像壓縮設計 高速介面數位控制(如MIPI/ISP等)
Hsinchu, Hsinchu City, Taiwan
1.8M ~ 3M TWD / year
1 years of experience required
No management responsibility
工作內容 Knowledge of System Verilog, digital simulation and debug. Exposure to UVM is desired. Familiar with USB design is a plus. DV Experience: 6~10 years 薪資架構 13個月計算, RSU 另計
工作內容 Knowledge of System Verilog, digital simulation and debug. Exposure to UVM is desired. Familiar with USB design is a plus. DV Experience: 6~10 years 薪資架構 13個月計算, RSU 另計
Hsinchu, Hsinchu City, Taiwan
4M ~ 5M TWD / year
6 years of experience required
Managing 1-5 staff
1.Micro-architecture / RTL design, simulation and verification 2.Chip integration, algorithm implementation or interface design. 3.Familiar CDC, synthesis, formality and STA flow 4. Familiar with F...
1.Micro-architecture / RTL design, simulation and verification 2.Chip integration, algorithm implementation or interface design. 3.Familiar CDC, synthesis, formality and STA flow 4. Familiar with F...
Taipei, Taiwan
1.5M ~ 2.5M TWD / year
3 years of experience required
No management responsibility
1.Creating verification plans of complex digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios. 2....
1.Creating verification plans of complex digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios. 2....
Neihu District, Taipei City, Taiwan 114, Zhubei City, Hsinchu County, Taiwan 302
3M ~ 4M TWD / year
10 years of experience required
No management responsibility