🖌SoC層級驗證的頂尖EDA 公司 - Design Verification Engineer - JL

Job updated 4 months ago

Job Description

  • Validate digital designs of extensive SoCs using advanced verification methodologies like UVM.
  • Develop reusable bus functional models, monitors, checkers, and scoreboards using coverage-driven techniques.
  • Comprehend design and implementation details, define verification scope, and establish verification infrastructure.
  • Create and execute test plans efficiently to verify designs.
  • Requirements

    • Bachelor's, Master's, or Ph.D. in Electrical Engineering, Computer Science, Computer Engineering, or related fields.
    • Background or keen interest in verification at Unit/Sub-system/SOC levels with expertise in SystemVerilog.
    • Experience with random stimulus, functional coverage, and assertion-based verification methods.
    • Proficiency in verification methodologies such as UVM/VMM and exposure to industry-standard tools for simulation and debugging.
    • Minimum of 2 years of relevant experience, whether from academia or industry.

    Prefer

    • Expertise in bus or interconnect protocols (e.g., AXI, AHB, APB) would be highly advantageous.
    • Experience in verifying complex ARM/RISC-V based systems, understanding RTL designs, and digital circuit modeling.
    • Familiarity with SystemVerilog, SystemC, and C/C++ programming languages.
    • Strong debugging and analytical skills.
    • An open-minded approach and enthusiasm for working in a dynamic and collaborative environment!
    1
    5 years of experience required
    Negotiable
    Partial Remote Work
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    Team

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