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Req ID: 130622Remote Position: NoRegion: AsiaCountry: TaiwanState/Province: TaiwanCity: TaipeiGeneral OverviewFunctional Area: Engineering Career Stream: Design Engineering Hardware IC/MGR: Individual Contributor Direct/Indirect Indicator: Indirect SummaryThe Senior Staff Engi

Req ID: 135773Remote Position: NoRegion: AsiaCountry: ThailandState/Province: ChonburiCity: Laem ChabangGeneral OverviewFunctional Area:Engineering Career Stream: Design - Software EngineeringSAP Short Name:ENG-ENG-DSEJob Level:Level 07IC/MGR: Individual Contributor Direct/Indi

Note: This is a mirrored copy of the posting from AMD's Career Page. For the official and most up-to-date listing, please refer to AMD's Career Page.---WHAT YOU DO AT AMD CHANGES EVERYTHINGAt AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. The Role:We are seeking a high-caliber FPGA Design Engineer to develop our next-generation IO-based connectivity systems. drive the design from initial concept through to hardware validation.Key Responsibilities: - System Architecture Implementation: Lead the design, documentation, and implementation of complex IO-based connectivity systems, ensuring high-speed data integrity and system reliability. - Front-End Methodology Leadership: Drive advanced RTL design flows, including resource optimization (Area/Power), multi-clock domain crossing (CDC) analysis, and reset domain crossing (RDC) strategies. - Technical Documentation Lifecycle Management: Synthesize comprehensive Requirement Specifications, Design Specs, and Test Plans. You will ensure these documents account for complex interactions between hardware, firmware, and software drivers. - Cross-Functional Collaboration: Partner closely with Architects, Hardware Engineers, and Firmware teams to define feature sets, negotiate interfaces, and ensure seamless system integration.Required Technical Qualifications: - Xilinx Expertise: Minimum of 6 years of hands-on experience in RTL design with a deep-seated understanding of AMD-Xilinx UltraScale+ FPGA architectures. - Toolchain Proficiency: Expert-level command of the Vivado Design Suite (Synthesis, Implementation, and Timing Closure). - System-Level Architecture: Proven track record with high-speed bus protocols (AXI4/AXI-Stream), memory controllers, and interconnect bridges. - High-Speed Connectivity: Direct experience implementing and debugging one or more high-speed protocols: PCIe (Gen3/4/5), 10/25/100G Ethernet, TCP/IP offload engines, or USB 3.x. - Verification Debug: Proficient in RTL simulation (Xcelium, Questa, or Vivado Simulator) and hardware-in-the-loop debugging using Xilinx ChipScope/ILA.Professional Attributes: - Ownership: A self-starting mindset with the ability to navigate ambiguity and independently drive tasks to production-ready completion. - Problem-Solving: Exceptional analytical skills for triaging complex system-level hardware/software bugs. - Communication: Ability to articulate technical trade-offs to both technical and non-technical stakeholders.Academic Credentials: - Bachelor’s or Master’s degree in electrical/computer engineering or related field preferred.Location:Taipei Taiwan#LI-VJ1 Benefits offered are described: AMD benefits at a glance.AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.This posting is for an existing vacancy.

Note: This is a mirrored copy of the posting from AMD's Career Page. For the official and most up-to-date listing, please refer to AMD's Career Page.---WHAT YOU DO AT AMD CHANGES EVERYTHINGAt AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. The Role:We are seeking a high-caliber FPGA Design Engineer to develop our next-generation IO-based connectivity systems. drive the design from initial concept through to hardware validation.Key Responsibilities: - System Architecture Implementation: Lead the design, documentation, and implementation of complex IO-based connectivity systems, ensuring high-speed data integrity and system reliability. - Front-End Methodology Leadership: Drive advanced RTL design flows, including resource optimization (Area/Power), multi-clock domain crossing (CDC) analysis, and reset domain crossing (RDC) strategies. - Technical Documentation Lifecycle Management: Synthesize comprehensive Requirement Specifications, Design Specs, and Test Plans. You will ensure these documents account for complex interactions between hardware, firmware, and software drivers. - Cross-Functional Collaboration: Partner closely with Architects, Hardware Engineers, and Firmware teams to define feature sets, negotiate interfaces, and ensure seamless system integration.Required Technical Qualifications: - Xilinx Expertise: Minimum of 6 years of hands-on experience in RTL design with a deep-seated understanding of AMD-Xilinx UltraScale+ FPGA architectures. - Toolchain Proficiency: Expert-level command of the Vivado Design Suite (Synthesis, Implementation, and Timing Closure). - System-Level Architecture: Proven track record with high-speed bus protocols (AXI4/AXI-Stream), memory controllers, and interconnect bridges. - High-Speed Connectivity: Direct experience implementing and debugging one or more high-speed protocols: PCIe (Gen3/4/5), 10/25/100G Ethernet, TCP/IP offload engines, or USB 3.x. - Verification Debug: Proficient in RTL simulation (Xcelium, Questa, or Vivado Simulator) and hardware-in-the-loop debugging using Xilinx ChipScope/ILA.Professional Attributes: - Ownership: A self-starting mindset with the ability to navigate ambiguity and independently drive tasks to production-ready completion. - Problem-Solving: Exceptional analytical skills for triaging complex system-level hardware/software bugs. - Communication: Ability to articulate technical trade-offs to both technical and non-technical stakeholders.Academic Credentials: - Bachelor’s or Master’s degree in electrical/computer engineering or related field preferred.Location:Taipei Taiwan#LI-VJ1 Benefits offered are described: AMD benefits at a glance.AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.This posting is for an existing vacancy.

1. Lidar 精密光機電產品 FPGA開發工程師- 負責開發熱成像模組與設計光達及其他精密光機電產品FPGA數位邏輯電路- 使用Verilog開發LiDAR相關功能與驗證- 根據需求開發IP及功能驗證- 熟悉Lidar、ToF、Radar相關開發經驗佳- 熟悉Thermal camera/RGB camera相關演算法開發經驗佳2. 嵌入式系統開發工程師- 負責熱成像模組或光達及其他精密光機電產品嵌入式系統相關程式開發與驗證- 具備嵌入式系統開發經驗(Linux、RTOS、Bare Metal開發經驗)- 周邊傳輸介面驅動開發經驗(MIPI、VDMA、URAT、SPI、I2C、Ethernet等)- 嵌入式系統平台整合和測試維護- 熟悉LiDAR、ToF、Radar相關開發經驗佳- 熟悉Thermal camera/RGB camera相關演算法開發經驗佳

About the Role: FPT Telecom is building the next generation of Edge AI computing solutions. We are looking for a highly skilled FPGA Engineer with specialized experience in AI Acceleration using AMD/Xilinx Versal ACAP architectures. In this role, you will bridge the gap between AI algorithms and hardware execution, developing high-performance, low-latency, and power-efficient AI accelerators for AI Server. Key Responsibilities: AI Hardware Deployment: Compile and deploy AI models (CNNs, Transformers) from frameworks (PyTorch/TensorFlow) to FPGA/SoC hardware using Vitis AI.AI Engine (AIE) Programming: Design, implement (in C/C++), and optimize parallel computing algorithms onto the AI Engine array of Xilinx Versal devices.Dataflow Optimization: Architect high-throughput data movement between Programmable Logic (PL), Processing System (PS), and AIE using AXI-Stream, DMA, and Network-on-Chip (NoC).System Integration: Collaborate with AI Engineers for model quantization (INT8/FP16) and HW Engineers to integrate custom pre/post-processing blocks (Verilog/HLS) into the system.Verification Profiling: Perform hardware-in-the-loop testing, bottleneck analysis, and profiling using Vitis Analyzer on actual evaluation boards.

職務概要：本職位負責領導硬體設計團隊，主導醫療產品（如醫療電腦、影像系統、診斷設備等）之硬體開發與設計管理。需具備深厚的硬體架構與電路設計背景，並能整合跨部門資源，確保產品符合醫療法規、品質與可靠性要求，同時達成專案時程與成本目標。主要工作內容：【專案開發管理】1. 負責醫療產品硬體開發專案之整體規劃、執行與追蹤（從概念設計至量產）。2. 制定專案時程、預算與資源配置，確保開發進度及品質目標達成。3. 與機構、韌體、軟體、品質與法規團隊協同合作，推動跨部門整合。【硬體設計與技術指導】1. 主導系統架構設計、電路設計審查、Layout Review 及整機驗證。2. 提升團隊在 EMC/ESD、Signal Integrity、Power Management、Thermal Simulation 等核心設計能力。3. 審查設計文件（Schematic、BOM、DFM/DFT、FMEA、Verification Plan）並確保文件完整性。【醫療法規與產品可靠性】 1. 確保產品符合醫療相關標準（IEC 60601、ISO 13485、EMC/ESD 要求）。2. 參與並監督 DVT/PVT 等設計驗證流程，確保設計品質與法規一致性。【團隊領導與人才發展】1. 帶領並培育硬體設計工程師團隊，建立標準化的設計流程與文件管理制度。2. 推動技術交流與內部培訓，持續提升團隊技術競爭力。【外部合作與供應鏈管理】1. 管理 ODM/OEM 合作夥伴與關鍵零件供應商，確保設計、成本與品質一致性。必要條件：1. 電子工程、電機工程、通訊工程或相關科系學士以上(碩士尤佳)。2. 15 年以上硬體設計與開發經驗，其中 5 年以上管理或專案領導經驗。3. 具醫療設備、工業電腦或高可靠度產品開發背景者尤佳。專業技能：1. 精通高速介面設計（PCIe、DDR、USB、Ethernet 等）。2. 熟悉 EMC/ESD 設計、電源管理與熱設計分析。3. 熟悉醫療安規（IEC 60601 系列）與設計流程（ISO 13485）。4. 熟悉 PLM 系統、Cadence Allegro、OrCAD CIS 等設計與管理工具。軟性條件：1. 具跨部門溝通與問題解決能力。2. 能以結果導向推動專案並領導團隊。3. 英文讀寫流暢，能與國際客戶及供應商溝通。加分條件：1. 具 FPGA、RISC、AI 加速器模組或影像處理硬體開發經驗。2. 曾參與醫療產品安規認證（如 CE、FDA、UL）流程。3. 具設計驗證與量產導入（NPI）管理經驗。

ORAN O-RU and gNB PHY 軟體開發

We are seeking a PCB Hardware Design Engineer to participate in the design, development, and testing of FPGA-based signal processing systems for defense applications.Key responsibilities: Designing signal processing boards using Xilinx RFSoC Gen3 with integrated high-speed ADC/DAC. Developing schematics and multi-layer PCB layouts in compliance with VPX military/industrial standards. Integrating high-speed interfaces such as Ethernet, JESD204B/C, PCIe, UART, USB, CAN, I2C, RS422, RAM, and Flash memory. Designing power architecture, including power trees and power supply circuits for FPGA systems (Power Management, Switching Regulators, LDOs, etc.). Creating and managing BOMs, and working with manufacturers to ensure product quality and fabrication/assembly readiness. Collaborating closely with system, FPGA, embedded software, and mechanical teams to ensure cohesive design integration. Participating in board bring-up, signal validation, performance evaluation, and debugging using tools such as oscilloscopes, logic analyzers, and DMMs. Supporting final system integration, field testing, troubleshooting, and performance optimization. 1. BE A CHIP MAKER - NOT JUST A CODER Full-Flow Ownership: Take ownership of the entire design lifecycle. You will not just write code; you will work closely with Architecture, DV, PD, DFT, and Power teams to bring a Large-Scale SoC from concept to Tape-out. Cutting-Edge Tech: Work on advanced ASIC IP-based architectures for AI Smart Camera applications. Handle sophisticated sub-systems and internal/external IP integration. Impactful Work: Develop methodology, flows, and checks that ensure our chips deliver the highest quality and efficiency (TOPs/Watt). 2. TOP-TIER BENEFITS CARE Competitive Package: Attractive salary + 13th-month salary + Performance-based bonuses. Premium Healthcare: Exclusive FPT Care insurance package (covering you and your family) with access to top international hospitals. Annual high-quality health check-ups. Work-Life Balance: Full compliance with Labor Law, generous leave policies, and care for employees' spiritual lives. 3. DYNAMIC ENVIRONMENT GROWTH Vibrant Culture: Join a friendly, open team with the unique "STCo" culture. Enjoy exciting activities: Teambuilding, Company Trips, Talent Shows (Sao Choi), Festivals, and more! Career Path: Clear roadmap for promotion and technical development. Work with modern facilities and high-quality equipment. Exclusive Perks: Special discounts on FPT Telecom FPT ecosystem services.

Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 8 years of experience with digital logic design principles, RTL design concepts, and languages, such as Verilog or SystemVerilog. 8 years of experience with multiple IPs/SoCs with silicon success. Experience with logic synthesis techniques to optimize RTL code, performance and power, as well as low-power design techniques. Preferred qualifications: Master's or PhD degree in Electrical Engineering, Computer Engineering or Computer Science. Experience with a scripting language like Perl or Python. Experience with ASIC or FPGA design verification, synthesis, timing/power analysis, and DFT. Knowledge of high-performance and low-power design techniques, assertion-based formal verification, FPGA and emulation platforms, and SOC architecture. Knowledge of memory compression, fabric, coherence, cache, or DRAM. About the jobBe part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.Responsibilities Define the block-level design document (e.g., interface protocol, block diagram, transaction flow, pipeline, etc.). Perform RTL coding, function/performance simulation debug, and Lint/Clock Domain Crossing (CDC)/Formal Verification (FV)/Unified Power Format (UPF) checks. Participate in synthesis, timing/power closure, and FPGA/silicon bring-up. Participate in test plan and coverage analysis of the block and ASIC-level verification. Communicate and work with multi-disciplined and multi-site teams. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.