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PURPOSE AND SCOPE OF ROLE: We’re looking for a Senior 3D Designer with solid experience in event activation, someone who can handle concepts, survive tight deadlines, and understands what it means to design for real-world execution. This is not a role for someone who only creates nice-looking 3D renders. You’ll be involved from concept → execution → real-life deployment. KEY RESPONSIBILITIES Take primary responsibility for 3D designs across assigned projects, including but not limited to: event booths, entrance gates, photobooths, decoration areas, overall master event layouts, and exhibition stands.Build and render high-quality, creative 3D visualizations that accurately reflect the spirit of the concept, client requirements, and project goals.Work closely with Creative and Account teams to receive ideas/concepts and execute 3D designs for campaigns;Production teams/vendors to supervise and ensure the actual onsite build perfectly matches the approved 3D visualization.Proactively propose solutions for space, structure, and materials to optimize both the design aesthetics and production costs.Support 2D design tasks when necessary (if any).

We’re looking for a Senior 2D Designer with solid experience in event activation, someone who can handle concepts, survive tight deadlines, and understands what it means to design for real-world execution. This is not a role for someone who only creates nice-looking artworks. KEY RESPONSIBILITIES Join brainstorming sessions and develop concepts key visuals for event / activation projects.Execute 2D designs for: Booths, stages, backdrops, entrance gates; POSM, OOH, activation materials; Visual guidelines for production installationWork closely with: Account / Planner to fully understand the brief; 3D Designers to align visual concepts with spatial design; Production teams / vendors to ensure designs are feasible for fabricationMaintain design quality from concept to final artwork and printing.Proactively propose solutions when briefs change or timelines are tight.Support and review junior designers’ work (if any).

Develop SI and PI design for server/storage/communication products. Major works are to serve as the signal integrity analyst and designer provides the support to internal team, suppliers, and customers to deliver the new products. Job Responsibilities: • PCB material choosing and stack-up definition. • 3D passive channel modeling, perform SerDes channel extraction using electromagnetic tools. • Perform signal integrity pre-layout and post-layout analysis in RD phase. • Perform static timing and signal integrity analysis of parallel (common clock, source-synchronous) interfaces. • Design and analysis of multi-gigabit serial links, including lab verification and tuning. • Perform power integrity analysis on power delivery network. • Generate and verify PCB layout rules, manage constraints for PCB layout. • Work directly with ASIC and PCB design teams to evaluate design tradeoffs and optimize design performance / risk / cost / manufacturability. • Cooperate with RD team and signal test engineers on debugging, failure analysis and fixing issues discovered during test. • Be familiar with SAS, PCIe, DDR3/4, 25G/56G Ethernet specification is a plus.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.Role Overview Astera Labs is establishing a strategic RD center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a highly skilled Physical Design CAD Engineer specializing in CAD Extraction to join our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful technical ownership in a new site, implementing the parasitic extraction (PEX) methodologies and flows for chips that power the world's largest AI clusters. As a foundational member of the team, you will be responsible for the accuracy and efficiency of our extraction environment, ensuring that our high-speed designs are modeled with the highest precision from RTL to GDSII. Key Responsibilities Develop, qualify, and maintain automated RC extraction flows for high-performance AI SoCs Own the setup and validation of foundry technology files (e.g., StarRC/Quantus techfiles, TLU+, ITF) across various process corners Perform correlation studies between different extraction tools and 3D field solvers (e.g., Raphael, QuickCap) to ensure modeling accuracy Collaborate closely with the Signal Integrity (SI) and Power Integrity (PI) teams to provide accurate parasitic data for critical high-speed nets and power grids Implement automated scripts (Tcl/Python) to streamline extraction regressions, data parsing, and PEX-to-STA (Static Timing Analysis) handoffs Analyze the impact of layout effects (LDE) and parasitics on timing and power, providing feedback to the implementation team to optimize PPA Interface with EDA vendors and foundries to resolve extraction tool bugs and methodology gaps related to advanced nodes (5nm/3nm) Basic Qualifications Bachelor’s degree in Electrical Engineering or a related technical field 5+ years of hands-on experience in Physical Design CAD or Physical Verification with a heavy focus on parasitic extraction Expert proficiency with industry-standard extraction tools such as Synopsys StarRC, Cadence Quantus (QRC), or Siemens Calibre xACT Strong scripting skills in Tcl and Python for flow automation and database manipulation Deep understanding of semiconductor physics, interconnect modeling, and the impact of parasitics on timing, EM (Electromigration), and IR drop Proven experience in validating tech files and running extraction for complex, multi-million gate designs Preferred Experience Hands-on experience with 5nm, 3nm, or more advanced process nodes, including FinFET-specific extraction challenges Familiarity with 3D field solvers and their use in benchmarking standard extraction engines Knowledge of Netlist formats (SPEF, DSPF) and their integration into STA and Spice simulation flows Experience with compute farm management (LSF/Slurm) and version control (Git) We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.Job Description: As a Principal Package Signal Power Integrity Engineer at Astera Labs, you will serve as a senior technical leader responsible for architecting, optimizing, and signing off package SIPI solutions for next-generation connectivity products. You will drive package electrical architecture across high-performance IC packaging platforms, including FCBGA, coreless substrates, chiplet-based packages, 2.5D/3D integration, silicon interposers, bridge-based interconnect, and heterogeneous multi-die systems. In this role, you will lead SIPI strategy and execution for products supporting PCIe, CXL, Ethernet, 200G/400G+ SerDes, and die-to-die interconnect. You will partner closely with silicon architecture, SerDes/IP teams, package design, PCB design, hardware validation, manufacturing, substrate vendors, and OSAT partners to optimize signal integrity, power delivery, substrate/interposer routing, bump planning, and system-level electrical performance while balancing cost, manufacturability, reliability, yield, and schedule. You will also drive SIPI methodology, modeling standards, simulation-to-measurement correlation, and chip–package–board co-design frameworks to enable scalable execution across multiple product lines. Key Responsibilities Define package SIPI architecture and design strategy for high-performance connectivity products, including PCIe 5.0/6.0/7.0, CXL, Ethernet, 200G/400G+ SerDes, and die-to-die interconnect. Perform package and system-level SI and PI simulations using industry-standard simulation software such as HFSS, SIwave, and Keysight ADS to develop, optimize, and sign off package electrical models, validate package architecture and designs, and ensure robust signal and power integrity across chip–package–board systems. Lead cross-functional execution across silicon team, package design, marketing and APPs, PCB board team, validation team, package manufacturing, and external substrate/OSAT partners, managing technical tradeoffs among SIPI performance, cost, DFM, yield, etc., and deliver packaging solutions on schedule. Drive simulation-to-measurement correlation strategy, ensuring strong alignment between EM extraction, system-level models, and lab validation (VNA, TDR, high-speed oscilloscope), continuously improving model accuracy, simulation efficiency, and SIPI signoff criteria. Own SIPI simulation and signoff for advanced packaging platforms, including chiplet-based packages, 2.5D/3D integration, silicon interposers, and bridge-based interconnect, by leading simulations for D2D interconnect (e.g., UCIe), multi-die PDN, micro-bump modeling, TSV/interposer modeling, and multi-die CPM co-simulation. Define substrate, interposer, and bridge routing guidelines for high-speed SerDes and D2D interfaces, including impedance targets, differential-pair geometry, via/transition optimization, return-current management, shielding, skew control, and crosstalk isolation. Establish SIPI modeling standards, design rules, review checklists, automation flows, and signoff methodologies to improve execution efficiency, while mentoring engineers across the organization. Required qualifications: 10+ years of experience in signal integrity, power integrity, package electrical design, or chip–package–board co-design for high-performance semiconductor products. Deep expertise in package SIPI modeling, analysis, optimization, and signoff across the chip–package–board system, for high-speed SerDes, PCIe, CXL, Ethernet, etc. Strong experience with PCIe 5.0/6.0, PAM4 SerDes channel design, high-speed S-parameter extraction, package model development, eye-diagram analysis, return/insertion-loss optimization, and crosstalk analysis. Proven track record delivering high-performance packages using FCBGA, FCCSP, coreless substrates, advanced organic substrates, chiplet-based packages, 2.5D integration, silicon interposers, or heterogeneous integration platforms. Hands-on expertise with EM extraction and SIPI simulation tools such as ANSYS HFSS, SIwave, Q3D, 3D Layout, Keysight ADS, Cadence Sigrity, or equivalent tools. Expert-level knowledge of PDN design, including DC IR drop, AC impedance, target impedance, loop inductance, decoupling optimization, transient response, noise coupling, and chip-package-model methodology. Demonstrated ability to correlate simulation to lab measurement (VNA, TDR, high-speed oscilloscope). Strong understanding of tradeoffs between SIPI performance, cost, reliability, and manufacturability. Experience leading vendor engagements and managing technical execution through production ramps. Preferred Qualifications: Experience influencing silicon floor planning, bump map definition, SerDes and power-grid planning, package escape strategy, and PCB breakout from a SIPI perspective. Experience with automation and scripting for SIPI modeling flow. Exposure to Allegro Package Designer (APD) for hands-on substrate editing. Knowledge on traditional FCBGA type package and advanced package (chiplet/2.5D/3D) manufacturing and assembly process flows Experience with CPO and NPO optical package SIPI design, including high-speed channel modeling between EIC/PIC/optical engine, PDN design, crosstalk/noise analysis, and chip–package–board co-design for optical connectivity applications. The base salary range is $203,000 USD – $230,000 USD. Your base salary will be determined based on location, experience, and employees' pay in similar positions.We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.At Astera Labs, we seek motivated Principal Signal and Power Integrity Engineers to work on our game-changing portfolio of connectivity products for Artificial Intelligence and Machine Learning applications. In this role, you will execute the SI planning, design, modeling, simulation, and lab validation with various system configurations. This position will be onsite. Basic Qualifications Strong academic/technical background in electrical engineering; Bachelor’s is required; Master’s preferred. 8+ years of experience supporting or developing complex SoC/silicon products for Server and Networking applications. 8+ years of hands-on high-speed SI/PI design, simulation, and measurement experience. Have a proven track record with defining hardware system constraints and high-speed technology roadmaps. Cross-functional design mentality with the electrical design community to develop systems. Self-starting, professional, and hands-on work ethic that can execute intense research in a dynamic environment. Proven track record solving problems independently, preferably as a tech lead. Entrepreneurial, open-minded behavior, and can-do attitude. Authorized to work in the US and start immediately. Required Experience Familiar with SI and PI design challenges for PCIe Gen5/6 and/or 224/448G Ethernet PCB and interconnects 2D and 3D EM simulation experience with Cadence/Ansys/ADS/etc. toolsets EM modeling of BGA and connector structures High-speed SERDES channel simulation, and equalization PI simulations with Ansys/Cadence toolsets Familiar with VNA, TDR, real-time and sub-sampling oscilloscopes, etc. Working knowledge of PCB fabrication limits and trade-offs Familiar with industry-standard such as PCI-SIG, and IEEE802.3, especially Electrical sections. Strong debugging, analysis, and problem-solving skills with experience leading root cause and correction action teams. An inherent sense of urgency and accountability. Must have the ability to multi-task in a fast-paced environment. Your base salary will be determined based on your experience and the pay of employees in similar positions. The base salary range is $203,000 USD - $230,000 USD for Principal level, and $237,500 USD - $250,000 USD for Senior Principal level. The actual level is to be determined by the years of experience and interview outcome.We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Google welcomes people with disabilities.Minimum qualifications: Bachelor's degree in a technical field, or equivalent practical experience. 5 years of experience in program management. 5 years of relevant process, research, or product development experience involving electro-mechanical products. Experience with manufacturing process or fixture development and validation experience. Experience with new product introduction, process management and contract manufacturing experience, and experience with design for assembly and failure analysis experience. Preferred qualifications: Master’s degree in mechanical engineering, industrial engineering, a related technical field, or equivalent practical experience. 10 years of relevant process, research, or product development experience involving electro-mechanical products. Experience in one or more of the following subject matter areas: automation, adhesives, leak testing, sealing and waterproofing, lean manufacturing, manufacturing process layout and optimization. Experience with manufacturing process or fixture development, and validation experience. High-volume and high-precision consumer electronics experience. Knowledge of generating functional requirements specifications and knowledge of tolerance analysis, 3D modeling, CAD Systems. About the jobA problem isn’t truly solved until it’s solved for all. That’s why Googlers build products that help create opportunities for everyone, whether down the street or across the globe. As a Technical Program Manager at Google, you’ll use your technical expertise to lead complex, multi-disciplinary projects from start to finish. You’ll work with stakeholders to plan requirements, identify risks, manage project schedules, and communicate clearly with cross-functional partners across the company. You're equally comfortable explaining your team's analyses and recommendations to executives as you are discussing the technical tradeoffs in product development with engineers. Googles mission is to organize the worlds information and make it universally accessible and useful. Our Devices Services team combines the best of Google AI, Software, and Hardware to create radically helpful experiences for users. We research, design, and develop new technologies and hardware to make our users interaction with computing faster, seamless, and more powerful. Whether finding new ways to capture and sense the world around us, advancing form factors, or improving interaction methods, the Devices Services team is making peoples lives better through technology.Responsibilities Drive product definition and architecture selection, in collaboration with design and ID teams, via early DFx engagement in areas such as precision electronic assembly, automation, sealing, adhesives, metal fabrication and finishing, injection molding, display design, PCBA design and fabrication, and leak testing. Conduct identification, investigation, analysis, and integration of new manufacturing processes, technology, and equipment in support of program objectives. Drive manufacturing process and fixture development, in collaboration with manufacturing partners, by identifying functional requirements, researching, designing, modifying, and testing manufacturing methods and equipment, and conferring with equipment providers. Lead improvement of manufacturing efficiency via analysis and planning of work flow, space requirements, production capacity, and equipment layout. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.

Google will be prioritizing applicants who have a current right to work in Singapore, and do not require Google's sponsorship of a visa.Minimum qualifications: Bachelor's degree in Mechanical Engineering, Electrical Engineering or IT Engineering, or equivalent practical experience. 5 years of experience working with external telecom vendors on telecom products. Preferred qualifications: Master's degree in Mechanical or Electrical or IT engineering. 6 years of experience as a Registered Communications Distribution Designer (RCDD) Certified professional with ICT/telecom scope within mechanical and electrical data center products. 6 years of experience as key contributor on ICT/telecom scope within mechanical and electrical data center products Experience with Autodesk Revit or other 3D modeling software developing telecom rack and tray layouts. Ability to travel to visit data center sites or manufacturing partners. About the jobOur thirst for technology is a part of everything we do. The Data Center Engineering team takes the physical design of our data centers into the future. Our lab mirrors a research and development department -- cutting-edge strategies are born, tested and tested again. Along with a team of great minds, you take on complex topics like how we use power or how to run state-of-the-art, environmentally-friendly facilities. You're a visionary who optimizes for efficiencies and never stops seeking improvements -- even small changes that can make a huge impact. You generate ideas, communicate recommendations to senior-level executives and drive implementation alongside facilities technicians. The Data Center Design Integration team is a multi disciplinary team of architects and Information and Communication Technology (ICT)/Telecommunications (Telecom) designers that work on next generation data center designs. We are a sub-team of the broader Data Center Technology and Systems (DCTS) organization.As a Telecom Lead, you will be responsible for working with executive level engineers across all disciplines to develop integrated telecom communication designs at the product and top level assembly state of a data center. You will lead external consultants to develop coordinated construction level drawing packages for manufacturing and construction.The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide. We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.Responsibilities Work with internal telecom engineers and network designers to rationalize requirements into products, conceptual one lines and conceptual rack or tray layouts to enable adequate telecom infrastructure. Work with cross-functional disciplines across architecture, civil, mechanical, electrical, controls, security on product development, and assembly integration of telecom infrastructure. Participate in internal and external ICT/telecom product and data center design reviews across the following disciplines: Telecom, Security, Controls and Networking. Review construction level drawings produced by internal and external vendors that document ICT/telecom scope for program reference. Review and enable best practices for converged network allocations across all mechanical, electrical, and controls products. Act as an escalation path for site localization of canonical design where local requirements necessitate engineering judgement on adjustments to ICT/telecom design. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.Role Overview As a Principal Package Thermal Mechanical Engineer at Astera Labs, you will serve as a technical leader driving the development and modeling of advanced IC packaging solutions that enable next-generation AI and high-performance connectivity systems. In this highly visible role, you will define and execute thermal and mechanical modeling strategies across the chip–package–board system, influencing package architecture, material selection, and reliability design. You will partner closely with package design, SIPI, silicon, system, and manufacturing teams to ensure robust thermal/mechanical performance and first-pass success. You will also drive modeling methodologies, correlation strategies, and best-known methods (BKMs), while engaging directly with customers to translate complex simulation insights into actionable system-level solutions. Key Responsibilities Thermal Mechanical Modeling Leadership Define and drive thermal and mechanical modeling strategies for advanced packages (FCBGA, FCCSP, multi-die, and chiplet-based architectures) Perform detailed thermal simulations including steady-state and transient heat transfer (conduction, convection, and interface resistances such as TIM1/TIM2) Develop and deploy compact thermal models (CTM), reduced-order models (ROM), and DELPHI-based models for system-level integration Analyze power density, hotspot behavior, and package-to-system thermal interactions across air and liquid cooling environments Perform thermo-mechanical stress/strain analysis including CTE mismatch, viscoelastic material behavior, and deformation Predict package warpage across process and use conditions (reflow, underfill cure, board attach, field operation) Model solder joint reliability and fatigue using industry standard models Package Architecture Thermal Design Strategy Drive package design decisions including material selection (EMC, substrate, TIM, lid/heat spreader), thermal path optimization, and early-stage architecture definition across air and liquid cooling solutions (air, cold plate, CPO/CPC) Conduct DOE, sensitivity studies, and worst-case analysis to guide tradeoffs across performance, cost, reliability, and manufacturability System Co-Design Automation Partner cross-functionally to drive chip–package–board co-design and resolve system-level thermal/mechanical challenges, including system integration constraints Serve as a technical interface for customers and internal teams, translating modeling results into actionable insights and leading design reviews and issue resolution Develop and scale modeling methodologies, workflows, and BKMs; mentor engineers and improve efficiency through automation and scripting (Python, MATLAB) Basic Qualifications M.S. or Ph.D. in Mechanical Engineering, Materials Science, Electrical Engineering, or related field 8+ years of experience in semiconductor packaging with strong focus on thermal and mechanical modeling Deep expertise in thermal modeling and simulation, including steady-state and transient analysis, compact thermal modeling (CTM), DELPHI methodology, and system-level thermal integration using tools such as ANSYS Icepak, Flotherm, or equivalent Deep expertise in thermo-mechanical modeling and FEA simulation, including stress/strain analysis, warpage prediction, and reliability modeling (BLR/CLR), using tools such as ANSYS Mechanical, or equivalent Proven ability to correlate simulation results with lab measurements Experience influencing package design and delivering solutions to production Strong cross-functional collaboration across package design, SIPI, system, and manufacturing teams Preferred Qualifications Experience with high-power AI / HPC packages and large FCBGA (50mm) Familiarity with advanced packaging technologies:2.5D / 3D integration, Chiplet, CPO/CPC Experience with system-level cooling solutions: Liquid cooling, cold plates, immersion cooling Knowledge of JEDEC standards and reliability qualification methodologies Experience working with OSATs and substrate vendors on thermal/mechanical design optimization Proficiency in scripting (Python, MATLAB) for modeling automation Exposure to multi-physics coupling (electrical–thermal–mechanical interactions) The base salary range is $185,000 USD – $230,000 USD. Your base salary will be determined based on location, experience, and employees' pay in similar positions.We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Introduction to the jobAre you challenged by the engineering of high-tech semiconductor equipment products? And you areaMechanical Developerwith experience inequipment design, cost of good reduction, mechatronics, and tooling design projects? You’d better contact us today!We at the Business-Line DUV IBE (Installed Base Extensions) support the Life-Time Extension of the PAS 5500 systems,the200mmwafer Lithography systems of ASML. And the XT-1-2-3, the firstgenerations300mmwafer Lithography systems. We provide refurbished systems, upgrades,spare-partsand service to our customers.Our Design Engineering team of around 50 engineersislocatedpartly in the Netherlandsand partly in Taiwan. Weensurethelong-term availability of parts,modulesand knowledgeof thePAS 5500 and XT-1-2-3platform to enablerefurbishment,upgradeand service business.Role and responsibilitiesContribute to the development of the PAS5500 product line by re-designing, creating and testing sub-modules, within the restrictions imposed by system specifications, costs and planning considerations.Manage the Development Projects (including supplier transfer activities) by co-working with Internal/External stakeholders and integrate the solutions into PAS5500 systems.Perform (re-)design of mechanical layout, tooling, and mixed pneumatic/mechatronic modules with quality.Specify, re-design, replace critical components, integrate, qualify and optimize mechanical aspects of the PAS 5500 modules in order to meet the system performance.Define test specifications and ensure that prototypes are built and tested accordingly.Lead the mechanical aspects related to repairs and refurbishment of PAS systems and trouble shooting, resulting in both quick fixes and structural solutions.Support the Manufacturing and Customer Support organization to meet the output and quality requirements and high end trouble shooting.Introduce the Engineering Change to Manufacturing and Customer Support organization and also support the Supplier to meet the output and quality requirements.Responsible for the technical product documentation using 3D modeling, BOM structures, and design documents in order to unambiguously explain the design to suppliers.Fulfill a technology bridging position between ASML and suppliers/customers.Co-operate with multi-sectors (ex, CS, PE, SCE and logistics) is required in daily work and also possibly co-work with worldwide ASML colleague and external sectors.Education and experienceBachelor/ Master degree in Engineering with 5 years of working experience in technical areas and project management experienceMechanical design of small modules, welded frame/covers, or toolsBoth 3D/2D modeling and drafting experience for mono parts and assembliesModule concept design to prototype and testInvestigate design or manufacturing issues and provide solutions to end customersConvert design specifications into element/module designsRealize design to manufacturing with suppliers.Able to do basic mechanic statics calculation analysis. To have the Finite Element Analysis experience is advantages.Experience in system/module and mechatronics design experiences are advantageous.Experience in lifting and hoisting tool design experience is advantageous. Experience in Quality Efficiency (including cost reduction) improvement projects in both the production - and development environment are an advantage.SkillsWorking at the cutting edge of technology means constant challenges and meaningful problem‑solving. Here, you won’t work in a silo—you’ll collaborate in a creative, supportive, and dynamic environment that values diverse perspectives. You’ll also have the flexibility and trust to choose the best way to tackle your tasks.To excel in this role, you should have:Strong root‑cause analysis skills and the ability to drive solutionsSolid analytical thinking with a practical mindsetA collaborative attitude and the ability to work effectively across culturesA proactive, hands‑on approach with a get‑things‑done mentalityStrong communication and interpersonal skills, with professionalism at all levelsComfort working in ambiguityAccurate, independent, and structured work habitsA strong sense of urgency and excellent prioritization skillsCreativity and out‑of‑the‑box thinkingGood English and Mandarin proficiencyDiversity InclusionASML is an Equal Opportunity Employer that values and respects the importance of a diverse and inclusive workforce. It is the policy of the company to recruit, hire, train and promote persons in all job titles without regard to race, color, religion, sex, age, national origin, veteran status, disability, sexual orientation, or gender identity. We recognize that diversity and inclusion is a driving force in the success of our company.Other informationBusiness Line DUV IBE is responsible for the entire installed base of PAS 5500 steppers and scanners as well as the life-extension for XT-1-2-3 systems. The BL DUV IBE DE team delivers the structural solutions to support both platforms.This position requires access to controlled technology, as defined in the United States Export Administration Regulations (15 C.F.R. § 730, et seq.). Qualified candidates must be legally authorized to access such controlled technology prior to beginning work. Business demands may require ASML to proceed with candidates who are immediately eligible to access controlled technology.Inclusion and diversityASML is an Equal Opportunity Employer that values and respects the importance of a diverse and inclusive workforce. It is the policy of the company to recruit, hire, train and promote persons in all job titles without regard to race, color, religion, sex, age, national origin, veteran status, disability, sexual orientation, or gender identity. We recognize that inclusion and diversity is a driving force in the success of our company.Need to know more about applying for a job at ASML? Read our frequently asked questions.