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PURPOSE AND SCOPE OF ROLE: We’re looking for a Senior 3D Designer with solid experience in event activation, someone who can handle concepts, survive tight deadlines, and understands what it means to design for real-world execution. This is not a role for someone who only creates nice-looking 3D renders. You’ll be involved from concept → execution → real-life deployment. KEY RESPONSIBILITIES Take primary responsibility for 3D designs across assigned projects, including but not limited to: event booths, entrance gates, photobooths, decoration areas, overall master event layouts, and exhibition stands.Build and render high-quality, creative 3D visualizations that accurately reflect the spirit of the concept, client requirements, and project goals.Work closely with Creative and Account teams to receive ideas/concepts and execute 3D designs for campaigns;Production teams/vendors to supervise and ensure the actual onsite build perfectly matches the approved 3D visualization.Proactively propose solutions for space, structure, and materials to optimize both the design aesthetics and production costs.Support 2D design tasks when necessary (if any).

We’re looking for a Senior 2D Designer with solid experience in event activation, someone who can handle concepts, survive tight deadlines, and understands what it means to design for real-world execution. This is not a role for someone who only creates nice-looking artworks. KEY RESPONSIBILITIES Join brainstorming sessions and develop concepts key visuals for event / activation projects.Execute 2D designs for: Booths, stages, backdrops, entrance gates; POSM, OOH, activation materials; Visual guidelines for production installationWork closely with: Account / Planner to fully understand the brief; 3D Designers to align visual concepts with spatial design; Production teams / vendors to ensure designs are feasible for fabricationMaintain design quality from concept to final artwork and printing.Proactively propose solutions when briefs change or timelines are tight.Support and review junior designers’ work (if any).

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.Role Overview Astera Labs is establishing a strategic RD center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a highly skilled Physical Design CAD Engineer specializing in CAD Extraction to join our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful technical ownership in a new site, implementing the parasitic extraction (PEX) methodologies and flows for chips that power the world's largest AI clusters. As a foundational member of the team, you will be responsible for the accuracy and efficiency of our extraction environment, ensuring that our high-speed designs are modeled with the highest precision from RTL to GDSII. Key Responsibilities Develop, qualify, and maintain automated RC extraction flows for high-performance AI SoCs Own the setup and validation of foundry technology files (e.g., StarRC/Quantus techfiles, TLU+, ITF) across various process corners Perform correlation studies between different extraction tools and 3D field solvers (e.g., Raphael, QuickCap) to ensure modeling accuracy Collaborate closely with the Signal Integrity (SI) and Power Integrity (PI) teams to provide accurate parasitic data for critical high-speed nets and power grids Implement automated scripts (Tcl/Python) to streamline extraction regressions, data parsing, and PEX-to-STA (Static Timing Analysis) handoffs Analyze the impact of layout effects (LDE) and parasitics on timing and power, providing feedback to the implementation team to optimize PPA Interface with EDA vendors and foundries to resolve extraction tool bugs and methodology gaps related to advanced nodes (5nm/3nm) Basic Qualifications Bachelor’s degree in Electrical Engineering or a related technical field 5+ years of hands-on experience in Physical Design CAD or Physical Verification with a heavy focus on parasitic extraction Expert proficiency with industry-standard extraction tools such as Synopsys StarRC, Cadence Quantus (QRC), or Siemens Calibre xACT Strong scripting skills in Tcl and Python for flow automation and database manipulation Deep understanding of semiconductor physics, interconnect modeling, and the impact of parasitics on timing, EM (Electromigration), and IR drop Proven experience in validating tech files and running extraction for complex, multi-million gate designs Preferred Experience Hands-on experience with 5nm, 3nm, or more advanced process nodes, including FinFET-specific extraction challenges Familiarity with 3D field solvers and their use in benchmarking standard extraction engines Knowledge of Netlist formats (SPEF, DSPF) and their integration into STA and Spice simulation flows Experience with compute farm management (LSF/Slurm) and version control (Git) We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

About CelesticaCelestica (NYSE, TSX: CLS) enables the world’s best brands. Through our recognized customer-centric approach, we partner with leading companies in Aerospace and Defense, Communications, Enterprise, HealthTech, Industrial, Capital Equipment and Energy to deliver solutions for their most complex challenges. As a leader in design, manufacturing, hardware platform and supply chain solutions, Celestica brings global expertise and insight at every stage of product development – from drawing board to full-scale production and after-market services for products from advanced medical devices, to highly engineered aviation systems, to next-generation hardware platform solutions for the Cloud. Headquartered in Toronto, with talented teams spanning 40+ locations in 13 countries across the Americas, Europe and Asia, we imagine, develop and deliver a better future with our customers.Job Summary The Staff Engineer, Mechanical Design develops new mechanical systems/modules and maintains existing designs. Research mechanical concepts and create system solutions using 3D modeling and simulation software. Complete calculations and test, validate, and qualify their systems and make adjustments as needed. Provide support throughout the manufacturing process of the mechanical system that they have designed.The Staff Engineer, Mechanical Design works with cross functional teams of other engineers, customers, supply chain and project leadership to ensure robust and high quality product development. Enhance designs with feedback from reviews in areas such as manufacturing, test, supply chain, reliability, industrial design and simulations.Detailed Description Performs tasks such as, but not limited to, the following: Lead the design, development and implementation of technical solutions for complex projects, involving multiple domains. Participate in project planning and scheduling.Provide technical leadership and direction to a sizable team of engineers. May be a recognized expert (go to person) in one or more technical areasTake responsibility for non-technical elements of an engineering project (people, financials etc.).Review and interpret customer requirements/specifications and may act as primary customer contract.Analyze trade-offs in complex systems and recommend solutions. Develops deployment strategies and plans.Lead the deployment of strategic complex programs and coordinate site-wide deployment efforts.May manage relationships with key vendors/partners.Prepare calculations on the proposed solution before completing technical drawingsDesign, modify and implement systems that meet customer and Celestica needs. E.g. Sketch and draw up designs using input from other engineers, requirements and input from design review (DFx) teamCreate designs in line with company procedure, regulations and client standardsSubmit drawings to management, engineering teams and customers for review.Use customer feedback and data to upgrade, improve or repair the company's existing machinesProvide support during the manufacturing processFinalize designs and send prints to the production department

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.Job Description: As a Principal Package Signal Power Integrity Engineer at Astera Labs, you will serve as a senior technical leader responsible for architecting, optimizing, and signing off package SIPI solutions for next-generation connectivity products. You will drive package electrical architecture across high-performance IC packaging platforms, including FCBGA, coreless substrates, chiplet-based packages, 2.5D/3D integration, silicon interposers, bridge-based interconnect, and heterogeneous multi-die systems. In this role, you will lead SIPI strategy and execution for products supporting PCIe, CXL, Ethernet, 200G/400G+ SerDes, and die-to-die interconnect. You will partner closely with silicon architecture, SerDes/IP teams, package design, PCB design, hardware validation, manufacturing, substrate vendors, and OSAT partners to optimize signal integrity, power delivery, substrate/interposer routing, bump planning, and system-level electrical performance while balancing cost, manufacturability, reliability, yield, and schedule. You will also drive SIPI methodology, modeling standards, simulation-to-measurement correlation, and chip–package–board co-design frameworks to enable scalable execution across multiple product lines. Key Responsibilities Define package SIPI architecture and design strategy for high-performance connectivity products, including PCIe 5.0/6.0/7.0, CXL, Ethernet, 200G/400G+ SerDes, and die-to-die interconnect. Perform package and system-level SI and PI simulations using industry-standard simulation software such as HFSS, SIwave, and Keysight ADS to develop, optimize, and sign off package electrical models, validate package architecture and designs, and ensure robust signal and power integrity across chip–package–board systems. Lead cross-functional execution across silicon team, package design, marketing and APPs, PCB board team, validation team, package manufacturing, and external substrate/OSAT partners, managing technical tradeoffs among SIPI performance, cost, DFM, yield, etc., and deliver packaging solutions on schedule. Drive simulation-to-measurement correlation strategy, ensuring strong alignment between EM extraction, system-level models, and lab validation (VNA, TDR, high-speed oscilloscope), continuously improving model accuracy, simulation efficiency, and SIPI signoff criteria. Own SIPI simulation and signoff for advanced packaging platforms, including chiplet-based packages, 2.5D/3D integration, silicon interposers, and bridge-based interconnect, by leading simulations for D2D interconnect (e.g., UCIe), multi-die PDN, micro-bump modeling, TSV/interposer modeling, and multi-die CPM co-simulation. Define substrate, interposer, and bridge routing guidelines for high-speed SerDes and D2D interfaces, including impedance targets, differential-pair geometry, via/transition optimization, return-current management, shielding, skew control, and crosstalk isolation. Establish SIPI modeling standards, design rules, review checklists, automation flows, and signoff methodologies to improve execution efficiency, while mentoring engineers across the organization. Required qualifications: 10+ years of experience in signal integrity, power integrity, package electrical design, or chip–package–board co-design for high-performance semiconductor products. Deep expertise in package SIPI modeling, analysis, optimization, and signoff across the chip–package–board system, for high-speed SerDes, PCIe, CXL, Ethernet, etc. Strong experience with PCIe 5.0/6.0, PAM4 SerDes channel design, high-speed S-parameter extraction, package model development, eye-diagram analysis, return/insertion-loss optimization, and crosstalk analysis. Proven track record delivering high-performance packages using FCBGA, FCCSP, coreless substrates, advanced organic substrates, chiplet-based packages, 2.5D integration, silicon interposers, or heterogeneous integration platforms. Hands-on expertise with EM extraction and SIPI simulation tools such as ANSYS HFSS, SIwave, Q3D, 3D Layout, Keysight ADS, Cadence Sigrity, or equivalent tools. Expert-level knowledge of PDN design, including DC IR drop, AC impedance, target impedance, loop inductance, decoupling optimization, transient response, noise coupling, and chip-package-model methodology. Demonstrated ability to correlate simulation to lab measurement (VNA, TDR, high-speed oscilloscope). Strong understanding of tradeoffs between SIPI performance, cost, reliability, and manufacturability. Experience leading vendor engagements and managing technical execution through production ramps. Preferred Qualifications: Experience influencing silicon floor planning, bump map definition, SerDes and power-grid planning, package escape strategy, and PCB breakout from a SIPI perspective. Experience with automation and scripting for SIPI modeling flow. Exposure to Allegro Package Designer (APD) for hands-on substrate editing. Knowledge on traditional FCBGA type package and advanced package (chiplet/2.5D/3D) manufacturing and assembly process flows Experience with CPO and NPO optical package SIPI design, including high-speed channel modeling between EIC/PIC/optical engine, PDN design, crosstalk/noise analysis, and chip–package–board co-design for optical connectivity applications. The base salary range is $203,000 USD – $230,000 USD. Your base salary will be determined based on location, experience, and employees' pay in similar positions.We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.At Astera Labs, we seek motivated Principal Signal and Power Integrity Engineers to work on our game-changing portfolio of connectivity products for Artificial Intelligence and Machine Learning applications. In this role, you will execute the SI planning, design, modeling, simulation, and lab validation with various system configurations. This position will be onsite. Basic Qualifications Strong academic/technical background in electrical engineering; Bachelor’s is required; Master’s preferred. 8+ years of experience supporting or developing complex SoC/silicon products for Server and Networking applications. 8+ years of hands-on high-speed SI/PI design, simulation, and measurement experience. Have a proven track record with defining hardware system constraints and high-speed technology roadmaps. Cross-functional design mentality with the electrical design community to develop systems. Self-starting, professional, and hands-on work ethic that can execute intense research in a dynamic environment. Proven track record solving problems independently, preferably as a tech lead. Entrepreneurial, open-minded behavior, and can-do attitude. Authorized to work in the US and start immediately. Required Experience Familiar with SI and PI design challenges for PCIe Gen5/6 and/or 224/448G Ethernet PCB and interconnects 2D and 3D EM simulation experience with Cadence/Ansys/ADS/etc. toolsets EM modeling of BGA and connector structures High-speed SERDES channel simulation, and equalization PI simulations with Ansys/Cadence toolsets Familiar with VNA, TDR, real-time and sub-sampling oscilloscopes, etc. Working knowledge of PCB fabrication limits and trade-offs Familiar with industry-standard such as PCI-SIG, and IEEE802.3, especially Electrical sections. Strong debugging, analysis, and problem-solving skills with experience leading root cause and correction action teams. An inherent sense of urgency and accountability. Must have the ability to multi-task in a fast-paced environment. Your base salary will be determined based on your experience and the pay of employees in similar positions. The base salary range is $203,000 USD - $230,000 USD for Principal level, and $237,500 USD - $250,000 USD for Senior Principal level. The actual level is to be determined by the years of experience and interview outcome.We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

About CelesticaCelestica (NYSE, TSX: CLS) enables the world’s best brands. Through our recognized customer-centric approach, we partner with leading companies in Aerospace and Defense, Communications, Enterprise, HealthTech, Industrial, Capital Equipment and Energy to deliver solutions for their most complex challenges. As a leader in design, manufacturing, hardware platform and supply chain solutions, Celestica brings global expertise and insight at every stage of product development – from drawing board to full-scale production and after-market services for products from advanced medical devices, to highly engineered aviation systems, to next-generation hardware platform solutions for the Cloud. Headquartered in Toronto, with talented teams spanning 40+ locations in 13 countries across the Americas, Europe and Asia, we imagine, develop and deliver a better future with our customers.Role SummaryThe Senior Lead Engineer, Hardware Design works with cross functional teams with other designers, customers, manufacturing engineering and project leadership to ensure robust and high quality product development. Enhance designs with feedback from reviews in areas such as manufacturing, test, supply chain, reliability, industrial design and simulations. Provide support throughout the manufacturing process of the electrical/mechanical system that they have designed.The Senior Lead Engineer, Hardware Design (Electrical) develops new electrical systems/circuits for various applications. Research system ideas and draw up plans for these systems, and capture them in schematics and system specifications. Test, simulate, validate and qualify their systems and make adjustments as needed The Senior Lead Engineer, Hardware Design (Mechanical) develops new mechanical systems/modules and maintains existing designs. Research mechanical concepts and create system solutions using 3D modeling and simulation software. Complete calculations and test, validate, and qualify their systems and make adjustments as needed.Detailed Job Description Performs tasks such as, but not limited to, the following: Lead the design, development and implementation of technical solutions in multiple domains. Participate in project planning and scheduling.Provide technical leadership and direction to a team of engineers. May be a recognised expert (go to person) in one or more technical areasReview, interpret and may negotiate customer requirements/specifications and provide customer feedbackLead the deployment of strategic programs and coordinate site-wide deployment efforts.Proactively promote industry best practicesMay manage relationships with key vendors/partners.Research systems ideas and will draw up plans for these systemsDesign, modify and implement systems that meet customer and Celestica needs.Create designs in line with Celesticas procedures, regulations and customer standardsKeep up to date with relevant industry knowledge and regulationsSolve complex problemsLiaison with suppliers, customers, contractors, and other internal teams.Recommend system modificationsElectrical: Creation of Schematics, Bills of material, diagrams, drawings, etc.Analysing and interpreting data and informationCreating reports and documentation Mechanical: Prepare calculations on the proposed solution before completing technical drawings. Sketch and draw up designs using input from other engineers, requirements and input from design review (DFx) teamCalculate factors like tolerance, dimensions, and thermal and structural analysisSubmit drawings to management, engineering teams and customers for review.Provide support during the manufacturing processFinalize designs and send prints to the production department

Google will be prioritizing applicants who have valid working rights in Thailand and do not require Google’s sponsorship of a visa.Note: Google's hybrid workplace includes remote roles.Remote location: Thailand.Minimum qualifications: Bachelor's degree in Electrical Engineering, Mechanical Engineering or equivalent practical experience. 8 years of experience in Printed Circuit Board Assembly (PCBA), and with in SMT processes. Experience with process and production line assembly development. Experience in leading design for manufacturability, hardware manufacturing, and lean manufacturing. Experience in developing relationships with contract manufacturers. Preferred qualifications: Master's degree in Electrical Engineering, Mechanical Engineering or equivalent practical experience. Experience with statistical product quality control, process capability, failure analysis, and process improvement. Experience with product data management systems (e.g., Agile, Windchill) and 3D CAD modeling tools, such as SolidWorks or Pro Engineer. Knowledge of IPC Workmanship Standards and ISO 9000. Ability to be well-focused, give attention to details, and commit to produce a timely and highly accurate work product. Excellent investigative, organizational, leadership, written and verbal communication skills. About the jobGoogle's custom-designed equipment makes up one of the largest and most powerful computing infrastructures in the world. The Manufacturing Operations team is responsible for providing the manufacturing capability to deliver this state-of-the-art physical infrastructure. As a Manufacturing Engineer, you evaluate the product designs and create the processes, tools and procedures behind Google’s powerful search technology. When vendors build parts for our infrastructure, you’re right there alongside ensuring manufacturing processes are repeatable and controlled. You collaborate with Commodity Managers and Design Engineers to determine Google’s infrastructure needs and product specifications. Your work ensures the various pieces of Google’s infrastructure fit together perfectly and keep our systems humming along smoothly for a seamless user experience. The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide. We're the driving team behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.Responsibilities Liaison for the manufacturing engineering to Google new technology teams, understand project requirements, assess product technologies and develop a manufacturing plan and supply chain to support it. Provide technical expertise and leadership throughout the product lifecycle, drive DFX, supporting New Product Introduction (NPI) builds and develop Google's supply chain. Provide strong technical influence and DFX that would benefit manufacturability. Build up CM capabilities in SMT, process, test, root cause analysis and communications. Develop and distribute manufacturing documentation in support of product design, configuration, process and build requirements, document such items as bill of materials (BOM), assembly drawings, manufacturing work instructions, Tooling/Jig, etc. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.

Google will be prioritizing applicants who have a current right to work in Singapore, and do not require Google's sponsorship of a visa.Minimum qualifications: Bachelor's degree in Mechanical Engineering, Electrical Engineering or IT Engineering, or equivalent practical experience. 5 years of experience working with external telecom vendors on telecom products. Preferred qualifications: Master's degree in Mechanical or Electrical or IT engineering. 6 years of experience as a Registered Communications Distribution Designer (RCDD) Certified professional with ICT/telecom scope within mechanical and electrical data center products. 6 years of experience as key contributor on ICT/telecom scope within mechanical and electrical data center products Experience with Autodesk Revit or other 3D modeling software developing telecom rack and tray layouts. Ability to travel to visit data center sites or manufacturing partners. About the jobOur thirst for technology is a part of everything we do. The Data Center Engineering team takes the physical design of our data centers into the future. Our lab mirrors a research and development department -- cutting-edge strategies are born, tested and tested again. Along with a team of great minds, you take on complex topics like how we use power or how to run state-of-the-art, environmentally-friendly facilities. You're a visionary who optimizes for efficiencies and never stops seeking improvements -- even small changes that can make a huge impact. You generate ideas, communicate recommendations to senior-level executives and drive implementation alongside facilities technicians. The Data Center Design Integration team is a multi disciplinary team of architects and Information and Communication Technology (ICT)/Telecommunications (Telecom) designers that work on next generation data center designs. We are a sub-team of the broader Data Center Technology and Systems (DCTS) organization.As a Telecom Lead, you will be responsible for working with executive level engineers across all disciplines to develop integrated telecom communication designs at the product and top level assembly state of a data center. You will lead external consultants to develop coordinated construction level drawing packages for manufacturing and construction.The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide. We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.Responsibilities Work with internal telecom engineers and network designers to rationalize requirements into products, conceptual one lines and conceptual rack or tray layouts to enable adequate telecom infrastructure. Work with cross-functional disciplines across architecture, civil, mechanical, electrical, controls, security on product development, and assembly integration of telecom infrastructure. Participate in internal and external ICT/telecom product and data center design reviews across the following disciplines: Telecom, Security, Controls and Networking. Review construction level drawings produced by internal and external vendors that document ICT/telecom scope for program reference. Review and enable best practices for converged network allocations across all mechanical, electrical, and controls products. Act as an escalation path for site localization of canonical design where local requirements necessitate engineering judgement on adjustments to ICT/telecom design. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.Role Overview As a Principal Package Thermal Mechanical Engineer at Astera Labs, you will serve as a technical leader driving the development and modeling of advanced IC packaging solutions that enable next-generation AI and high-performance connectivity systems. In this highly visible role, you will define and execute thermal and mechanical modeling strategies across the chip–package–board system, influencing package architecture, material selection, and reliability design. You will partner closely with package design, SIPI, silicon, system, and manufacturing teams to ensure robust thermal/mechanical performance and first-pass success. You will also drive modeling methodologies, correlation strategies, and best-known methods (BKMs), while engaging directly with customers to translate complex simulation insights into actionable system-level solutions. Key Responsibilities Thermal Mechanical Modeling Leadership Define and drive thermal and mechanical modeling strategies for advanced packages (FCBGA, FCCSP, multi-die, and chiplet-based architectures) Perform detailed thermal simulations including steady-state and transient heat transfer (conduction, convection, and interface resistances such as TIM1/TIM2) Develop and deploy compact thermal models (CTM), reduced-order models (ROM), and DELPHI-based models for system-level integration Analyze power density, hotspot behavior, and package-to-system thermal interactions across air and liquid cooling environments Perform thermo-mechanical stress/strain analysis including CTE mismatch, viscoelastic material behavior, and deformation Predict package warpage across process and use conditions (reflow, underfill cure, board attach, field operation) Model solder joint reliability and fatigue using industry standard models Package Architecture Thermal Design Strategy Drive package design decisions including material selection (EMC, substrate, TIM, lid/heat spreader), thermal path optimization, and early-stage architecture definition across air and liquid cooling solutions (air, cold plate, CPO/CPC) Conduct DOE, sensitivity studies, and worst-case analysis to guide tradeoffs across performance, cost, reliability, and manufacturability System Co-Design Automation Partner cross-functionally to drive chip–package–board co-design and resolve system-level thermal/mechanical challenges, including system integration constraints Serve as a technical interface for customers and internal teams, translating modeling results into actionable insights and leading design reviews and issue resolution Develop and scale modeling methodologies, workflows, and BKMs; mentor engineers and improve efficiency through automation and scripting (Python, MATLAB) Basic Qualifications M.S. or Ph.D. in Mechanical Engineering, Materials Science, Electrical Engineering, or related field 8+ years of experience in semiconductor packaging with strong focus on thermal and mechanical modeling Deep expertise in thermal modeling and simulation, including steady-state and transient analysis, compact thermal modeling (CTM), DELPHI methodology, and system-level thermal integration using tools such as ANSYS Icepak, Flotherm, or equivalent Deep expertise in thermo-mechanical modeling and FEA simulation, including stress/strain analysis, warpage prediction, and reliability modeling (BLR/CLR), using tools such as ANSYS Mechanical, or equivalent Proven ability to correlate simulation results with lab measurements Experience influencing package design and delivering solutions to production Strong cross-functional collaboration across package design, SIPI, system, and manufacturing teams Preferred Qualifications Experience with high-power AI / HPC packages and large FCBGA (50mm) Familiarity with advanced packaging technologies:2.5D / 3D integration, Chiplet, CPO/CPC Experience with system-level cooling solutions: Liquid cooling, cold plates, immersion cooling Knowledge of JEDEC standards and reliability qualification methodologies Experience working with OSATs and substrate vendors on thermal/mechanical design optimization Proficiency in scripting (Python, MATLAB) for modeling automation Exposure to multi-physics coupling (electrical–thermal–mechanical interactions) The base salary range is $185,000 USD – $230,000 USD. Your base salary will be determined based on location, experience, and employees' pay in similar positions.We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.