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職位描述：我們正在尋找一位經驗豐富的減速機機構工程師，負責機器人關節模組與精密傳動機構中減速機的設計與優化。該職位將與減速機齒輪之機構設計、製造與驗證、並須跨功能團隊合作，從概念設計到產品實現，確保機器人關節的高效能和可靠性。主要職責：1.減速機設計與開發：- 設計與分析諧波減速機、行星減速機、蝸輪蝸桿減速機等精密傳動機構。- 根據應用需求選擇適當的減速比、齒輪模數與結構設計，確保低噪音高效率與低背隙。治具設計、修改與驗收，負責試製與量產階段的技術支援、問題分析與解決。- 根據應用需求選擇合適的材料（如高強度合金鋼、工程塑膠、陶瓷等）。優化減速機結構，減

【Position Overview】We are seeking a pioneering Senior/ Staff Level SI Engineer to establish our High-Speed Test Competency Center from the ground up. In this role, you will be the key architect bridging the gap between RD develop and Mass Production. You will not only define the SI/PI guidelines for our next-generation CIS (MIPI C-PHY/D-PHY) and SerDes products but also lead the technical transformation of our test engineering team.【Responsibilities】A. Architecture Simulation * Perform Pre-layout and Post-layout SI/PI simulations for ATE Load Boards and Probe Cards using tools like Ansys, ADS...etc * Develop channel models and loss budgets for complex test interfaces (Socket, Pogo Tower, Relay, Cable) to predict signal degradation. * Establish develop Guidelines: Create and maintain the "High-Speed PCB develop Checklist" for external vendors to ensure impedance control compliance.B. Lab Characterization * Build the Lab: Lead the evaluation and setup of high-speed measurement infrastructure (TDR, VNA, High-bandwidth Oscilloscopes). * Execute physical layer validation for MIPI C-PHY/D-PHY and SerDes interfaces. * Define "Golden Eye Diagram" criteria and generate S-parameter reports for mass production baseline.C. Lab-to-Fab Correlation * Collaborate with Test Engineers (TE) to perform De-embedding and Receiver Equalization (CTLE/DFE) tuning on ATE platforms. * Lead the root cause analysis for yield excursions, distinguishing between device defects, contact issues, and signal integrity artifacts. * Conduct gap analysis between Bench data (Lab) and ATE data (Production) to optimize test limits.D. Methodology Mentorship * Act as a Technical Coach: Train and mentor Test Engineers on high-speed fundamentals, helping them interpret eye diagrams and debug logs. * Standardize the hardware validation flow and create troubleshooting SOPs for the operation team.E. Other tasks assigned by supervisors.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.Role Overview Astera Labs is establishing a strategic RD center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a highly skilled Physical Design Engineer specializing in EMIR CAD to join our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful technical ownership in a new site, executing the backend power methodologies for chips that power the world's largest AI clusters. As a Physical Design Engineer, you will be a core technical contributor ensuring the power robustness and long-term reliability of our high-performance connectivity silicon. You will continuously develop the Electro-Migration and IR Drop (EMIR) flow, working closely at the intersection of Physical Design, Analog/Mixed-Signal design, and Package Engineering. Key Responsibilities Take responsibility on IR drop analysis and signal/power electromigration (EM) flow Implement and maintain robust EMIR flows and methodologies using industry-standard tools (Ansys RedHawk-SC, Cadence Voltus, or equivalent) Collaborate closely with Analog/SerDes designers to integrate current profiles and ensure robust power delivery to sensitive high-speed IP blocks Partner with Package Design engineers to perform Chip-Package-System (CPS) co-analysis flow Understand root-cause analysis for voltage drop violations and EM risks Support silicon bring-up by correlating simulation results with actual silicon measurements and yield data Basic Qualifications Bachelor's or Master's degree in Electrical Engineering or a related technical field 5+ years of hands-on experience in EMIR/Power Integrity analysis for high-performance SoCs or high-speed connectivity products Strong proficiency in industry-standard EMIR tools flow development (Ansys RedHawk/RedHawk-SC, or Cadence Voltus) Deep understanding of EM/IR challenges in advanced FinFET nodes (7nm, 5nm, 3nm) Basic understanding of Place Route flows, power grid synthesis, extraction (RC), and standard cell architecture Proven Proficiency in Python in required, Tcl or Perl preferable for flow automation and data parsing Deep understanding of the RedHawk tool, including efficient use of MapReduce and other Ansys proprietary capabilities (including potential use of ad-hoc SDC for context and LSO – Logic State Override) Strong understanding of required inputs for creating Scenarios and Analysis Views Deep understanding of standard cell and IP abstractions (APL, LIB, AVM), including IP waveform construction from PWL (sim2iprof) Preferred Experience Experience performing Chip-Package-System (CPS) thermal and power co-simulation Familiarity with thermal analysis tools and their interaction with electrical performance Experience working with sign-off criteria and margins for high-volume production chips Basic understanding of timing and PR Good understanding of EM, including deterministic EM (DC, peak, RMS) Basic understanding of statistical EM and reliability concepts (SEB, Black’s Equation, FIT, MTTF) Basic understanding of packaging, top metal layers, MIM capacitor usage, and power distribution We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

1.負責熱流系統/材料模型設計、建立和優化。2.精通Ansys Fluent 等相關應用軟件，進行熱流系統與材料的性能分析，藉此評估方案的有效性。3.針對熱流系統/材料，給予開發過程中的建議與實務擬合，為項目提供支持。*須長期出差

1.執行部門主管訂定的部門策略。2.主導磁性元件最新產品的開發任務。3.協助和指導工程師或者資深工程師提高設計開發能力。4.主導產品從開發到量產的轉移。5.對產品設計的技術瓶頸提供可行的解決方案。6.主導技術品質事件分析。7.開發項目中重點設計參數的把關與建議。Preference：1.熟悉電磁學,磁性材料,電力電子相關基礎知識2.具有電磁模擬(Maxwell,Ansys)相關經驗尤佳3.具有磁性元件設計及開發經驗尤佳

🧠 用模擬預測未來，讓產品更強、更穩、更可靠！ 如果你熱愛結構分析、也想把理論真正應用在產品設計上—— 👉 歡迎加入我們【CAE工程師】團隊！ 🔧 你將負責的工作 在這裡，你的分析將直接影響產品設計決策： 結構強度模擬 振動模擬 衝擊／摔落模擬 結構疲勞壽命模擬 結構最佳化設計 與機構設計團隊協作，提供設計改善建議

Logitech is the Sweet Spot for people who want their actions to have a positive global impact while having the flexibility to do it in their own way.The Role:The responsibilities for this position include mechanical design and development of Video Collaboration System from product front end, through product design and launch into successful mass production, with a clear focus on user experience. The ability to use Pro/E, Ansys, and analysis tools to create reliable mechanical designs for volume mass production is required. Additional responsibilities include ensuring product features achieve cost, schedule, reliability, regulatory and safety goals.Your Contribution:Be Yourself. Be Open. Stay Hungry and Humble. Collaborate. Challenge. Decide and just Do. Share our passion for Equality and the Environment. These are the behaviors you’ll need for success at Logitech. In this role you will:Design, analysis, documentation and testing of complex mechanical parts and assemblies. Analyze critical areas of design with use of appropriate analysis tools.Play a key role in ensuring the final design meets quality and cost goals, and achieves specifications of reliability, manufacturability, and ESD containment.Partner with Manufacturing teams/Suppliers to ensure our designs are optimized for mass production.Resolve ME issues/challenges.Partner and collaborate with other worldwide functions to achieve seamless product development.Launch the development and qualification of plastic tooling, including design debug. Qualification Skills:For consideration, you must bring the following minimum skills and behaviors to our team:6 years experience in mechanical design/development of high-volume consumer electronic products.Good knowledge of plastic, tooling, injection molding, assembly processes, cosmetic finishes, and defect analysis.Good knowledge in metal punch tool structure and design.Good Pro/E and AutoCAD skills.Skilled in Ansys simulation.Good problem-solving skills.Good understanding of risk management.Advanced knowledge of quality tools such as DFMEA, DFMA, PSS and tolerance analysis.Fluent prototyping skills. CAE experience is a plus.Creative and self-motivated.Good in English writing and speaking, and presentation skills.Education:Master / Bachelor in Mechanical Engineering or equivalent.Background:Experience in camera, video conferencing devices and related consumer electronic products.#LI-KS1/104Across Logitech we empower collaboration and foster play. We help teams collaborate/learn from anywhere, without compromising on productivity or continuity so it should be no surprise that most of our jobs are open to work from home from most locations. Our hybrid work model allows some employees to work remotely while others work on-premises. Within this structure, you may have teams or departments split between working remotely and working in-house.Logitech is an amazing place to work because it is full of authentic people who are inclusive by nature as well as by design. Being a global company, we value our diversity and celebrate all our differences. Don’t meet every single requirement? Not a problem. If you feel you are the right candidate for the opportunity, we strongly recommend that you apply. We want to meet you!We offer comprehensive and competitive benefits packages and working environments that are designed to be flexible and help you to care for yourself and your loved ones, now and in the future. We believe that good health means more than getting medical care when you need it. Logitech supports a culture that encourages individuals to achieve good physical, financial, emotional, intellectual and social wellbeing so we all can create, achieve and enjoy more and support our families. We can’t wait to tell you more about them being that there are too many to list here and they vary based on location.All qualified applicants will receive consideration for employment without regard to race, sex, age, color, religion, sexual orientation, gender identity, national origin, protected veteran status, or on the basis of disability.If you require an accommodation to complete any part of the application process, are limited in the ability, are unable to access or use this online application process and need an alternative method for applying, you may contact us toll free at 1-510-713-4866 for assistance and we will get back to you as soon as possible.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.Role Overview As a Principal Package Thermal Mechanical Engineer at Astera Labs, you will serve as a technical leader driving the development and modeling of advanced IC packaging solutions that enable next-generation AI and high-performance connectivity systems. In this highly visible role, you will define and execute thermal and mechanical modeling strategies across the chip–package–board system, influencing package architecture, material selection, and reliability design. You will partner closely with package design, SIPI, silicon, system, and manufacturing teams to ensure robust thermal/mechanical performance and first-pass success. You will also drive modeling methodologies, correlation strategies, and best-known methods (BKMs), while engaging directly with customers to translate complex simulation insights into actionable system-level solutions. Key Responsibilities Thermal Mechanical Modeling Leadership Define and drive thermal and mechanical modeling strategies for advanced packages (FCBGA, FCCSP, multi-die, and chiplet-based architectures) Perform detailed thermal simulations including steady-state and transient heat transfer (conduction, convection, and interface resistances such as TIM1/TIM2) Develop and deploy compact thermal models (CTM), reduced-order models (ROM), and DELPHI-based models for system-level integration Analyze power density, hotspot behavior, and package-to-system thermal interactions across air and liquid cooling environments Perform thermo-mechanical stress/strain analysis including CTE mismatch, viscoelastic material behavior, and deformation Predict package warpage across process and use conditions (reflow, underfill cure, board attach, field operation) Model solder joint reliability and fatigue using industry standard models Package Architecture Thermal Design Strategy Drive package design decisions including material selection (EMC, substrate, TIM, lid/heat spreader), thermal path optimization, and early-stage architecture definition across air and liquid cooling solutions (air, cold plate, CPO/CPC) Conduct DOE, sensitivity studies, and worst-case analysis to guide tradeoffs across performance, cost, reliability, and manufacturability System Co-Design Automation Partner cross-functionally to drive chip–package–board co-design and resolve system-level thermal/mechanical challenges, including system integration constraints Serve as a technical interface for customers and internal teams, translating modeling results into actionable insights and leading design reviews and issue resolution Develop and scale modeling methodologies, workflows, and BKMs; mentor engineers and improve efficiency through automation and scripting (Python, MATLAB) Basic Qualifications M.S. or Ph.D. in Mechanical Engineering, Materials Science, Electrical Engineering, or related field 8+ years of experience in semiconductor packaging with strong focus on thermal and mechanical modeling Deep expertise in thermal modeling and simulation, including steady-state and transient analysis, compact thermal modeling (CTM), DELPHI methodology, and system-level thermal integration using tools such as ANSYS Icepak, Flotherm, or equivalent Deep expertise in thermo-mechanical modeling and FEA simulation, including stress/strain analysis, warpage prediction, and reliability modeling (BLR/CLR), using tools such as ANSYS Mechanical, or equivalent Proven ability to correlate simulation results with lab measurements Experience influencing package design and delivering solutions to production Strong cross-functional collaboration across package design, SIPI, system, and manufacturing teams Preferred Qualifications Experience with high-power AI / HPC packages and large FCBGA (50mm) Familiarity with advanced packaging technologies:2.5D / 3D integration, Chiplet, CPO/CPC Experience with system-level cooling solutions: Liquid cooling, cold plates, immersion cooling Knowledge of JEDEC standards and reliability qualification methodologies Experience working with OSATs and substrate vendors on thermal/mechanical design optimization Proficiency in scripting (Python, MATLAB) for modeling automation Exposure to multi-physics coupling (electrical–thermal–mechanical interactions) The base salary range is $185,000 USD – $230,000 USD. Your base salary will be determined based on location, experience, and employees' pay in similar positions.We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

【本職缺優先審核英特格官方網站投遞】 請至英特格官方網站投遞個人履歷表，此職缺履歷登錄網址: https://bit.ly/Entegris_Careers【The Role】The Product Design Engineer will provide technical solutions in Microenvironment mainly focus on FOUP (Front Opening Unified Pod) products through manufacturable, reliable designs by combining mechanical engineering, SolidWorks expertise, and simulation. You will partner with suppliers and cross‑functional, global teams to deliver designs that meet function, quality, schedule, and cost goals—reducing development risk and accelerating time‑to‑market.【In this role you will】• Translate ideas into robust designs using SolidWorks and engineering simulation to inform decisions.• Design and build plastic parts and prototypes (3D printing and injection molding) in close collaboration with suppliers.• Balance quality, cost, and schedule with cross functional stakeholders across regions.• Plan and support validation builds from concept through ramp; drive issue closure to enable milestones.• Maintain essential documentation (drawings, BOM, changes) with disciplined configuration control.• Communicate clearly in English across time zones to align requirements, decisions, and risks.【Traits we believe make a strong candidate】• Mechanical engineering foundation; strong SolidWorks (parts, assemblies, drawings).• Working knowledge of simulation on SolidWorks or Ansys to guide design trade‑offs.• Hands‑on experience with plastic part design and 3D printing prototyping.• Practical understanding of manufacturing and supplier collaboration.• Systems thinking and structured, data‑informed problem solving.• Innovation mindset with the ability to turn ideas into testable designs.• Clear, concise English communication and stakeholder management across functions and geographies.• Ownership and execution: plans well, follows through, and adapts under ambiguity.

Google welcomes people with disabilities.Minimum qualifications: Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, Physics, or a specialized field (e.g., Optics, Sensors, Audio/DSP, etc.), or equivalent practical experience. 4 years of experience working in designing de-sense or EMC for consumer electronics. 4 years of experience working with Radio Frequency (RF) interference mitigation, factory processes, and manufacturing. 4 years of experience working with different wireless communication systems (e.g., GSM/UMTS/CDMA/LTE/NR, 802.11, Bluetooth, GNSS, etc.) as well as equipment operation. 4 years of experience in spectrum operation or near field scanning for noise root cause analysis. Preferred qualifications: Experience with test automation and scripting (Python, C++, Java, MATLAB). Knowledge of international EMC regulations, compliance requirements and standards (include, but are not limited to FCC/CISPR,IEC/EN,ETSI) and test methodologies. Knowledge of de-sense regarding RF coexistence. Fundamental knowledge of RF and antenna design. Familiar with relevant simulation tool and can support software tools development such as ANSYS or CST. Skilled in EMC debug techniques and must be able to accurately perform emissions and immunity testing. About the jobThe Google Pixel team focuses on designing and delivering the world's most helpful mobile experience. The team works on shaping the future of Pixel devices and services through some of the most advanced designs, techniques, products, and experiences in consumer electronics. This includes bringing together the best of Google’s artificial intelligence, software, and hardware to build global smartphones and create transformative experiences for users across the world.Responsibilities Work with cross-functional teams to solve over the air de-sense issues including all wireless technologies (e.g., FR1, FR2, LTE, UMTS, GSM, WLAN, BT, GNSS). Work on hardware schematics design, providing appropriate de-sense and Electromagnetic Compatibility (EMC) solutions across each hardware function and also system architecture and grounding materials selection in relation to product design. Execute de-sense and EMC validation from proto to Production Validation Test (PVT), troubleshooting related issues efficiently without any impact to the product schedule. Be responsible for PCB layout review at each development stage, achieving the best layout routing from de-sense and EMC perspective. Work closely with key parts technical program managers or vendors to drive the best de-sense/EMC performance, including display, camera, fingerprint sensor etc. Be responsible for factory issues in relation to de-sense and EMC. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.