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Minimum qualifications: PhD degree in Electronics and Communication Engineering, Electrical Engineering, Computer Engineering or related technical field, or equivalent practical experience. Experience with accelerator architectures and data center workloads. Experience in programming languages (e.g., C++, Python, Verilog), Synopsys, Cadence tools. Preferred qualifications: 2 years of experience post PhD. Experience with performance modeling tools. Knowledge of arithmetic units, bus architectures, accelerators, or memory hierarchies. Knowledge of high performance and low power design techniques. About the jobIn this role, you will shape the future of AI/ML hardware acceleration as a Silicon Architect/Design Engineer and drive cutting-edge TPU (Tensor Processing Unit) technology that fuels Google's most demanding AI/ML applications. You will collaborate with hardware and software architects and designers to architect, model, analyze, define and design next-generation TPUs. You will have dynamic, multi-faceted responsibilities in areas such as product definition, design, and implementation, collaborating with the Engineering teams to drive the optimal balance between performance, power, features, schedule, and cost.The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide. We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.Responsibilities Revolutionize Machine Learning (ML) workload characterization and benchmarking, and propose capabilities and optimizations for next-generation TPUs. Develop architecture specifications that meet current and future computing requirements for AI/ML roadmap. Develop architectural and microarchitectural power/performance models, microarchitecture and RTL designs and evaluate quantitative and qualitative performance and power analysis. Partner with hardware design, software, compiler, Machine Learning (ML) model and research teams for effective hardware/software codesign, creating high performance hardware/software interfaces. Develop and adopt advanced AI/ML capabilities, drive accelerated and efficient design verification strategies and implementations. Use AI techniques for faster and optimal Physical Design Convergence -Timing, floor planning, power grid and clock tree design etc. Investigate, validate, and optimize DFT, post-silicon test, and debug strategies, contributing to the advancement of silicon bring-up and qualification processes. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.

CS Infrastructure Support – Infra Support Intern ASIntroduction:CS IAS (CS Infrastructure, Architecture and Security) covers worldwide functional support for all off-scanner Applications, Infrastructure and Security. We ensure that CS field engineer operation and process excellence.Job Mission:Your main responsibilities are to ensure that support operations are picked up and handled to the satisfaction of our end-users and within given KPI’s, to update the knowledge bases, participate in user acceptance tests and to administrate calls in our call management system. Working hours need to fit the time window for which the AS team is responsible. Main responsibility is to coordinate CS and end customers project discussion of infrastructure topics.Job Description:Ticket management: CS IAS incident handlingCoordinate BRES account applicationCS IAS work instruction and document maintenanceEducation:Bachelor/ MasterPersonal Skills:The ability to speak and write in EnglishKnowledge in MS OfficeAble to build strong networks with stakeholdersCultural awareness of applicable customersOffice locationHsinchu, TaiwanThis position requires access to controlled technology, as defined in the United States Export Administration Regulations (15 C.F.R. § 730, et seq.). Qualified candidates must be legally authorized to access such controlled technology prior to beginning work. Business demands may require ASML to proceed with candidates who are immediately eligible to access controlled technology.Inclusion and diversityASML is an Equal Opportunity Employer that values and respects the importance of a diverse and inclusive workforce. It is the policy of the company to recruit, hire, train and promote persons in all job titles without regard to race, color, religion, sex, age, national origin, veteran status, disability, sexual orientation, or gender identity. We recognize that inclusion and diversity is a driving force in the success of our company.Need to know more about applying for a job at ASML? Read our frequently asked questions.

Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 10 years of experience in ASIC development with Verilog/SystemVerilog, Vhsic Hardware Description Language (VHDL). Experience in micro-architecture and design IPs and Subsystems. Experience in ASIC design verification, synthesis, timing/power analysis, and Design for Testing (DFT). Preferred qualifications: Experience with scripting languages (e.g., Python or Perl). Experience in SoC designs and integration flows. Knowledge of bus architectures, fabrics/NoC, processor design, accelerators, or memory hierarchies.. Knowledge of high performance and low power design techniques. About the jobIn this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. In this role, you will be part of a team developing Application-Specific Integrated Circuits (ASIC) used to accelerate and improve traffic efficiency in data centers. You will collaborate with members of architecture, verification, power and performance, physical design, etc. to specify and deliver high quality designs for next generation data center accelerators. You will solve technical problems with innovative micro-architecture and practical logic solutions, and evaluate design options with complexity, performance, power and area in mind.The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide. We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.Responsibilities Drive development of complex IPs and subsystems along with a team of engineers. Own micro-architecture and implementation of IPs and subsystems. Work with architecture, firmware and software teams to drive feature closure and develop micro-architecture specifications. Drive design methodology, libraries, debug, code review in coordination with other IPs Design Verification (DV) teams and physical design teams. Identify and drive power, performance and area improvements for the domains owned. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.

｜核心職責 (Technical Execution)【全渠道通訊架構與高併發治理 (Omnichannel Messaging Architecture)】。主導 Meta (WhatsApp, Facebook Messenger, Instagram) 與 LINE 等第三方通訊平台的底層串接架構設計。。建構具備高吞吐量、高可用性且支援非同步處理的訊息中樞 (Message Hub)，確保在海量 Webhook 瞬間併發下，系統仍能穩健運行且達到「訊息零丟失 (Zero Message Loss)」。【核心模組演進與重構】。主導系統中複雜模組的 refactoring 實作。具備處理大規模程式碼異動的能力，能在不影響業務運行下，完成 Scope 極大的系統改版與邏輯優化。【AI 協作開發實踐】。將 AI 輔助工具（如 GitHub Copilot, Cursor）深度整合進日常工作流。利用 AI 進行高效率的 code review、基於 Testcontainers 與 LocalStack 的整合測試生成及複雜邏輯的重構建議，示範如何以 AI 賦能達成極致的產出品質。【務實的性能治理與調優】。根據業務場景進行合理的 performance tuning。需具備判斷技術投入產出比（ROI）的能力，確保核心通訊場景具備極限負載下的穩定性，同時在一般功能中保持開發效率與成本平衡。【安全性與弱點修復】。主導處理經由 Inspector 掃描發現的系統弱點（Vulnerabilities）。需具備評估風險優先級與實作修復方案的能力，在維持系統高可用性的前提下，優化軟體依賴與代碼安全性。。針對第三方平台的 Token 授權管理、API Secret 存放與傳輸安全進行嚴格把關。【高品質代碼實作】。負責核心 Feature 的開發與關鍵 API 設計，建立具備高度可讀性、可維護性且效能優異的代碼範本。【技術瓶頸攻堅】。針對系統運行中的各類 Hard Problem（如 deadlock、race condition、OOM 等）進行深度追蹤並完成修復。

Responsibilities: High-Quality Code Delivery:Write clean, concise, easy-to-read, and well-documented code to ensure the system is maintainable and scalable.Ensure code is designed for scalability and performance, anticipating future growth and changes.System Analysis and Refactoring:Analyze existing system code, refactor and optimize it, and write tests to ensure system stability and performance.Propose and implement refactoring strategies that improve maintainability, performance, and readability of the system.Code Review and Team Collaboration:Actively participate in code reviews, provide constructive feedback on pull requests, and help the team continuously improve.Share best practices to elevate the overall code quality within the team.Requirements Understanding and System Design:Collaborate closely with product and business teams to thoroughly understand requirements and contribute to system architecture design, implementing effective technical solutions.Contribute to the design and architecture of scalable systems, ensuring alignment with overall product strategy.Identify potential technical challenges early and propose effective solutions.International Team Collaboration:Work with global engineering teams, engaging in technical communication and collaboration to drive product innovation.

About OptiSigns OptiSigns is a fast-scaling cloud platform powering digital signage for 35,000+ businesses across 100+ countries, with 200,000+ active screens worldwide. Founded in Houston, Texas in 2016 and now expanding aggressively in Asia and Europe, we help companies transform ordinary screens into powerful, dynamic communication tools. Our Vietnam engineering team is central to our next phase of growth. Why This Role This is not a typical engineer role. We are looking to bring on a Chinese speaking Embedded Android Lead engineer to relocate to Ho Chi Minh City, Vietnam or Houston TX, USA,and lead our growing engineering hub. This is a hands-on technical leadership role, with real ownership over both system scalability and team developmentand lead firmware and OS layer of our digital signage platform. You will be responsible for building and maintaining a custom Android (AOSP-based) system running on Rockchip devices. This role includes a full relocation package and offers a global career path, including the opportunity to work from our US headquarters as part of our rotation program. What You’ll Do Build and customize Android (AOSP) for embedded devicesWork with BSP and vendor SDKs (Rockchip)Optimize system performance for media playback and multi-displayOwn firmware lifecycle: build, release, maintenanceImplement OTA update systemsWork closely with hardware/ODM teams during bring-upIntegrate drivers, HALs, and system servicesEnable remote diagnostics and debugging Why Join OptiSigns High-impact role shaping the architecture of a globally used product (200,000+ screens)Real-world scaling challenges with tangible business impactStrong ownership, high visibility, and direct influence on technical directionOpportunity to build and lead a growing engineering team in VietnamFully supported relocation from Taiwan What We Offer Competitive salary: TWD 2.0M – 3.0M per year Performance bonus: 15–25% based on impactOpportunity for global rotation program (work in our US office after 1+ year of strong performance)Full relocation package (visa sponsorship, flights, Temp housing allowance, onboarding support)13th-month salary, comprehensive health insurance, and standard Vietnam benefits

Google welcomes people with disabilities.Note: By applying to this position you will have an opportunity to share your preferred working location from the following: New Taipei, Banqiao District, New Taipei City, Taiwan; Zhubei, Zhubei City, Hsinchu County, Taiwan.Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. 8 years of experience with computer architecture concepts, including micro architecture, cache hierarchy, pipelining, and memory subsystems. 3 years of experience working with Mobile or Embedded SoCs architecture or use case system design. Preferred qualifications: Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science. 5 years of experience working with Mobile or Embedded SoCs related to system design to improve use case level power and performance. Experience driving system architecture decisions across SW/HW teams within an organization to build up the consensus and translate ideas into architecture specifications. Experience with Android Architecture, Mobile SoC architecture, ML architecture, Computer Architecture, PPA trade-offs. Knowledge of interactions between software and HW IP blocks, general and special purpose compute units. About the jobBe part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. As part of the Platform System Architecture team, you will leverage the expertise in computer and AI/ML architecture, Power, Performance, and Area (PPA) trade-offs, mobile SoC AI/ML workloads analysis, ability to traverse across the Software (SW)/Hardware (HW) stack to influence IP and SoC architecture for the Tensor SoC to bring in the latest AI/ML user experience on Pixel devices.Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.Responsibilities Influence Tensor SoC architecture decisions for PPA working cross-functionally with SW/HW architects, design teams, and research teams to enable the industrial best user experience on Pixel phone devices empowered by the latest and the most advanced Generative AI technologies provided by Google research. Leverage a data driven approach through profiling, simulation and modeling, drive consensus around architectural decisions across the entire silicon organization to solve system design problems. Be the primary owner of the architecture specifications, system design documentation, workload analysis, modeling and projection to influence and define future SoC architecture. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.

About This RoleThis role is a UI/UX Designer position that requires both UI and UX capabilities.In practice, the role places a stronger emphasis on UX thinking, flow design, and overall product experience.Responsibilities Plan and optimize user flows and information architecture (IA) Translate requirements into wireframes, prototypes, and production-ready UI designs Collaborate closely with Product and Engineering from problem definition through implementation Conduct or participate in UX research and usability testing, and turn insights into design decisions Design and maintain consistent, scalable UI components and interface guidelines Work with Brand / Visual Designers to ensure alignment between product experience and visual direction Continuously iterate and improve the product experience based on user feedback and data

Google welcomes people with disabilities.Note: By applying to this position you will have an opportunity to share your preferred working location from the following: New Taipei, Banqiao District, New Taipei City, Taiwan; Zhubei, Zhubei City, Hsinchu County, Taiwan.Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering or Computer Science, emphasizing in Computer Architecture, or equivalent practical experience. 4 years of experience in microprocessor architecture, microarchitecture, performance, or advanced CPU design. Experience with C/C++ and scripting languages (e.g., Python). Experience in CPU architecture, performance modeling, analysis, correlation, and workload characterization. Preferred qualifications: Master's or PhD degree in Electrical Engineering, Computer Engineering, or Computer Science, emphasizing in Computer Architecture or Machine Learning. Experience in CPU/ML microarchitecture exploration, performance model development, performance analysis, performance correlation, or workload characterization. Knowledge of microprocessor instruction set architecture (e.g., ARM, RISC-V, x86). Familiarity with system software components, such as Linux, drivers, and runtime. About the jobAs a CPU Performance Architect, you will be the key contributor to improve processor instruction set architecture, to develop innovative microarchitecture features, and deliver Google’s advanced SoC products. You will collaborate cross-functionally with Android Applications and AI teams to conduct applications and benchmark performance analysis and to project their performance at various design phases. You will be guided by architects and work with engineers in Power, Thermal, Security, and Physical Design teams to determine the CPU subsystem configuration and features.Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.Responsibilities Develop and modify a performance model for performance analysis and microarchitecture study. Evaluate Advanced RISC Machine (ARM’s) architecture features from both architecture and performance angles. Define and write CPU subsystem architecture specifications. Collaborate with Register-Transfer Level (RTL), design verification, and physical design teams to develop a high-performance and efficient CPU implementation. Manage performance correlation between the performance model and RTL implementation, including micro-benchmark development and pre-silicon and post-silicon performance bug triage. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.

Google welcomes people with disabilities.Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Zhubei, Zhubei City, Hsinchu County, Taiwan; New Taipei, Banqiao District, New Taipei City, Taiwan.Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or equivalent practical experience. 8 years of experience in microprocessor architecture, micro-architecture, performance, or advanced CPU design. Experience in CPU architecture, performance modeling, analysis, correlation, and workload characterization. Experience with C/C++ and scripting languages (e.g., Python). Preferred qualifications: PhD in Electrical Engineering, Computer Engineering, or Computer Science. Experience in leading CPU/ML micro-architecture exploration, performance model development, performance analysis, performance correlation, and workload characterization. Knowledge of processor instruction set architecture (e.g., ARM, RISC-V, x86). Knowledge of system software components (e.g., Linux, drivers, and runtime). Excellent communication skills. About the jobBe part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. In this role, you will be the key contributor to improve processor instruction set architecture, develop micro-architecture features, and to deliver Google’s SoC products. You will have the opportunity to collaborate with Google’s Android applications and AI teams to plan and conduct application and benchmark performance analysis.Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.Responsibilities Plan and evaluate ARM’s architecture features from both architecture and performance aspects. Develop a performance model for performance analysis and micro-architecture study. Define and write CPU subsystem architecture specifications. Lead collaborate with RTL, design verification, and physical design teams to develop CPU implementation. Drive performance correlation between the performance model and RTL implementation, including micro-benchmark development and pre-silicon and post-silicon performance bug triage. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.