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Minimum qualifications: PhD degree in Electronics and Communication Engineering, Electrical Engineering, Computer Engineering or related technical field, or equivalent practical experience. Experience with accelerator architectures and data center workloads. Experience in programming languages (e.g., C++, Python, Verilog), Synopsys, Cadence tools. Preferred qualifications: 2 years of experience post PhD. Experience with performance modeling tools. Knowledge of arithmetic units, bus architectures, accelerators, or memory hierarchies. Knowledge of high performance and low power design techniques. About the jobIn this role, you will shape the future of AI/ML hardware acceleration as a Silicon Architect/Design Engineer and drive cutting-edge TPU (Tensor Processing Unit) technology that fuels Google's most demanding AI/ML applications. You will collaborate with hardware and software architects and designers to architect, model, analyze, define and design next-generation TPUs. You will have dynamic, multi-faceted responsibilities in areas such as product definition, design, and implementation, collaborating with the Engineering teams to drive the optimal balance between performance, power, features, schedule, and cost.The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide. We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.Responsibilities Revolutionize Machine Learning (ML) workload characterization and benchmarking, and propose capabilities and optimizations for next-generation TPUs. Develop architecture specifications that meet current and future computing requirements for AI/ML roadmap. Develop architectural and microarchitectural power/performance models, microarchitecture and RTL designs and evaluate quantitative and qualitative performance and power analysis. Partner with hardware design, software, compiler, Machine Learning (ML) model and research teams for effective hardware/software codesign, creating high performance hardware/software interfaces. Develop and adopt advanced AI/ML capabilities, drive accelerated and efficient design verification strategies and implementations. Use AI techniques for faster and optimal Physical Design Convergence -Timing, floor planning, power grid and clock tree design etc. Investigate, validate, and optimize DFT, post-silicon test, and debug strategies, contributing to the advancement of silicon bring-up and qualification processes. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.

Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 10 years of experience in ASIC development with Verilog/SystemVerilog, Vhsic Hardware Description Language (VHDL). Experience in micro-architecture and design IPs and subsystems. Experience in ASIC design verification, synthesis, timing/power analysis, and Design for Testing (DFT). Preferred qualifications: Experience with scripting languages (e.g., Python or Perl). Experience in SoC designs and integration flows. Knowledge of bus architectures, fabrics/NoC, processor design, accelerators, or memory hierarchies.. Knowledge of high-performance and low-power design techniques. About the jobIn this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. In this role, you will be part of a team developing Application-Specific Integrated Circuits (ASIC) used to accelerate and improve traffic efficiency in data centers. You will collaborate with members of architecture, verification, power and performance, physical design, etc. to specify and deliver high quality designs for next generation data center accelerators. You will solve technical problems with innovative micro-architecture and practical logic solutions, and evaluate design options with complexity, performance, power and area in mind.The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide. We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.Responsibilities Drive development of complex IPs and subsystems along with a team of engineers. Own micro-architecture and implementation of IPs and subsystems. Work with architecture, firmware and software teams to drive feature closure and develop micro-architecture specifications. Drive design methodology, libraries, debug, code review in coordination with other IPs Design Verification (DV) teams and physical design teams. Identify and drive power, performance and area improvements for the domains owned. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.

Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. 8 years of experience in ASIC/SoC architecture, logic design, or systems engineering. Experience defining and specifying boot, reset, and power management architectures for SoCs. Experience in hardware security principles (e.g., secure boot, hardware root of trust, secure debug). Experience in debug and trace architectures, specifically with ARM CoreSight infrastructure. Preferred qualifications: Master’s degree or PhD in Electrical Engineering, Computer Engineering, or a related field. Experience with AI/ML accelerator architectures or high-performance computing (HPC) SoCs. Experience taking a complex SoC from early concept definition through to post-silicon bring-up and debug. Knowledge of PCIe (Peripheral Component Interconnect Express) architecture and integration. Excellent communication and documentation skills, with the ability to lead and influence cross-functional engineering teams. About the jobIn this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide. We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.Responsibilities Define and architect SoC-level debug and trace features, heavily utilizing ARM CoreSight and custom debug IPs to enable deep visibility into complex, multi-die AI systems. Partner with IP design, SoC integration, Design Verification (DV), and low-level software/firmware teams to translate architectural requirements into executable specifications. Drive the definition of the SoC power management architecture, including power domains, low-power states, and power sequencing. Conduct PPA (Power, Performance, Area) analysis to make data-driven architectural decisions. Architect robust and scalable boot, initialization, and reset sequences across the entire SoC and Security. Define hardware security architectures, including secure boot, cryptographic isolation, and debug security/entitlement mechanisms. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.

Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 8 years of experience in Application-Specific Integrated Circuit/System on a chip (ASIC/SoC) development with Verilog/SystemVerilog. Experience in micro-architecture and design of IPs and Subsystems. Experience in ASIC design verification, synthesis, timing/power analysis, and Design for Testing (DFT). Preferred qualifications: Master's or PhD degree in Electrical Engineering, Computer Engineering, or Computer Science, with an emphasis on computer architecture. Experience with scripting languages (e.g., Python or Perl). Experience in SoC designs and integration flows. Knowledge of high performance and low power design techniques. Knowledge of bus architectures, fabrics/NoC, processor design, accelerators, or memory hierarchies. About the jobBe part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. In this role, you will join a team developing Application-Specific Integrated Circuits (ASICs) to accelerate Machine Learning (ML) computation in data centers. You will collaborate with Architecture, Verification, Power and Performance, and Physical Design teams to specify and deliver quality designs for next-generation accelerators. You will solve technical problems through micro-architecture innovation and evaluate design trade-offs between performance and power.The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide. We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.Responsibilities Own micro-architecture and implementation of complex subsystems. Work with Architecture, Firmware and Software teams to drive feature closure and develop microarchitecture specifications.  Drive design methodology, libraries, debug, code review in coordination with other IPs Design Verification (DV) teams and physical design teams. Identify and drive Power, Performance and Area improvements for the domains owned. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.

Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Bengaluru, Karnataka, India; Hyderabad, Telangana, India.Minimum qualifications: Bachelor’s degree in Computer Science, related technical field, or equivalent practical experience. 15 years of experience in software engineering or related field. Experience building software and distributed systems, and working on enterprise cloud applications and products. Experience with the software development lifecycle process, including analysis and design, APIs, development tools and technologies. Experience guiding and influencing software engineers without direct management responsibility, working with data, APIs, and metrics oriented products. Preferred qualifications: Experience balancing engineering priorities against timelines, execution urgency, and innovation. Experience designing and building Agents leveraging LLMs to transform various business processes in enterprise applications. Ability to direct the full product lifecycle and software development, from outlook and roadmap execution to building scalable systems and coaching high-talent teams. Ability to set and drive the “big picture” strategy, while also contributing directly and providing detailed guidance on individual projects. Innovative problem-solving skills, with an ability to develop creative solutions in ambiguous environments. Excellent communication skills, with the ability to influence without authority and work with technical/cross-functional teams. About the jobGoogle Cloud Business Platform (GCBP) is a unified platform that streamlines workflows, fosters collaboration, and provides a cohesive, efficient ecosystem for customers, partners, and Googlers. Within GCBP, the Area Tech Leads (ATL) team is responsible for managing technical and functional architecture across the entire lead to cash business process to ensure a scalable and consistent architecture across the business process to provide a delightful experience to our users.As Principal Engineer, you will guide the architecture of highly scalable enterprise applications used by all Google Cloud customers and partners, as well as many Googlers across the Sales, Marketing, Finance, and Customer Success organizations. You will have technical oversight of first-party platforms and related aspects of architecture, technology platform choices, features, and consult on the designing and planning for integration of third-party technologies. You will act as a key stakeholder in defining complex technical and functional architectural designs across key business flows balancing both short-term tactical approaches and longer term strategies. You will coach software engineers and teams, and set organizational engineering excellence best practices. Working closely with counterparts across GCBP and other Google Cloud teams, you will drive technology innovation that has a significant, real-world impact in enabling Google Cloud’s continued growth and leadership.Google Cloud accelerates every organization’s ability to digitally transform its business and industry. We deliver enterprise-grade solutions that leverage Google’s cutting-edge technology, and tools that help developers build more sustainably. Customers in more than 200 countries and territories turn to Google Cloud as their trusted partner to enable growth and solve their most critical business problems.Responsibilities Provide technical outlook and strategy for the GCBP organization. Contribute to the broader Google Cloud Business outlook. Deliver high quality and impactful launches through close partnership with all of GCBP and the Google Cloud Business teams. Build a collaborative work environment, helping others in the organization execute to their maximum potential, and actively develop and expand talent through effective mentoring and coaching. Partner closely with product management, program management, engineering and other teams to create, drive, and deliver an innovative, compelling experience to our customers. Identify and solve cross-functional and inter-team issues efficiently. Lead software development efforts by driving architecture selection, software design, execution, and operations to build out architectures that are resilient to change. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.

Minimum qualifications: Bachelor's degree in Electrical, Electronics, Communication, Computer Engineering, a related field, or equivalent practical experience. 8 years of experience with implementation and validation of various DFT technologies. Experience with multiple projects in DFT design and verification, DFT specification, definition, architecture, and insertion. Experience with DFT techniques and tools, ASIC DFT synthesis, simulation, and verification flow. Experience in leading DFT activities throughout an ASIC development flow. Preferred qualifications: Master's degree in Electrical Engineering, or a related field. Experience in IP integration (e.g., memories, test controllers, TAP, and MBIST). Experience in SoC cycles, including silicon bring-up and silicon debug activities. Experience in fault modeling. About the jobIn this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. In this role, you will be responsible for defining, implementing, and deploying advanced Design for Testing (DFT) methodologies for digital, mixed-signal chips, or IPs. You will define silicon test strategies, DFT architecture, and create DFT specifications for the next generation System on a Chip (SoCs). You will design, insert, and verify the DFT logic. You will prepare for post-silicon and co-work/debug with test engineers. You will be responsible for reducing test cost, increasing production quality, and enhancing yield.The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.Responsibilities Develop DFT strategy and architecture (e.g., hierarchical DFT, DFT for High speed IOs, Analog DFT). Develop and drive die level DFT validation strategy and complete all Test Design Rule Checks (TDRC) and design changes to fix TDRC violations to achieve high-test quality. Integrate DFT logic, boundary scan, scan chains, DFT compression, Logic BIST, TAP controller, clock control block, and other DFT IP blocks. Document DFT architecture, test sequences, and boot-up sequences associated with test pins. Generate and deliver the production and debug patterns to Post Silicon Engineering team and run diagnosis for post silicon supports. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.

Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. 4 years of experience in ASIC development with Verilog, SystemVerilog, Very High Speed Integrated Circuit (VHSIC), Hardware Description Language, or Chisel. Experience with micro-architecture and designing IPs and subsystems. Experience in ASIC design verification, synthesis, timing/power analysis, and design for testing. Preferred qualifications: Experience with coding languages (e.g., Python or Perl). Experience in System on a Chip (SoC) designs and integration flows. Knowledge of arithmetic units, bus architectures, processor design, accelerators, or memory hierarchies. Knowledge of high performance and low power design techniques. About the jobBe part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. In this role, you will be part of a team developing Application-specific integrated circuit (ASICs) used to accelerate machine learning computation in data centers. You will collaborate with members of architecture, verification, power and performance, physical design to specify and deliver quality designs for next generation data center accelerators. You will solve technical problems with micro-architecture and practical reasoning solutions, and evaluate design options with complexity, performance, and power.The ML, Systems, Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world. We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Cloud’s Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.Responsibilities Own microarchitecture and implementation of Internet Protocol (IP) and subsystems. Work with Architecture, Firmware, and Software teams to drive feature closure and develop micro-architecture specifications. Drive design methodology, libraries, debug, code review in coordination with other IP Design Verification (DV) teams and physical design teams. Identify and drive power, performance and area of improvements. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.

Minimum qualifications:Bachelor's degree or equivalent practical experience.8 years of experience in software development.5 years of experience building and developing large - scale infrastructure, distributed systems or networks, or experience with compute technologies, storage, or hardware architecture.Experience in architecting and designing a distributed system in a public cloud environment (e.g., Google Cloud Platform).Experience working with Kubernetes, public cloud infrastructure, and cloud security.Experience in developing and maintaining backend systems.Preferred qualifications: 5 years of experience in software development building large-scale platforms. Experience contributing to open source projects or working with open source community. Understanding of cloud architectures, public and private cloud based systems. Ability to navigate open-ended technical challenges and make proper trade-offs. About the jobGoogle Cloud's software engineers develop the next-generation technologies that change how billions of users connect, explore, and interact with information and one another. We're looking for engineers who bring fresh ideas from all areas, including information retrieval, distributed computing, large-scale system design, networking and data storage, security, artificial intelligence, natural language processing, UI design and mobile; the list goes on and is growing every day. As a software engineer, you will work on a specific project critical to Google Cloud's needs with opportunities to switch teams and projects as you and our fast-paced business grow and evolve. You will anticipate our customer needs and be empowered to act like an owner, take action and innovate. We need our engineers to be versatile, display leadership qualities and be enthusiastic to take on new problems across the full-stack as we continue to push technology forward. Google Distributed Cloud - Airgapped (GDCag) is a new, converged hardware and software solution that brings selected Google Cloud Platform services on-premises. It is designed for customers who need to run cloud workloads in air-gapped (no connectivity to Google Cloud Platform) and highly secure environments due to regulations or policies, while still gaining operational efficiency and a consistent Google Cloud Platform experience.Google Cloud accelerates every organization’s ability to digitally transform its business and industry. We deliver enterprise-grade solutions that leverage Google’s cutting-edge technology, and tools that help developers build more sustainably. Customers in more than 200 countries and territories turn to Google Cloud as their trusted partner to enable growth and solve their most critical business problems.Responsibilities Build a scalable platform that supports key business deliverables for Google Distributed Cloud - Airgapped. Work closely with a variety of Google Distributed Cloud - Airgapped teams, Google Cloud Platform teams, and external vendors to ensure the timely delivery of the Google Distributed Cloud - Airgapped software stack. Influence and shape the security architecture and roadmap of Google Distributed Cloud - Airgapped in live threat detection, vulnerabilities detection, and remediation. Collaborate with Google Distributed Cloud - Airgapped Product Management, Principals, and Architecture to solve broad, impactful problems to raise the bar for quality, robustness, operability, and velocity. Define Agentic Artificial Intelligence opportunities in Google Distributed Cloud - Airgapped in the space of fault remediation and architect, design, and land solutions. Drive alignment of Google Distributed Cloud - Airgapped security components with Google Cloud Platform security architecture. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.

Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. 8 years of experience with advanced foundry process nodes, design-technology co-optimization (DTCO), and circuit-level PPA for standard cells, SRAM, and IO/ESD design. 8 years of experience with CMOS, device physics, and circuit design principles, including the first-party IP, third-party IP, and design service vendor landscape. 8 years of experience with circuit characterization and modeling for digital design flows. Preferred qualifications: Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture. Experience partnering with wafer foundries, specifically in PDK management, design collateral integration, and debugging. Understanding of physical design implementation and DFT methodologies. Ability to develop test-chip architectures for advanced circuit characterization and post-silicon validation. About the jobBe part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.Responsibilities Manage IP vendors for standard cell libraries, SRAM compilers, GPIO, eFuse, OT, and process sensors. Analyze architecture and design specifications to drive new circuit designs, including standard cells and memory options, to meet stringent Performance, Power, Area (PPA) and cost goals on process nodes. Collaborate with foundry and test-chip teams to validate the functionality and characterization of new circuit topologies. Negotiate design and timelines with 3PIP vendors, engaging in technical and schedule trade-off discussions. Provide technical support to Architecture, Design, and Physical Design teams to optimize the use of foundation IPs for improved functionality and PPA. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.

Minimum qualifications: PhD degree in Electronics and Communication Engineering, Electrical Engineering, Computer Engineering, a related technical field, or equivalent practical experience. Experience in programming languages (e.g., C++, Python, Verilog), Synopsys, Cadence tools. Experience with accelerator architectures and data center workloads. Preferred qualifications: 2 years of experience in Silicon engineering post PhD. Experience with performance modeling tools. Knowledge of arithmetic units, bus architectures, accelerators, or memory hierarchies. Knowledge of high-performance and low-power design techniques. About the jobIn this role, you will shape the future of AI/ML hardware acceleration as a Silicon Architect/Design Engineer and drive Tensor Processing Unit (TPU) technology that fuels Google's most demanding AI/ML applications. You will collaborate with hardware and software architects and designers to architect, model, analyze, define and design next-generation TPUs. You will have dynamic, multi-faceted responsibilities in areas such as product definition, design, and implementation, collaborating with the Engineering teams to drive the optimal balance between performance, power, features, schedule, and cost.Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.Responsibilities Revolutionize Machine Learning (ML) workload characterization and benchmarking, and propose capabilities and optimizations for next-generation TPUs. Develop architecture specifications that meet current and future computing requirements for AI/ML roadmap. Develop architectural and microarchitectural power/performance models, microarchitecture and RTL designs and evaluate quantitative and qualitative performance and power analysis. Partner with hardware design, software, compiler, Machine Learning (ML) model and research teams for effective hardware/software codesign, creating high performance hardware/software interfaces. Develop and adopt advanced AI/ML capabilities, drive accelerated and efficient design verification strategies and implementations. Use AI techniques for faster and optimal physical design convergence-timing, floor planning, power grid and clock tree design, etc. Investigate, validate, and optimize DFT, post-silicon test, and debug strategies, contributing to the advancement of silicon bring-up and qualification processes. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.