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Google welcomes people with disabilities.Note: By applying to this position you will have an opportunity to share your preferred working location from the following: New Taipei, Banqiao District, New Taipei City, Taiwan; Zhubei, Zhubei City, Hsinchu County, Taiwan.Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. 8 years of experience with computer architecture concepts, including micro architecture, cache hierarchy, pipelining, and memory subsystems. 3 years of experience working with mobile or embedded SoCs architecture or use case system design. Preferred qualifications: Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science. 5 years of experience working with mobile or embedded SoCs related to system design to improve use case level power and performance. Experience driving system architecture decisions across SW/HW teams within an organization to build up the consensus and translate ideas into architecture specifications. Experience with android architecture, mobile SoC architecture, ML architecture, computer architecture, PPA trade-offs. Knowledge of interactions between software and HW IP blocks, general and special purpose compute units. About the jobBe part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. As part of the Platform System Architecture team, you will leverage the expertise in computer and AI/ML architecture, Power, Performance, and Area (PPA) trade-offs, mobile SoC AI/ML workloads analysis, ability to traverse across the Software (SW)/Hardware (HW) stack to influence IP and SoC architecture for the Tensor SoC to bring in the latest AI/ML user experience on Pixel devices.Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.Responsibilities Influence Tensor SoC architecture decisions for PPA working cross-functionally with SW/HW architects, design teams, and research teams to enable the industrial best user experience on Pixel phone devices empowered by the latest and the most advanced Generative AI technologies provided by Google research. Leverage a data driven approach through profiling, simulation and modeling, drive consensus around architectural decisions across the entire silicon organization to solve system design problems. Be the primary owner of the architecture specifications, system design documentation, workload analysis, modeling and projection to influence and define future SoC architecture. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.

Google welcomes people with disabilities.Note: By applying to this position you will have an opportunity to share your preferred working location from the following: New Taipei, Banqiao District, New Taipei City, Taiwan; Zhubei, Zhubei City, Hsinchu County, Taiwan.Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or equivalent practical experience. 8 years of experience in microprocessor architecture, micro-architecture, performance, or advanced CPU design. Experience in CPU architecture, performance modeling, analysis, correlation, and workload characterization. Experience with C/C++ and scripting languages (e.g., Python). Preferred qualifications: PhD in Electrical Engineering, Computer Engineering, or Computer Science. Experience in leading CPU/ML micro-architecture exploration, performance model development, performance analysis, performance correlation, and workload characterization. Knowledge of processor instruction set architecture (e.g., ARM, RISC-V, x86). Knowledge of system software components (e.g., Linux, drivers, and runtime). Excellent communication skills. About the jobBe part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. In this role, you will be the key contributor to improve processor instruction set architecture, develop micro-architecture features, and to deliver Google’s SoC products. You will have the opportunity to collaborate with Google’s Android applications and AI teams to plan and conduct application and benchmark performance analysis.Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.Responsibilities Plan and evaluate ARM’s architecture features from both architecture and performance aspects. Develop a performance model for performance analysis and micro-architecture study. Define and write CPU subsystem architecture specifications. Lead collaborate with RTL, design verification, and physical design teams to develop CPU implementation. Drive performance correlation between the performance model and RTL implementation, including micro-benchmark development and pre-silicon and post-silicon performance bug triage. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.

Google welcomes people with disabilities.Note: By applying to this position you will have an opportunity to share your preferred working location from the following: New Taipei, Banqiao District, New Taipei City, Taiwan; Zhubei, Zhubei City, Hsinchu County, Taiwan.Minimum qualifications: Bachelor's degree in Electrical Engineering, a related field, or equivalent practical experience. 3 years of experience developing random stress tests, silicon validation frameworks, or related infrastructure. Experience programming in C/C++. Experience in Advanced RISC Machines (ARM) architecture and in IP level power management, Dynamic Voltage and Frequency Scaling (DVFS), or SoC/CPU/memory power management. Preferred qualifications: Experience executing tests on emulation platforms or Field Programmable Gate Array (FPGA) and with board level debug. Experience with complex system debug, embedded operating systems, and bare metal programming. Experience with JTAG debuggers (e.g., Lauterbach). Knowledge of low power design and architecture techniques. Knowledge of operating system fundamentals. Familiarity with Power Management Integrated Circuit (PMIC) and power modeling techniques. About the jobGoogle engineers develop the next-generation technologies that change how users connect, explore, and interact with information and one another. As a member of an extraordinarily creative, motivated and talented team, you develop new products that are used by millions of people. We need our engineers to be versatile and passionate to take on new problems as we continue to push technology forward. If you get excited about building new things and working across discipline lines, then our team might be your next career step. In this role, you will be a part of Google’s Silicon team, working to enable Google’s continuous innovations. You'll be responsible for bare-metal and operating system based validation, including both pre-silicon verification and post-silicon bring-up and validation, ensuring the delivery of high-quality silicon.Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.Responsibilities Plan, develop, and execute tests to validate IP, subsystem, and system level power management. Manage power correlation and power management design validation on pre-silicon and post-silicon platforms. Interface with Software, Architecture, Design, and Design Verification teams to create and execute test plans Support silicon debug and field failures. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.

1. Responsible for developing and executing design flow for Power IC module.2. Familiar with the architecture of buck converter / driver / amplifier3. Co-work with testing engineer to achieve the mass production4. Familiar with working principle of the power MOS device

1. Responsible for developing the Power IC module product lines. 2. Lead the project and inspire the team. 3. Demonstrate ambition in driving the product from specification, design, engineering, validation, debugging to mass production. 4. Familiar with the architecture of buck converter / driver / amplifier, working principle of the power MOS device.

1. Responsible for developing and executing design flow for Sensor IC.2. Familiar with the architecture of Sensor Interface / Signal Chain3. Expertise in any of the following areas: High CMRR low offset amplifier/High voltage amplifier /High precision ADC(DSM or SAR)/ Low Temperature Drift Bandgap4. Co-work with testing engineer to achieve the mass production