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Minimum qualifications: PhD degree in Electronics and Communication Engineering, Electrical Engineering, Computer Engineering or related technical field, or equivalent practical experience. Experience with accelerator architectures and data center workloads. Experience in programming languages (e.g., C++, Python, Verilog), Synopsys, Cadence tools. Preferred qualifications: 2 years of experience post PhD. Experience with performance modeling tools. Knowledge of arithmetic units, bus architectures, accelerators, or memory hierarchies. Knowledge of high performance and low power design techniques. About the jobIn this role, you will shape the future of AI/ML hardware acceleration as a Silicon Architect/Design Engineer and drive cutting-edge TPU (Tensor Processing Unit) technology that fuels Google's most demanding AI/ML applications. You will collaborate with hardware and software architects and designers to architect, model, analyze, define and design next-generation TPUs. You will have dynamic, multi-faceted responsibilities in areas such as product definition, design, and implementation, collaborating with the Engineering teams to drive the optimal balance between performance, power, features, schedule, and cost.The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide. We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.Responsibilities Revolutionize Machine Learning (ML) workload characterization and benchmarking, and propose capabilities and optimizations for next-generation TPUs. Develop architecture specifications that meet current and future computing requirements for AI/ML roadmap. Develop architectural and microarchitectural power/performance models, microarchitecture and RTL designs and evaluate quantitative and qualitative performance and power analysis. Partner with hardware design, software, compiler, Machine Learning (ML) model and research teams for effective hardware/software codesign, creating high performance hardware/software interfaces. Develop and adopt advanced AI/ML capabilities, drive accelerated and efficient design verification strategies and implementations. Use AI techniques for faster and optimal Physical Design Convergence -Timing, floor planning, power grid and clock tree design etc. Investigate, validate, and optimize DFT, post-silicon test, and debug strategies, contributing to the advancement of silicon bring-up and qualification processes. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.

Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 10 years of experience in ASIC development with Verilog/SystemVerilog, Vhsic Hardware Description Language (VHDL). Experience in micro-architecture and design IPs and subsystems. Experience in ASIC design verification, synthesis, timing/power analysis, and Design for Testing (DFT). Preferred qualifications: Experience with scripting languages (e.g., Python or Perl). Experience in SoC designs and integration flows. Knowledge of bus architectures, fabrics/NoC, processor design, accelerators, or memory hierarchies.. Knowledge of high-performance and low-power design techniques. About the jobIn this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. In this role, you will be part of a team developing Application-Specific Integrated Circuits (ASIC) used to accelerate and improve traffic efficiency in data centers. You will collaborate with members of architecture, verification, power and performance, physical design, etc. to specify and deliver high quality designs for next generation data center accelerators. You will solve technical problems with innovative micro-architecture and practical logic solutions, and evaluate design options with complexity, performance, power and area in mind.The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide. We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.Responsibilities Drive development of complex IPs and subsystems along with a team of engineers. Own micro-architecture and implementation of IPs and subsystems. Work with architecture, firmware and software teams to drive feature closure and develop micro-architecture specifications. Drive design methodology, libraries, debug, code review in coordination with other IPs Design Verification (DV) teams and physical design teams. Identify and drive power, performance and area improvements for the domains owned. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.

Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. 8 years of experience in ASIC/SoC architecture, logic design, or systems engineering. Experience defining and specifying boot, reset, and power management architectures for SoCs. Experience in hardware security principles (e.g., secure boot, hardware root of trust, secure debug). Experience in debug and trace architectures, specifically with ARM CoreSight infrastructure. Preferred qualifications: Master’s degree or PhD in Electrical Engineering, Computer Engineering, or a related field. Experience with AI/ML accelerator architectures or high-performance computing (HPC) SoCs. Experience taking a complex SoC from early concept definition through to post-silicon bring-up and debug. Knowledge of PCIe (Peripheral Component Interconnect Express) architecture and integration. Excellent communication and documentation skills, with the ability to lead and influence cross-functional engineering teams. About the jobIn this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide. We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.Responsibilities Define and architect SoC-level debug and trace features, heavily utilizing ARM CoreSight and custom debug IPs to enable deep visibility into complex, multi-die AI systems. Partner with IP design, SoC integration, Design Verification (DV), and low-level software/firmware teams to translate architectural requirements into executable specifications. Drive the definition of the SoC power management architecture, including power domains, low-power states, and power sequencing. Conduct PPA (Power, Performance, Area) analysis to make data-driven architectural decisions. Architect robust and scalable boot, initialization, and reset sequences across the entire SoC and Security. Define hardware security architectures, including secure boot, cryptographic isolation, and debug security/entitlement mechanisms. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.

Minimum qualifications: Bachelor's degree in Electrical, Electronics, Communication, Computer Engineering, a related field, or equivalent practical experience. 8 years of experience with implementation and validation of various DFT technologies. Experience with multiple projects in DFT design and verification, DFT specification, definition, architecture, and insertion. Experience with DFT techniques and tools, ASIC DFT synthesis, simulation, and verification flow. Experience in leading DFT activities throughout an ASIC development flow. Preferred qualifications: Master's degree in Electrical Engineering, or a related field. Experience in IP integration (e.g., memories, test controllers, TAP, and MBIST). Experience in SoC cycles, including silicon bring-up and silicon debug activities. Experience in fault modeling. About the jobIn this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. In this role, you will be responsible for defining, implementing, and deploying advanced Design for Testing (DFT) methodologies for digital, mixed-signal chips, or IPs. You will define silicon test strategies, DFT architecture, and create DFT specifications for the next generation System on a Chip (SoCs). You will design, insert, and verify the DFT logic. You will prepare for post-silicon and co-work/debug with test engineers. You will be responsible for reducing test cost, increasing production quality, and enhancing yield.The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.Responsibilities Develop DFT strategy and architecture (e.g., hierarchical DFT, DFT for High speed IOs, Analog DFT). Develop and drive die level DFT validation strategy and complete all Test Design Rule Checks (TDRC) and design changes to fix TDRC violations to achieve high-test quality. Integrate DFT logic, boundary scan, scan chains, DFT compression, Logic BIST, TAP controller, clock control block, and other DFT IP blocks. Document DFT architecture, test sequences, and boot-up sequences associated with test pins. Generate and deliver the production and debug patterns to Post Silicon Engineering team and run diagnosis for post silicon supports. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.

Logitech is the Sweet Spot for people who want their actions to have a positive global impact while having the flexibility to do it in their own way.About the RoleLogitechs product ecosystem spans embedded hardware, desktop software, and cloud services, and the security of everything we build sits at the heart of what this team does.As a Product Security Architect, you will work across Logitechs full portfolio of internally built and self-hosted applications, providing security architecture guidance, threat modeling expertise, and hands-on consultancy to engineering teams throughout the product development lifecycle.Your scope will deliberately span both product and enterprise software. Whether you are reviewing the secure design of a companion desktop application or advising on the authentication architecture of an internal enterprise service, you will be the security voice that engineering teams turn to before problems emerge.You will work closely with Product Managers, Engineers, and fellow security team members, using a combination of deep technical expertise and modern AI-assisted tooling to embed security early and at scale across Logitechs engineering organization.What You Will DoSecure Architecture DesignDefine and own the secure architecture standards across Logitechs in-house built and self-hosted applications, spanning product ecosystems and enterprise servicesDesign secure communication pathways, trust boundaries, authentication frameworks, and cryptographic standards across our full software stackEstablish reusable, scalable security patterns that engineering teams can adopt without slowing down deliveryThreat Modeling Risk AdvisoryLead threat modeling exercises across new and existing products, leveraging AI models to accelerate baseline generation and focusing your expertise on complex, Logitech-specific attack vectorsIdentify architectural risks early in the SDLC and translate them into clear, prioritized, and actionable engineering requirementsMaintain a living view of our internal threat landscape and evolving attack surfaces, including AI-integrated product featuresInternal Security ConsultancyServe as the trusted security partner for Product Managers, Lead Engineers, and Engineering Directors during ideation and design phasesDrive security reviews and design consultations across multiple product squads simultaneously, ensuring security remains an accelerator rather than a blockerDefine testing scopes and critical attack paths to guide offensive security and validation effortsAI Feature Integration SecurityAct as the primary security authority for AI features being embedded into Logitech products and services — including on-device ML models, cloud-hosted LLM integrations, and AI data pipelinesDefine security guardrails for generative AI integrations, covering risks such as prompt injection, insecure output handling, and training data exposureWhat You BringExperience6 years in Application Security, Product Security, or Security Architecture roles covering a diverse and complex software portfolioDemonstrated experience designing secure architectures across both product-facing and enterprise internal applicationsTrack record of influencing engineering culture and embedding security practices early in the development lifecycleTechnical SkillsDeep expertise in threat modeling methodologiesStrong command of modern authentication and authorization protocols (OAuth 2.0, OIDC) and secure API design principlesSolid understanding of cryptographic fundamentals and their practical application in software systemsFamiliarity with cloud-native security architectures (AWS, GCP, or Azure) and self-hosted infrastructure securityWorking knowledge of secure SDLC frameworks (OWASP SAMM or equivalent)AI Modern Security PracticesPractical experience using AI and LLM tools to accelerate threat modeling, architecture reviews, or security researchUnderstanding of AI/ML security risks, including adversarial inputs, model extraction, prompt injection, and data pipeline securitySoft SkillsExceptional communication skills — you can speak to a firmware engineer and a VP of Engineering in the same day and be equally effective with bothStrong consultancy mindset: you influence without authority and build long-term trust with engineering teamsAcross Logitech we empower collaboration and foster play. We help teams collaborate/learn from anywhere, without compromising on productivity or continuity so it should be no surprise that most of our jobs are open to work from home from most locations. Our hybrid work model allows some employees to work remotely while others work on-premises. Within this structure, you may have teams or departments split between working remotely and working in-house.Logitech is an amazing place to work because it is full of authentic people who are inclusive by nature as well as by design. Being a global company, we value our diversity and celebrate all our differences. Don’t meet every single requirement? Not a problem. If you feel you are the right candidate for the opportunity, we strongly recommend that you apply. We want to meet you!We offer comprehensive and competitive benefits packages and working environments that are designed to be flexible and help you to care for yourself and your loved ones, now and in the future. We believe that good health means more than getting medical care when you need it. Logitech supports a culture that encourages individuals to achieve good physical, financial, emotional, intellectual and social wellbeing so we all can create, achieve and enjoy more and support our families. We can’t wait to tell you more about them being that there are too many to list here and they vary based on location.All qualified applicants will receive consideration for employment without regard to race, sex, age, color, religion, sexual orientation, gender identity, national origin, protected veteran status, or on the basis of disability.If you require an accommodation to complete any part of the application process, are limited in the ability, are unable to access or use this online application process and need an alternative method for applying, you may contact us toll free at 1-510-713-4866 for assistance and we will get back to you as soon as possible.

Minimum qualifications:Bachelor's degree or equivalent practical experience.8 years of experience in software development.5 years of experience building and developing large - scale infrastructure, distributed systems or networks, or experience with compute technologies, storage, or hardware architecture.Experience in architecting and designing a distributed system in a public cloud environment (e.g., Google Cloud Platform).Experience working with Kubernetes, public cloud infrastructure, and cloud security.Experience in developing and maintaining backend systems.Preferred qualifications: 5 years of experience in software development building large-scale platforms. Experience contributing to open source projects or working with open source community. Understanding of cloud architectures, public and private cloud based systems. Ability to navigate open-ended technical challenges and make proper trade-offs. About the jobGoogle Cloud's software engineers develop the next-generation technologies that change how billions of users connect, explore, and interact with information and one another. We're looking for engineers who bring fresh ideas from all areas, including information retrieval, distributed computing, large-scale system design, networking and data storage, security, artificial intelligence, natural language processing, UI design and mobile; the list goes on and is growing every day. As a software engineer, you will work on a specific project critical to Google Cloud's needs with opportunities to switch teams and projects as you and our fast-paced business grow and evolve. You will anticipate our customer needs and be empowered to act like an owner, take action and innovate. We need our engineers to be versatile, display leadership qualities and be enthusiastic to take on new problems across the full-stack as we continue to push technology forward. Google Distributed Cloud - Airgapped (GDCag) is a new, converged hardware and software solution that brings selected Google Cloud Platform services on-premises. It is designed for customers who need to run cloud workloads in air-gapped (no connectivity to Google Cloud Platform) and highly secure environments due to regulations or policies, while still gaining operational efficiency and a consistent Google Cloud Platform experience.Google Cloud accelerates every organization’s ability to digitally transform its business and industry. We deliver enterprise-grade solutions that leverage Google’s cutting-edge technology, and tools that help developers build more sustainably. Customers in more than 200 countries and territories turn to Google Cloud as their trusted partner to enable growth and solve their most critical business problems.Responsibilities Build a scalable platform that supports key business deliverables for Google Distributed Cloud - Airgapped. Work closely with a variety of Google Distributed Cloud - Airgapped teams, Google Cloud Platform teams, and external vendors to ensure the timely delivery of the Google Distributed Cloud - Airgapped software stack. Influence and shape the security architecture and roadmap of Google Distributed Cloud - Airgapped in live threat detection, vulnerabilities detection, and remediation. Collaborate with Google Distributed Cloud - Airgapped Product Management, Principals, and Architecture to solve broad, impactful problems to raise the bar for quality, robustness, operability, and velocity. Define Agentic Artificial Intelligence opportunities in Google Distributed Cloud - Airgapped in the space of fault remediation and architect, design, and land solutions. Drive alignment of Google Distributed Cloud - Airgapped security components with Google Cloud Platform security architecture. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.

Minimum qualifications: Bachelor's degree in Electrical Engineering, a related field, or equivalent practical experience. 10 years of experience with silicon design, DV, implementation and chip integration. Experience with management in Application-Specific Integrated Circuit (ASIC) development teams. Experience in leading design teams with working on digital designs that have taped-out and produced working silicon and delivering silicon. Preferred qualifications: Experience with extraction of design parameters, Quality of Results (QoR) metrics, and analyzing data trends. Experience with engineering across design, DV, physical design, implementation, Graphic Data System (GDS) tape-out. Knowledge of delivery of silicon in technology process nodes. Ability to lead cross-functional teams. About the jobIn this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. In this role, you will be responsible for overseeing the design and development of chips for the products. You will be responsible for leading the chip design end-to-end, from architecture requirements up to tape-out.Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.Responsibilities Manage Register-Transfer Level (RTL) design, Design Verification (DV) and physical design of System-on-Chip (SoC) to tape-out while working with multiple team members. Evaluate and develop SoC design and Integration methodologies and decide on the SoC flow. Work with architects and reasoning designers to drive architectural feasibility studies, develop timing, power and area design goals, and explore RTL/design trade-offs for physical design closure. Participate in design reviews and track issue resolution, and engage in technical and schedule trade-off discussions. Create execution plans for projects and manage team efforts from concept to working silicon in volume. Understand architecture and design specifications with the larger team, and define physical design strategies and tactics to meet quality and schedule goals. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.

Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. 8 years of experience with advanced foundry process nodes, design-technology co-optimization (DTCO), and circuit-level PPA for standard cells, SRAM, and IO/ESD design. 8 years of experience with CMOS, device physics, and circuit design principles, including the first-party IP, third-party IP, and design service vendor landscape. 8 years of experience with circuit characterization and modeling for digital design flows. Preferred qualifications: Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture. Experience partnering with wafer foundries, specifically in PDK management, design collateral integration, and debugging. Understanding of physical design implementation and DFT methodologies. Ability to develop test-chip architectures for advanced circuit characterization and post-silicon validation. About the jobBe part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.Responsibilities Manage IP vendors for standard cell libraries, SRAM compilers, GPIO, eFuse, OT, and process sensors. Analyze architecture and design specifications to drive new circuit designs, including standard cells and memory options, to meet stringent Performance, Power, Area (PPA) and cost goals on process nodes. Collaborate with foundry and test-chip teams to validate the functionality and characterization of new circuit topologies. Negotiate design and timelines with 3PIP vendors, engaging in technical and schedule trade-off discussions. Provide technical support to Architecture, Design, and Physical Design teams to optimize the use of foundation IPs for improved functionality and PPA. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.

Minimum qualifications: PhD degree in Electronics and Communication Engineering, Electrical Engineering, Computer Engineering, a related technical field, or equivalent practical experience. Experience in programming languages (e.g., C++, Python, Verilog), Synopsys, Cadence tools. Experience with accelerator architectures and data center workloads. Preferred qualifications: 2 years of experience in Silicon engineering post PhD. Experience with performance modeling tools. Knowledge of arithmetic units, bus architectures, accelerators, or memory hierarchies. Knowledge of high-performance and low-power design techniques. About the jobIn this role, you will shape the future of AI/ML hardware acceleration as a Silicon Architect/Design Engineer and drive Tensor Processing Unit (TPU) technology that fuels Google's most demanding AI/ML applications. You will collaborate with hardware and software architects and designers to architect, model, analyze, define and design next-generation TPUs. You will have dynamic, multi-faceted responsibilities in areas such as product definition, design, and implementation, collaborating with the Engineering teams to drive the optimal balance between performance, power, features, schedule, and cost.Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.Responsibilities Revolutionize Machine Learning (ML) workload characterization and benchmarking, and propose capabilities and optimizations for next-generation TPUs. Develop architecture specifications that meet current and future computing requirements for AI/ML roadmap. Develop architectural and microarchitectural power/performance models, microarchitecture and RTL designs and evaluate quantitative and qualitative performance and power analysis. Partner with hardware design, software, compiler, Machine Learning (ML) model and research teams for effective hardware/software codesign, creating high performance hardware/software interfaces. Develop and adopt advanced AI/ML capabilities, drive accelerated and efficient design verification strategies and implementations. Use AI techniques for faster and optimal physical design convergence-timing, floor planning, power grid and clock tree design, etc. Investigate, validate, and optimize DFT, post-silicon test, and debug strategies, contributing to the advancement of silicon bring-up and qualification processes. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.

Minimum qualifications: PhD degree in Electronics and Communication Engineering, Electrical Engineering, Computer Engineering or related technical field, or equivalent practical experience. Experience in programming languages (e.g., C++, Python, Verilog), Synopsys, Cadence tools. Experience with accelerator architectures and data center workloads. Preferred qualifications: 2 years of experience in Silicon domain post PhD.Experience with performance modeling tools. Knowledge of arithmetic units, bus architectures, accelerators, or memory hierarchies. Knowledge of high performance and low power design techniques. About the jobIn this role, you will shape the future of AI/ML hardware acceleration as a Silicon Architect/Design Engineer and drive TPU (Tensor Processing Unit) technology that fuels Google's most demanding AI/ML applications. You will collaborate with hardware and software architects and designers to architect, model, analyze, define and design next-generation TPUs. You will have dynamic, multi-faceted responsibilities in areas such as product definition, design, and implementation, collaborating with the Engineering teams to drive the optimal balance between performance, power, features, schedule, and cost.Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.Responsibilities Revolutionize Machine Learning (ML) workload characterization and benchmarking, and propose capabilities and optimizations for next-generation TPUs. Develop architecture specifications that meet current and future computing requirements for AI/ML roadmap. Develop architectural and microarchitectural power/performance models, microarchitecture and RTL designs and evaluate quantitative and qualitative performance and power analysis. Partner with hardware design, software, compiler, Machine Learning (ML) model and research teams for effective hardware/software codesign, creating high performance hardware/software interfaces. Develop and adopt advanced AI/ML capabilities, drive accelerated and efficient design verification strategies and implementations. Use AI techniques for faster and optimal physical design convergence -timing, floor planning, power grid and clock tree design etc. Investigate, validate, and optimize DFT, post-silicon test, and debug strategies, contributing to the advancement of silicon bring-up and qualification processes. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.