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Google welcomes people with disabilities.Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. 8 years of experience with high-performance microprocessor architecture, CPU microarchitecture, and workload performance analysis. Experience in high-performance CPU architecture. Experience with at least one area: instruction set architecture (ISA), machine learning (ML), or branch prediction. Experience in performance modeling, analysis, correlation, and workload characterization. Experience with C/C++ and scripting languages (e.g., Python). Preferred qualifications: PhD degree in Electrical Engineering, Computer Engineering, or Computer Science, with a focus on computer architecture or machine learning. 6 years of high-performance microprocessor architecture, microarchitecture, performance, and design experience. Experience in leading CPU/ML performance model development, performance analysis, performance correlation, and workload characterization. Deep knowledge with processor instruction set architecture (e.g., ARM, RISC-V, x86). Knowledgeable on system software components, such as Linux, drivers, and runtime. About the jobBe part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. As a CPU architecture and performance architect, you'll be the key contributor to improve processor instruction set architecture, to develop innovative microarchitecture features, and to deliver Google’s advanced SoC products. You’ll have the opportunity to collaborate with talents in system performance and software teams to plan and conduct application and benchmark performance analysis and to project their performance at various design phases. Leveraging your CPU-specific knowledge and leadership, you’ll be guiding junior CPU architects and working with engineers in power, thermal, security, and physical design teams to determine the CPU subsystem configuration and features.Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.Responsibilities Drive performance correlation between the performance model and RTL implementation, including micro-benchmark development, pre-silicon performance correlation, and post-silicon performance analysis and debugging. Plan and evaluate CPU architecture features from both architecture and performance angles. Develop a performance model for performance analysis and microarchitecture design study. Collaborate with other teams, such as RTL design, design verification, and physical design, to develop a high performance and efficient CPU implementation. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.

Role summary: Customer-facing CSA focused on enterprise solution design, architecture governance, documentation, and project execution for complex Microsoft cloud transformation programs. Key responsibilities: Lead architecture discovery, requirements gathering, and technical design workshops with enterprise customers. Create high-level and low-level architecture documents, solution design documents, deployment plans, migration plans, and decision records. Translate business requirements into scalable, secure, and supportable Microsoft cloud architectures. Coordinate across customer stakeholders, project managers, engineers, partners, and Microsoft account teams. Drive architecture reviews, risk assessments, technical blockers, and implementation planning. Support Customer Success motions by aligning technical delivery to customer business outcomes, adoption, and operational readiness.Act as a trusted technical advisor to strategic enterprise customers.Drive adoption, consumption, health, and successful implementation of Microsoft cloud services.Identify technical blockers and coordinate resolution with support, engineering, partners, and account teams.Deliver architecture workshops, technical guidance, readiness sessions, and best-practice reviews.Align customer technical plans with business outcomes and measurable success criteria.Document customer architecture, risks, dependencies, recommendations, and next steps.

Role summary: Customer-facing Security CSA responsible for helping enterprise customers design, secure, monitor, and improve Microsoft cloud security architecture, with emphasis on Web Application Firewall, identity security, SIEM, and threat protection. Key responsibilities: Design secure cloud architectures using Microsoft security best practices and Zero Trust principles. Advise customers on Azure Web Application Firewall, Application Gateway, Front Door, DDoS Protection, and secure network design. Support identity and access architecture using Microsoft Entra ID, Conditional Access, MFA, Privileged Identity Management, and identity governance. Help customers deploy and optimize Microsoft Sentinel for SIEM, analytics rules, incidents, workbooks, and automation. Conduct security posture reviews and recommend improvements using Defender for Cloud and related Microsoft security tools.Partner with Customer Success and security stakeholders to improve adoption, risk reduction, and customer security outcomesAct as a trusted technical advisor to strategic enterprise customers.Drive adoption, consumption, health, and successful implementation of Microsoft cloud services.Identify technical blockers and coordinate resolution with support, engineering, partners, and account teams.Deliver architecture workshops, technical guidance, readiness sessions, and best-practice reviews.Align customer technical plans with business outcomes and measurable success criteria.Document customer architecture, risks, dependencies, recommendations, and next steps.

Google welcomes people with disabilities.Note: By applying to this position you will have an opportunity to share your preferred working location from the following: New Taipei, Banqiao District, New Taipei City, Taiwan; Zhubei, Zhubei City, Hsinchu County, Taiwan.Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering or Computer Science, with a focus on computer architecture, or equivalent practical experience. 4 years of experience in microprocessor architecture, microarchitecture, performance, or advanced CPU design. Experience in CPU architecture, performance modeling, analysis, correlation, and workload characterization. Experience with C/C++ and scripting languages (e.g., Python). Preferred qualifications: Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science, with an emphasis on computer architecture or machine learning. Experience in CPU/ML microarchitecture exploration, performance model development, performance analysis, performance correlation, or workload characterization. Knowledge of microprocessor instruction set architecture (e.g., ARM, RISC-V, x86). Familiarity with system software components, such as Linux, drivers, and runtime. About the jobAs a CPU Performance Architect, you will be the key contributor to improve processor instruction set architecture, to develop innovative microarchitecture features, and deliver Google’s advanced SoC products. You will collaborate cross-functionally with android applications and AI teams to conduct applications and benchmark performance analysis and to project their performance at various design phases. You will be guided by architects and work with engineers in Power, Thermal, Security, and Physical Design teams to determine the CPU subsystem configuration and features.Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.Responsibilities Develop and modify a performance model for performance analysis and microarchitecture study. Evaluate Advanced RISC Machine (ARM’s) architecture features from both architecture and performance angles. Define and write CPU subsystem architecture specifications. Collaborate with Register-Transfer Level (RTL), design verification, and physical design teams to develop a high-performance and efficient CPU implementation. Manage performance correlation between the performance model and RTL implementation, including micro-benchmark development and pre-silicon and post-silicon performance bug triage. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.

About the Role At Canner, we're building breakthrough AI and data infrastructure that transforms data from a static asset into the core engine of enterprise decision-making. As part of our RD team, you'll help drive the development and adoption of Wren AI. Wren AI is Canner's flagship open-source project, enabling Large Language Models (LLMs) to query enterprise data directly and providing AI Agents with precise semantic query capabilities. Our open-source repository has been featured on GitHub Top Trending for several consecutive weeks, accumulating nearly 15k+ stars and establishing itself as a leading global GenBI solution — a strong signal of worldwide developer recognition and demand. As a Forward Deployed Engineer (FDE), you'll be the engineer on the front line with our customers — deeply understanding their data architecture and business context, and turning Wren AI into the AI data infrastructure that powers their organization. You won't just respond to issues; you'll proactively drive customer success, channel frontline insights back to product, and accelerate our iteration cycle. If you're passionate about large-scale AI applications, working with international enterprises, serving global users, and learning the standards and expectations of multinational customers, this is an exceptional opportunity to participate in cutting-edge industry development. Responsibilities Serve as the technical partner and engineering point of contact for customers — understanding their data architecture, business needs, and use cases, and helping them plan and implement Wren AI best practices in their environment Lead customer onboarding and deployment, including data source connections (databases, data warehouses, etc.), semantic model (MDL) design and tuning, and AI model configuration and validation Design and build custom integrations, PoCs, demos, and technical validations tailored to each customer's data environment, demonstrating Wren AI's value in their specific context Triage, diagnose, and resolve technical issues customers encounter with the Wren AI platform/API — including natural language query accuracy, SQL generation, chart/report rendering, and API integration challenges Collaborate closely with Product and Engineering teams to translate customer needs and frontline insights into product issues and feature requests, and participate in testing fixes and validating new features Write and maintain technical documentation, integration guides, best practices, FAQs, and solution templates to improve customer self-service and team-wide support efficiency Track and respond to customer requests within SLA, ensuring high-quality and timely resolution Analyze customer usage patterns and recurring issues to proactively propose product improvements and customer success strategies — improving product stability, user experience, and retention Support Wren AI's open-source community growth and engagement — responding to GitHub issues/discussions, supporting community contributors, writing technical blog posts and example projects, and participating in community events to expand our global developer ecosystem

Google welcomes people with disabilities.Minimum qualifications: Bachelor’s degree in Electrical or Electronics Engineering, or equivalent practical experience. 2 years of experience in SoC Software, Architecture, or hardware validation, with mobile, Internet of Things (IoT), or consumer electronics. Experience with coding languages such as Python, Bash, or Perl for automating data collection, analysis, and report generation. Preferred qualifications: 4 years of experience in SoC Software, Architecture, or hardware validation, with mobile, Internet of Things (IoT), or consumer electronics. Experience in using lab test equipment like oscilloscopes, electronic loads, and network analyzers for mixed-signal validation. Experience with hardware, including working with pre-production silicon and evaluation platforms in a lab setting. Knowledge in working of operating systems (e.g., Android/IoS/Linux), including how OS interacts with the SoC's hardware for memory management, power management, and scheduling. About the jobBe part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. The Google Pixel team focuses on designing and delivering the world's most helpful mobile experience. The team works on shaping the future of Pixel devices and services through some of the most advanced designs, techniques, products, and experiences in consumer electronics. This includes bringing together the best of Google’s artificial intelligence, software, and hardware to build global smartphones and create transformative experiences for users across the world.Responsibilities Conduct technical and market-based analysis of System on a Chip (SoCs), covering areas such as architecture, performance, features, and cost. Lead technical tear-downs and benchmark activities to gather detailed intelligence on participants products. Develop and maintain engaging intelligence reports, including market landscapes, product road maps, and feature comparisons. Collaborate with cross-functional teams, including engineering, marketing, and business to support product planning and Go-to-Market (GTM) strategies. Monitor industry trends, emerging technologies, and participants moves to provide analysis. Use data analysis tools and techniques to reconcile datasets and deliver insights. Maintain and update internal engaging databases and repositories of technical information. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.

Google welcomes people with disabilities.Minimum qualifications: Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field or equivalent practical experience. 4 years of work experience in Consumer Electronics/embedded system design or electrical systems development. 4 years of experience with signal and power integrity simulation of system boards, including SoC/chipset, Memory technology, and other communication interfaces. Preferred qualifications: MS degree or PhD in Electrical Engineering or Computer Engineering. 8 years of working experience with implementing a product development process for mass volume production design, with a focus on signal integrity, power integrity and electromagnetic interference (EMI). Experience with managing SIPI trade-off decisions with cross functional teams to define an optimized solution that meets product design requirements. Experience with industry SIPI simulation and lab tools (e.g. Ansys HFSS, SIwave, Designer, Cadence Sigrity tools, ADS, Hspice, TDR, VNA). Strong fundamental understanding of hardware system architecture, spanning SOC, PMIC, Audio, sensors, display, touch, camera or RF subsystems. About the jobbr/br Googles mission is to organize the worlds information and make it universally accessible and useful. Our Devices Services team combines the best of Google AI, Software, and Hardware to create radically helpful experiences for users. We research, design, and develop new technologies and hardware to make our users interaction with computing faster, seamless, and more powerful. Whether finding new ways to capture and sense the world around us, advancing form factors, or improving interaction methods, the Devices Services team is making peoples lives better through technology.Responsibilities Design Google's future products by managing architecture selection, electrical design, and validation, including early product architecture definition and manage Signal Integrity (SI) and Power Integrity (PI) of products and sub-component development. Provide detailed SI/PI rules for cutting-edge PCB and Flex technology and participate in PCB design reviews and drive resolution of SI/PI challenges in collaboration with Design Engineer, PCB Designer, and System teams. Provide simulation and DOEs to support cross-functional teams on SI/PI debugging, root-cause analysis, and solution optimization and work with Engineering/Qualification teams on system bring-up and design validation. Bring Pixel design to mass production by defining ERS, analyzing test data, assisting in software bring-up, and traveling on-site to ensure successful manufacturing and testing. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.

📋 Job Responsibilities We are seeking senior technical anchors across three core disciplines to join our newly established advanced server infrastructure wing. You will hold high levels of autonomy to architect, design, and validate the thermal and structural future of next-generation AI high-performance computing platforms. 🔹 Liquid cooling System Architecture Development: Own the structural layout, architecture definition, and initial prototyping for next-generation High-Performance Computing (HPC/AI) liquid cooling products and critical server-level thermal components (including CDUs and Manifolds).Cooling Path Planning: Lead complex internal cooling fluid path planning, execute optimized thermal component/radiator selection, and engineer high-efficiency pump configurations.Manufacturing Alignment Collaboration: Review and evaluate key production processes (including welding, stamping, and CNC machining); collaborate deeply with internal mechanical forces to deliver scalable technical solutions to tier-1 global clients and suppliers. 🔹 Thermal Simulation Modeling: Conduct independent, high-precision thermal and fluid dynamics modeling utilizing advanced CFD software suites (such as Fluent, Icepak, FloTHERM, and CFX).Design Optimization: Lead advanced heat dissipation module optimizations, execute meticulous thermal resistance analyses, and conduct rigorous evaluations of materials' thermal characteristics.Cross-Disciplinary Integration: Interface seamlessly with mechanical engineering teams to bridge simulation data with physical prototypes, delivering robust technical solutions to international clients and suppliers. 🔹 Mechanical Structural Design: Apply fundamental mechanical principles (solid mechanics, kinematics, and structural dynamics) to design high-performance server chassis and provide robust structural solutions.Mass Production Induction (NPI): Own the New Product Introduction phase, leading sample validation, prototype testing, and root-cause analysis to resolve engineering defects during trial production.DFM Tooling Review: Conduct deep Design for Manufacturing (DFM) reviews with factory production teams to assess mass-production feasibility; possessing a strong background in stamping mold design and tooling engineering is highly preferred. 🛠 Technologies Core Concepts Used Liquid cooling Track: CDU Manifold Architecture, Fluid Routing Layouts, Pump Configuration, CNC/Stamping/Welding Processes.Thermal Track: CFD Simulation (Fluent, Icepak, FloTHERM, CFX), Thermal Resistance Analysis, Material Thermal Characterization.Mechanical Track: Structural Enclosure Design, Mechanics of Materials, NPI Lifecycle, Prototype Validation, Stamping Mold Tooling (DFM).

Role summary: Customer-facing Azure Infrastructure CSA focused on designing, deploying, and optimizing Azure foundations including landing zones, subscriptions, networking, identity integration, governance, and virtual machine workloads. Key responsibilities: Design Azure landing zones aligned to Microsoft Cloud Adoption Framework and Well-Architected Framework. Advise customers on subscription strategy, management groups, RBAC, policies, tagging, and governance. Architect and configure Azure Virtual Machines, availability sets, VM scale sets, disks, backup, and recovery. Support Azure networking design including VNets, subnets, NSGs, route tables, private endpoints, VPN, and ExpressRoute. Help customers migrate and modernize workloads from on-premises to Azure.Drive technical workshops, architecture reviews, and deployment planning sessions.Act as a trusted technical advisor to strategic enterprise customers.Drive adoption, consumption, health, and successful implementation of Microsoft cloud services.Identify technical blockers and coordinate resolution with support, engineering, partners, and account teams.Deliver architecture workshops, technical guidance, readiness sessions, and best-practice reviewsAlign customer technical plans with business outcomes and measurable success criteriaDocument customer architecture, risks, dependencies, recommendations, and next steps.

Google welcomes people with disabilities.Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 1 year of experience with verification methodologies and languages such as UVM or SystemVerilog. Experience with object oriented programming. Preferred qualifications: Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture, or a related field. Experience creating and using verification components and environments in a standard verification methodology such as UVM. Experience with image processing or other multimedia IPs such as Display or Video Codec. Experience with performance verification of ASICs and ASIC components and experience with ASIC standard interfaces and memory system architecture. Experience with verification techniques, System Verilog Assertions (SVA), and assertion-based verification. Experience with low-power DV, and support of SOC DV or gate-level simulation(GLS). About the jobBe part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.Responsibilities Plan the verification of complex multimedia digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios. Create and enhance constrained-random verification environments using System Verilog and UVM. Identify and write all types of coverage measures for stimulus and corner-cases. Debug tests with design engineers to deliver functionally correct design blocks. Close coverage measures to identify verification holes and to show progress towards tape-out. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.