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Google welcomes people with disabilities.Note: By applying to this position you will have an opportunity to share your preferred working location from the following: New Taipei, Banqiao District, New Taipei City, Taiwan; Zhubei, Zhubei City, Hsinchu County, Taiwan.Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering or Computer Science, with a focus on computer architecture, or equivalent practical experience. 4 years of experience in microprocessor architecture, microarchitecture, performance, or advanced CPU design. Experience in CPU architecture, performance modeling, analysis, correlation, and workload characterization. Experience with C/C++ and scripting languages (e.g., Python). Preferred qualifications: Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science, with an emphasis on computer architecture or machine learning. Experience in CPU/ML microarchitecture exploration, performance model development, performance analysis, performance correlation, or workload characterization. Knowledge of microprocessor instruction set architecture (e.g., ARM, RISC-V, x86). Familiarity with system software components, such as Linux, drivers, and runtime. About the jobAs a CPU Performance Architect, you will be the key contributor to improve processor instruction set architecture, to develop innovative microarchitecture features, and deliver Google’s advanced SoC products. You will collaborate cross-functionally with android applications and AI teams to conduct applications and benchmark performance analysis and to project their performance at various design phases. You will be guided by architects and work with engineers in Power, Thermal, Security, and Physical Design teams to determine the CPU subsystem configuration and features.Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.Responsibilities Develop and modify a performance model for performance analysis and microarchitecture study. Evaluate Advanced RISC Machine (ARM’s) architecture features from both architecture and performance angles. Define and write CPU subsystem architecture specifications. Collaborate with Register-Transfer Level (RTL), design verification, and physical design teams to develop a high-performance and efficient CPU implementation. Manage performance correlation between the performance model and RTL implementation, including micro-benchmark development and pre-silicon and post-silicon performance bug triage. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.

Google welcomes people with disabilities.Note: By applying to this position you will have an opportunity to share your preferred working location from the following: New Taipei, Banqiao District, New Taipei City, Taiwan; Zhubei, Zhubei City, Hsinchu County, Taiwan.Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 1 year of experience with verification methodologies and languages such as UVM or SystemVerilog. Experience with object oriented programming. Preferred qualifications: Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture, or a related field. Experience creating and using verification components and environments in a standard verification methodology such as UVM. Experience with image processing or other multimedia IPs such as Display or Video Codec. Experience with performance verification of ASICs and ASIC components and experience with ASIC standard interfaces and memory system architecture. Experience with verification techniques, System Verilog Assertions (SVA), and assertion-based verification. Experience with low-power DV, and support of SOC DV or gate-level simulation(GLS). About the jobBe part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.Responsibilities Plan the verification of complex multimedia digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios. Create and enhance constrained-random verification environments using System Verilog and UVM. Identify and write all types of coverage measures for stimulus and corner-cases. Debug tests with design engineers to deliver functionally correct design blocks. Close coverage measures to identify verification holes and to show progress towards tape-out. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.

Google welcomes people with disabilities.Note: By applying to this position you will have an opportunity to share your preferred working location from the following: New Taipei, Banqiao District, New Taipei City, Taiwan; Zhubei, Zhubei City, Hsinchu County, Taiwan.Minimum qualifications: Bachelor's degree in Electrical Engineering, Semiconductor Processing, or a related field, or equivalent practical experience. 4 years of experience in VLSI technologies, product and test engineering, and semiconductor processing. Experience in Integrated Circuit (IC) qualification, data review, production release, system level testing, test time reduction and yield improvement. Experience with Yield and Fail Pareto Analysis using JMP, Exensio, Datapower or O+. Preferred qualifications: 8 years of experience in VLSI technologies, Product and Test Engineering, Semiconductor processing. Experience in Test and Design for test (DFT) techniques, and with structural tests such as Scan/ATPG, JTAG, Memory BIST and sensors such as PVT/temperature/current/droop sensors, etc. Experience with test chip design, development and testing methodologies. Experience with advanced packaging such as 2.5d, 3d, InFo. Familiar with Automatic Test Equipment (ATE) test platforms such as Advantest 93K , Teradyne UltraFlex SOC test system. Knowledge of reliability stress, device qualification and associated processes. About the jobBe part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. In this role, you will develop and deploy productization solutions while partnering with cross-functional teams to enable manufacturing at fabrication plants and assembly and test sites. You will help integrate System on a chip (SoC) technologies into devices and facilitate Automated Test Equipment (ATE)/System Level Testing (SLT) manufacturing testing of SoC to validate performance and screen out failing devices. You will work with cross-functional teams to ensure optimal test coverage and cost efficiencies in production to ensure quality SoCs. You will work with multiple groups to develop digital and mixed signal tests, automation methodologies, develop/support internal tools for data analysis, yield analysis, silicon debug, reliability qualification, manufacturing ramp and customer returns. You will also be a partner on releasing production test solutions into mass production.Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.Responsibilities Perform SoC Artificial Intelligence (AI)-centric product specifications and Design for testing (DFT) architecture reviews and generate New Product Introduction (NPI) characterization, test, or manufacturing plans. Support test hardware design (e.g., probe card, Load board) requirements, ATE/SLT test program review, and work for test coverage. Perform Die/Package level bring-ups, troubleshoot different failure modes and help resolve issues by collaborating with cross-functional teams. Support Outsourced Assembly and Test (OSAT) bring-up, ATE/SLT manufacturing test programs releases, and meet test cost goals. Manage NPI and Manufacturing Return Materials/Merchandise Authorizations (RMAs) to achieve TurnAround Times (TATs) and provide lot dispositions. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.