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Google welcomes people with disabilities.Minimum qualifications: Bachelor's degree or equivalent practical experience. 2 years of experience with software development in one or more programming languages (e.g., Python, C++, Rust, Go). Preferred qualifications: Experience with automated testing frameworks. Experience with operating systems, distributed systems, compilers, Low Level Virtual Machines (LLVM). About the jobGoogle's software engineers develop the next-generation technologies that change how billions of users connect, explore, and interact with information and one another. Our products need to handle information at massive scale, and extend well beyond web search. We're looking for engineers who bring fresh ideas from all areas, including information retrieval, distributed computing, large-scale system design, networking and data storage, security, artificial intelligence, natural language processing, UI design and mobile; the list goes on and is growing every day. As a software engineer, you will work on a specific project critical to Google’s needs with opportunities to switch teams and projects as you and our fast-paced business grow and evolve. We need our engineers to be versatile, display leadership qualities and be enthusiastic to take on new problems across the full-stack as we continue to push technology forward. In this role, you will design, develop, and maintain software testing frameworks and integrations, involving coding in Rust, Python, C++, and Go. You will work in greenfield projects as well as new features in existing systems. You will work across the entire stack, from the kernel to userspace to beyond the device, to develop testing features. You will propose and implement kernel-level features as needed, You will implement data processing pipelines to analyze test results at scale. You will develop and improve tools for test execution, output processing, and result collection. You will investigate and implement AI/ML models to assist with test generation, optimization, and automated bug triaging. You will contribute to shared team responsibilities such as roller/build rotation, debug and triage customer issues.Fuchsia is a modern, open source operating system that is simple, secure, updatable, and performant. It’s a general purpose OS, designed to power an ecosystem of hardware and software, and provides core operating system functions like system resource management, a driver framework, and software abstractions.Responsibilities Design and implement new testing features in C++ and Rust. Implement new end-to-end testing harnesses in Python for device testing. Collaborate across the organization to gather feedback and identify gaps in our testing frameworks. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.Role Overview Astera Labs is at the epicenter of the AI infrastructure revolution, building the intelligent connectivity solutions that power the world's most advanced data centers. As AI workloads scale to unprecedented levels, the demand for purpose-built, rack-scale platforms that seamlessly integrate high-speed connectivity, firmware intelligence, and composable architectures has never been greater — and neither has the opportunity to shape what comes next. The AI Platform Solutions Group is seeking a Distinguished Engineer to serve as the technical visionary for next-generation AI infrastructure, spanning server firmware, high-speed connectivity, and rack-scale system design. In this role, you will define the end-to-end architecture for AI platforms that integrate cutting-edge technologies such as PCIe Gen5/6, composable rack architectures, and advanced interconnect solutions including Astera Labs' portfolio of retimers, switches, and fabric controllers. This is a high-impact, high-visibility role where you will drive innovation across silicon integration, platform firmware, system performance, and rack-level orchestration — directly enabling hyperscale AI training and inference workloads. You will partner with silicon vendors, hyperscalers, OEMs, and ODMs while influencing industry standards and mentoring the next generation of platform architects. If you want to architect the future of AI infrastructure at a company that is defining the connectivity backbone of modern data centers, this is your role. Key Responsibilities AI Platform Rack-Scale Architecture Define the end-to-end architecture for AI platforms, from node-level design to rack-scale composable systems Drive adoption of PCIe-based fabrics for disaggregated compute, memory, and accelerator scalability Architect solutions for GPU/accelerator-dense systems optimized for AI training and inference workloads Lead integration of connectivity solutions — retimers, switches, and fabric controllers — aligned with Astera Labs' product ecosystem Firmware Platform Leadership Drive innovation in server BIOS/UEFI architecture, OpenBMC-based platform management, Redfish APIs for scalable infrastructure control, and lifecycle provisioning frameworks Lead system bring-up and ensure seamless firmware-hardware-software integration across complex AI platforms Define the technical vision and multi-year firmware roadmap for AI infrastructure platforms Performance Optimization Own end-to-end AI platform performance strategy including PCIe topology optimization, bandwidth scaling, latency reduction, and CPU performance tuning for AI orchestration workloads Drive memory performance optimization across DDR, NUMA, and emerging memory expansion technologies Lead performance tuning for multi-accelerator systems (GPU/ASIC/FPGA), high-throughput data pipelines, and distributed AI workloads Ecosystem Industry Leadership Collaborate with silicon vendors (CPU, GPU, AI accelerators), connectivity ecosystem partners, OEMs, ODMs, and hyperscalers Influence industry standards across OpenBMC, Redfish, OCP, and related consortia Mentor senior engineers and grow deep technical bench strength across the organization Represent Astera Labs as a recognized thought leader in AI infrastructure and platform innovation Basic Qualifications Bachelor's degree in Computer Science, Electrical Engineering, Computer Engineering, or a related field 15+ years of experience in system architecture, server firmware, or platform engineering Deep expertise in server BIOS/UEFI, OpenBMC and BMC firmware stacks, and Redfish or datacenter management frameworks Strong knowledge of PCIe architecture and performance optimization (Gen4/5/6) Experience with CPU, memory, and system-level performance tuning for high-performance computing or AI platforms Strong programming experience in C/C++ and low-level system software Proven track record of leading cross-functional, large-scale architecture initiatives Preferred Qualifications Master's degree or PhD in Computer Science, Electrical Engineering, or a related field Experience with rack-scale composable infrastructure and disaggregated architectures Background in AI training clusters, accelerator-based systems, or hyperscale datacenter design Expertise in high-speed interconnect solutions such as retimers, switches, and fabric ICs Experience with platform lifecycle management systems and fleet-level automation Contributions to industry standards bodies or open-source firmware ecosystems Demonstrated ability to define multi-year technical roadmaps and influence executive strategy We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com. Role Overview Astera Labs is at the epicenter of the AI infrastructure revolution, building the intelligent connectivity solutions that power the world's most advanced data centers. As AI workloads scale to unprecedented levels, the demand for purpose-built, rack-scale platforms that seamlessly integrate high-speed connectivity, firmware intelligence, and composable architectures has never been greater — and neither has the opportunity to shape what comes next. The AI Platform Solutions Group is seeking a Distinguished Engineer to serve as the technical visionary for next-generation AI infrastructure, spanning server firmware, high-speed connectivity, and rack-scale system design. In this role, you will define the end-to-end architecture for AI platforms that integrate cutting-edge technologies such as PCIe Gen5/6, UAlink, CXL, composable rack architectures, and advanced interconnect solutions including Astera Labs' portfolio of retimers, switches, and fabric controllers. This is a high-impact, high-visibility role where you will drive innovation across silicon integration, platform firmware, system performance, and rack-level orchestration — directly enabling hyperscale AI training and inference workloads. You will partner with silicon vendors, hyperscalers, OEMs, and ODMs while influencing industry standards and mentoring the next generation of platform architects. If you want to architect the future of AI infrastructure at a company that is defining the connectivity backbone of modern data centers, this is your role. Key Responsibilities AI Platform Rack-Scale Architecture Define the end-to-end architecture for AI platforms, from node-level design to rack-scale composable systems Drive adoption of PCIe/UAlink-based fabrics for disaggregated compute, memory, and accelerator scalability Architect solutions for GPU/accelerator-dense systems optimized for AI training and inference workloads Lead integration of connectivity solutions — retimers, switches, and fabric controllers — aligned with Astera Labs' product ecosystem System Architecture Platform Leadership Lead system architecture and design for high-performance compute platforms optimized for AI and accelerator-driven workloads Design and integrate PCIe-based subsystems including GPU, accelerator, and high-speed I/O components leveraging PCIe Gen5/6 technologies Define and implement GPU-enabled server platforms for AI training, inference, and HPC workloads Architect and optimize high-speed Ethernet networking interfaces (25G/100G/400G+) within platform designs Define the technical vision and multi-year product roadmap for AI infrastructure platforms Platform Management Cross-Functional Leadership Define and implement platform management solutions including BMC integration, telemetry, health monitoring, and system-level diagnostics Collaborate with cross-functional teams spanning hardware, firmware, BIOS, and OS to ensure seamless platform integration Partner with silicon vendors, OEMs, and hyperscalers on custom platform development aligned with Astera Labs' connectivity ecosystem Drive performance optimization across PCIe topology, accelerator interconnects, and memory subsystems Own end-to-end AI platform performance strategy including PCIe topology optimization, bandwidth scaling, latency reduction, and CPU performance tuning for AI orchestration workloads Lead performance tuning for multi-accelerator systems (GPU/ASIC/FPGA), high-throughput data pipelines, and distributed AI workloads Ecosystem Industry Leadership Collaborate with silicon vendors (CPU, GPU, AI accelerators), connectivity ecosystem partners, OEMs, ODMs, and hyperscalers Influence industry standards across OpenBMC, Redfish, OCP, and related consortia Mentor senior engineers and grow deep technical bench strength across the organization Represent Astera Labs as a recognized thought leader in AI infrastructure and platform innovation Basic Qualifications Bachelor's degree in Computer Science, Electrical Engineering, Computer Engineering, or a related field 15+ years of experience in system architecture, server firmware, or platform engineering Deep expertise in server BIOS/UEFI, OpenBMC and BMC firmware stacks, and Redfish or datacenter management frameworks Strong knowledge of PCIe architecture and performance optimization (Gen4/5/6) Experience with CPU, memory, and system-level performance tuning for high-performance computing or AI platforms Strong programming experience in C/C++ and low-level system software Proven track record of leading cross-functional, large-scale architecture initiatives Preferred Qualifications Master's degree or PhD in Computer Science, Electrical Engineering, or a related field Experience with rack-scale composable infrastructure and disaggregated architectures Background in AI training clusters, accelerator-based systems, or hyperscale datacenter design Expertise in high-speed interconnect solutions such as retimers, switches, and fabric ICs Experience with platform lifecycle management systems and fleet-level automation Contributions to industry standards bodies or open-source firmware ecosystems Demonstrated ability to define multi-year technical roadmaps and influence executive strategy We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Minimum qualifications: PhD degree in Electronics and Communication Engineering, Electrical Engineering, Computer Engineering or related technical field, or equivalent practical experience. Experience with accelerator architectures and data center workloads. Experience in programming languages (e.g., C++, Python, Verilog), Synopsys, Cadence tools. Preferred qualifications: 2 years of experience post PhD. Experience with performance modeling tools. Knowledge of arithmetic units, bus architectures, accelerators, or memory hierarchies. Knowledge of high performance and low power design techniques. About the jobIn this role, you will shape the future of AI/ML hardware acceleration as a Silicon Architect/Design Engineer and drive cutting-edge TPU (Tensor Processing Unit) technology that fuels Google's most demanding AI/ML applications. You will collaborate with hardware and software architects and designers to architect, model, analyze, define and design next-generation TPUs. You will have dynamic, multi-faceted responsibilities in areas such as product definition, design, and implementation, collaborating with the Engineering teams to drive the optimal balance between performance, power, features, schedule, and cost.The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide. We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.Responsibilities Revolutionize Machine Learning (ML) workload characterization and benchmarking, and propose capabilities and optimizations for next-generation TPUs. Develop architecture specifications that meet current and future computing requirements for AI/ML roadmap. Develop architectural and microarchitectural power/performance models, microarchitecture and RTL designs and evaluate quantitative and qualitative performance and power analysis. Partner with hardware design, software, compiler, Machine Learning (ML) model and research teams for effective hardware/software codesign, creating high performance hardware/software interfaces. Develop and adopt advanced AI/ML capabilities, drive accelerated and efficient design verification strategies and implementations. Use AI techniques for faster and optimal Physical Design Convergence -Timing, floor planning, power grid and clock tree design etc. Investigate, validate, and optimize DFT, post-silicon test, and debug strategies, contributing to the advancement of silicon bring-up and qualification processes. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.

CS Infrastructure Support – Infra Support Intern ASIntroduction:CS IAS (CS Infrastructure, Architecture and Security) covers worldwide functional support for all off-scanner Applications, Infrastructure and Security. We ensure that CS field engineer operation and process excellence.Job Mission:Your main responsibilities are to ensure that support operations are picked up and handled to the satisfaction of our end-users and within given KPI’s, to update the knowledge bases, participate in user acceptance tests and to administrate calls in our call management system. Working hours need to fit the time window for which the AS team is responsible. Main responsibility is to coordinate CS and end customers project discussion of infrastructure topics.Job Description:Ticket management: CS IAS incident handlingCoordinate BRES account applicationCS IAS work instruction and document maintenanceEducation:Bachelor/ MasterPersonal Skills:The ability to speak and write in EnglishKnowledge in MS OfficeAble to build strong networks with stakeholdersCultural awareness of applicable customersOffice locationHsinchu, TaiwanThis position requires access to controlled technology, as defined in the United States Export Administration Regulations (15 C.F.R. § 730, et seq.). Qualified candidates must be legally authorized to access such controlled technology prior to beginning work. Business demands may require ASML to proceed with candidates who are immediately eligible to access controlled technology.Inclusion and diversityASML is an Equal Opportunity Employer that values and respects the importance of a diverse and inclusive workforce. It is the policy of the company to recruit, hire, train and promote persons in all job titles without regard to race, color, religion, sex, age, national origin, veteran status, disability, sexual orientation, or gender identity. We recognize that inclusion and diversity is a driving force in the success of our company.Need to know more about applying for a job at ASML? Read our frequently asked questions.

Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 10 years of experience in ASIC development with Verilog/SystemVerilog, Vhsic Hardware Description Language (VHDL). Experience in micro-architecture and design IPs and subsystems. Experience in ASIC design verification, synthesis, timing/power analysis, and Design for Testing (DFT). Preferred qualifications: Experience with scripting languages (e.g., Python or Perl). Experience in SoC designs and integration flows. Knowledge of bus architectures, fabrics/NoC, processor design, accelerators, or memory hierarchies.. Knowledge of high-performance and low-power design techniques. About the jobIn this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. In this role, you will be part of a team developing Application-Specific Integrated Circuits (ASIC) used to accelerate and improve traffic efficiency in data centers. You will collaborate with members of architecture, verification, power and performance, physical design, etc. to specify and deliver high quality designs for next generation data center accelerators. You will solve technical problems with innovative micro-architecture and practical logic solutions, and evaluate design options with complexity, performance, power and area in mind.The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide. We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.Responsibilities Drive development of complex IPs and subsystems along with a team of engineers. Own micro-architecture and implementation of IPs and subsystems. Work with architecture, firmware and software teams to drive feature closure and develop micro-architecture specifications. Drive design methodology, libraries, debug, code review in coordination with other IPs Design Verification (DV) teams and physical design teams. Identify and drive power, performance and area improvements for the domains owned. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.

｜核心職責 (Technical Execution)【全渠道通訊架構與高併發治理 (Omnichannel Messaging Architecture)】。主導 Meta (WhatsApp, Facebook Messenger, Instagram) 與 LINE 等第三方通訊平台的底層串接架構設計。。建構具備高吞吐量、高可用性且支援非同步處理的訊息中樞 (Message Hub)，確保在海量 Webhook 瞬間併發下，系統仍能穩健運行且達到「訊息零丟失 (Zero Message Loss)」。【核心模組演進與重構】。主導系統中複雜模組的 refactoring 實作。具備處理大規模程式碼異動的能力，能在不影響業務運行下，完成 Scope 極大的系統改版與邏輯優化。【AI 協作開發實踐】。將 AI 輔助工具（如 GitHub Copilot, Cursor）深度整合進日常工作流。利用 AI 進行高效率的 code review、基於 Testcontainers 與 LocalStack 的整合測試生成及複雜邏輯的重構建議，示範如何以 AI 賦能達成極致的產出品質。【務實的性能治理與調優】。根據業務場景進行合理的 performance tuning。需具備判斷技術投入產出比（ROI）的能力，確保核心通訊場景具備極限負載下的穩定性，同時在一般功能中保持開發效率與成本平衡。【安全性與弱點修復】。主導處理經由 Inspector 掃描發現的系統弱點（Vulnerabilities）。需具備評估風險優先級與實作修復方案的能力，在維持系統高可用性的前提下，優化軟體依賴與代碼安全性。。針對第三方平台的 Token 授權管理、API Secret 存放與傳輸安全進行嚴格把關。【高品質代碼實作】。負責核心 Feature 的開發與關鍵 API 設計，建立具備高度可讀性、可維護性且效能優異的代碼範本。【技術瓶頸攻堅】。針對系統運行中的各類 Hard Problem（如 deadlock、race condition、OOM 等）進行深度追蹤並完成修復。

Responsibilities: High-Quality Code Delivery:Write clean, concise, easy-to-read, and well-documented code to ensure the system is maintainable and scalable.Ensure code is designed for scalability and performance, anticipating future growth and changes.System Analysis and Refactoring:Analyze existing system code, refactor and optimize it, and write tests to ensure system stability and performance.Propose and implement refactoring strategies that improve maintainability, performance, and readability of the system.Code Review and Team Collaboration:Actively participate in code reviews, provide constructive feedback on pull requests, and help the team continuously improve.Share best practices to elevate the overall code quality within the team.Requirements Understanding and System Design:Collaborate closely with product and business teams to thoroughly understand requirements and contribute to system architecture design, implementing effective technical solutions.Contribute to the design and architecture of scalable systems, ensuring alignment with overall product strategy.Identify potential technical challenges early and propose effective solutions.International Team Collaboration:Work with global engineering teams, engaging in technical communication and collaboration to drive product innovation.

產業類別： 電腦/週邊設備製造 職責要求 一、團隊與組織管理 1.領導企業營運開發團隊（SAP開發 / Integration / AI應用） 2.建立系統開發與交付機制（SDLC / Agile / DevOps） 3.負責團隊人力規劃、技術培育與績效管理（約 3–5 人） 4.與營運管理課協同，確保開發與維運順利銜接 二、系統與架構治理 1.主導企業系統架構設計（SAP S/4HANA + 異質系統整合） 2.規劃系統整合架構（API / Interface / Middleware） 3.設計資料架構與資料流（Data Model / Data Flow） 4.建立開發規範與技術標準（Coding / Transport / Version Control） 三、需求與系統設計 1.主導業務需求訪談與系統解決方案設計 2.撰寫與審查功能規格與技術規格（FS / TS） 3.設計跨模組流程（FI/CO/MM/SD/PP/QM/WM）整合 4.建立可重用開發元件與標準化方案 四、專案與跨部門協作 1.主導系統開發與整合專案（Enhancement / Integration / Automation） 2.控管專案時程、品質與風險 3.跨部門溝通（IT / 財務 / 業務 / 製造） 4.協同 SAP 顧問與外部開發團隊推動專案 五、AI 與自動化推動（與營運管理課共同推進） 1.評估並導入 AI 應用（AI Agent / RPA / Automation） 2.設計 AI 與 ERP / Workflow / BI 系統整合模式 3.推動流程自動化與智慧化應用落地 4.支援企業 AI 技術導入與架構設計 六、治理與合規 1.確保系統開發符合內控與資安要求（ITGC / Audit） 2.建立開發流程之控制機制（Change / Transport / Authorization） 3.配合內外部稽核與文件準備

Established in 1987 and headquartered in Taiwan, TSMC pioneered the pure-play foundry business model with an exclusive focus on manufacturing its customers’ products. As of 2024, TSMC serves more than 500 customers and manufactures over 11,000 products for high-performance computing, smartphones, the Internet of Things (IoT), automotive, and digital consumer electronics. It is the world’s largest provider of logic ICs, with an annual capacity of 16 million 12-inch equivalent wafers. TSMC operates fabs in Taiwan as well as manufacturing subsidiaries in Washington State, Japan and China, and the Company began construction on a specialty technology fab in Dresden, Germany, in 2024. In Arizona, TSMC is building three fabs, with the first starting 4nm production in 2025, the second by 2028, and the third by the end of the decade. Are you a creative IT professional with strong technical aptitude who embraces changes and is passionate about data and information? We invite you to join our highly innovative data engineering team which is constantly designing, developing, and delivering high quality solutions for our customers. As a data engineer, you will have opportunities to work in a dynamic and fast-paced environment to collaborate with business functions to design solutions. You will translate business requirements into technical needs, connect and automate data pipelines, and deliver data architecture and data governance solutions. Responsibility: Perform IT system architecture design, new technology research, and provide recommendation.Design and implement optimal data pipeline architecture (considered high data volume, data governance, etc.).Work with PRODUCT/BIZ teams to assist with new data platform re-engineering or data-related technical issues.DataOps high availability NoSQL DB (e.g.: Cassandra, S3/MinIO, MariaDB, etc.) on K8s environment.