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CS Infrastructure Support – Infra Support Intern ASIntroduction:CS IAS (CS Infrastructure, Architecture and Security) covers worldwide functional support for all off-scanner Applications, Infrastructure and Security. We ensure that CS field engineer operation and process excellence.Job Mission:Your main responsibilities are to ensure that support operations are picked up and handled to the satisfaction of our end-users and within given KPI’s, to update the knowledge bases, participate in user acceptance tests and to administrate calls in our call management system. Working hours need to fit the time window for which the AS team is responsible. Main responsibility is to coordinate CS and end customers project discussion of infrastructure topics.Job Description:Ticket management: CS IAS incident handlingCoordinate BRES account applicationCS IAS work instruction and document maintenanceEducation:Bachelor/ MasterPersonal Skills:The ability to speak and write in EnglishKnowledge in MS OfficeAble to build strong networks with stakeholdersCultural awareness of applicable customersOffice locationHsinchu, TaiwanThis position requires access to controlled technology, as defined in the United States Export Administration Regulations (15 C.F.R. § 730, et seq.). Qualified candidates must be legally authorized to access such controlled technology prior to beginning work. Business demands may require ASML to proceed with candidates who are immediately eligible to access controlled technology.Inclusion and diversityASML is an Equal Opportunity Employer that values and respects the importance of a diverse and inclusive workforce. It is the policy of the company to recruit, hire, train and promote persons in all job titles without regard to race, color, religion, sex, age, national origin, veteran status, disability, sexual orientation, or gender identity. We recognize that inclusion and diversity is a driving force in the success of our company.Need to know more about applying for a job at ASML? Read our frequently asked questions.

Established in 1987 and headquartered in Taiwan, TSMC pioneered the pure-play foundry business model with an exclusive focus on manufacturing its customers’ products. As of 2024, TSMC serves more than 500 customers and manufactures over 11,000 products for high-performance computing, smartphones, the Internet of Things (IoT), automotive, and digital consumer electronics. It is the world’s largest provider of logic ICs, with an annual capacity of 16 million 12-inch equivalent wafers. TSMC operates fabs in Taiwan as well as manufacturing subsidiaries in Washington State, Japan and China, and the Company began construction on a specialty technology fab in Dresden, Germany, in 2024. In Arizona, TSMC is building three fabs, with the first starting 4nm production in 2025, the second by 2028, and the third by the end of the decade. Are you a creative IT professional with strong technical aptitude who embraces changes and is passionate about data and information? We invite you to join our highly innovative data engineering team which is constantly designing, developing, and delivering high quality solutions for our customers. As a data engineer, you will have opportunities to work in a dynamic and fast-paced environment to collaborate with business functions to design solutions. You will translate business requirements into technical needs, connect and automate data pipelines, and deliver data architecture and data governance solutions. Responsibility: Perform IT system architecture design, new technology research, and provide recommendation.Design and implement optimal data pipeline architecture (considered high data volume, data governance, etc.).Work with PRODUCT/BIZ teams to assist with new data platform re-engineering or data-related technical issues.DataOps high availability NoSQL DB (e.g.: Cassandra, S3/MinIO, MariaDB, etc.) on K8s environment.

【工作內容】 - 雲端設定與維護 (資料保存/備份/備援/防禦)- 系統與程式更新、部署機制規劃與執行- 標配MAC電腦(本職務工作地點位於桃園) 【上班時間】 早上 9 點至下午 6 點並且有 30 分鐘彈性上下班 【公司福利】 勞健保、三節、尾牙、生日禮金。 我們公司設有咖啡休息區，免費零食、飲料、餐點，飲品，備有微波爐。 不定時員工聚餐與每年都有員工旅遊。

【關於這個職位：成為美妝界的數位大腦】 在資訊爆炸的時代，我們堅信情報真實重要性及拒絕任何不真實虛假。作為「產品營運」，你將不只是資料的管理者，更是平台信任價值的守護者。你將直接參與全台灣最權威化妝品資料庫的建構，透過大數據驅動的決策與流程優化，確保每一筆產品與成分資料、每一份心得都能成為消費者決策的關鍵。 這是一個結合「美妝專業」與「科技思維」的關鍵角色，你將在這裡建立業界標竿，定義何謂真正具備信賴性的美妝內容。 @cosme Taiwan(前身UrCosme)在台營運超過20年，是國內消費者找尋化妝品使用心得及排行榜綜合資訊的主流網站，隸屬於日本上市公司集團istyle.Inc.(@cosme)。我們堅信「真實情報」是帶給使用者幸福的關鍵，而美妝資料庫的真實、正確與公信力則是我們所有情報服務的最重要基石。 我們正在尋找一位熱愛美妝、深度認同此一情報真實平台重要性，並不斷提昇「資料真實及價值」以及守護「品質管理」的夥伴。您將身處平台核心價值創造的戰略制高點，透過對每一個產品、每一篇口碑、屬性、標籤、以及群眾智慧創出的過程有深度參與和品管職責。 透過這份工作，您將成為： 平台內最懂美妝最新話題的人： 每天接觸最新最完整的產品資訊，比任何部門都更快掌握市場動向與消費者興趣的發酵點。美妝知識學習的最佳途徑： 讓對美妝的熱情，能夠轉化為專業且高價值資訊情報的機會，為數百萬網友的消費決策奠定最可靠的基礎。透過DB價值提昇專案，學習情報媒合及服務創建的最重要基盤。 【核心職掌】 此職位隸屬於平台策略營運部，您的主要任務是確保@cosme資料庫的真實與公信力，確保平台上資訊可信賴性，共同推動平台持續成長，核心內容包含（依狀況進行工作分配）: 真實信賴內容管理 (Integrity Trust Management)協助平台能提供真實具有公信力的消費者使用心得作為購物決策時的重要指標，即時提供並管理市場上最完整詳盡且正確的美妝資訊。確保透過真實口碑累積的數據結果具備最高的公信力與可信度，並創造群眾智慧的價值。- 包含「正確產品資訊建構」，「UGC真實心得審核機制」，運用數據分析技術識別異常行為與虛假評論。- 定義內容品質的關鍵指標 (KPI)，確保平台內容的專業性與客觀性。美妝資料庫入庫分類、架構與流程優化 (System Architecture Optimization)- 負責化妝品資料庫的生命週期管理，優化資料入庫、分類與更新的標準化作業流程 (SOP)。 - 協同開發團隊，透過科技手段提升資料庫的檢索效率與使用者體驗。DB價值提昇專案：參與DB價值提昇專案，進一步透過數據整合及用途設計，進一步習得群眾智慧平台的價值轉換設計過程。大數據洞察與趨勢分析 (Data-Driven Insights)- 從海量使用心得中提煉使用者情感 (Sentiment Analysis)，產出具有市場引領性的消費趨勢洞察，並應用在社群平台機制與內容規劃上。- 監控市場新品動向，確保資料庫的時效性領先於業界。跨團隊協作與產品進化 (Cross-functional Collaboration)作為用戶與工程師之間的橋樑，蒐集並轉化內部營運需求，推動產品功能迭代。推動平台使用者育成：透過理解美妝社群動向，後續可進一步學習如何利用自動化行銷，設計使用者與平台互動之所有細節，搭配網站功能設計，提高使用者之活躍度。網站營運：利用UI優化、網站功能設計，優化平台輔助使用者購物決策資訊流程，達到有效媒合。期待您能從營運經驗中創發許多優化思惟，對網路生態有較高敏感度，擁有適應環境的柔軟性及良好的溝通能力，相信資訊帶給人的幸福價值。

About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact As a Digital IC Design Staff Engineer with Marvell, you’ll be a member of the Central Engineering business group. If you picture Marvell as a wheel, Central Engineering is the center hub providing IP to be used by all the other spokes on that wheel, including Automotive, Storage, Security, and Networking. You’ll be part of a digital team of about eight people making a big impact on this organization, working on ultra-dense and performance ASIC. This team hires some of the biggest problem solvers in Silicon and has a huge impact on the work done at Marvell. The customers served by this team are often other chip companies and big tech companies, familiar names to all candidates. What You Can Expect Job Responsibilities: Become a member of a world‐class design team. You will have an opportunity to design the latest high‐performance AI silicon and other critical high speed interface (PCIe, CXL, UA link) IP designs for Marvell’s core products. All team members participate in circuit architecture, RTL implementation, design review, layout, and silicon DV and validation in the following areas: Develop next generation silicon IP utilizing advanced digital technologies.Perform architecture discussion and design. Review architecture and define test plan, including RTL coding and debug.Support firmware team to develop production firmware code.Support validation team and FAE to trouble shoot for our silicon to find root cause and provide fix.Review design documentation, description and information to internal and external customers. What We're Looking For Requirements:Minimum BSEE plus 2-5 years of design experience in one of the following areas below: Analyze and improve design architecture and block-level IP microarchitectureImplement RTL design with Hardware Description Language (Verilog, SystemVerilog)On-Chip bus protocols knowledge: AXI, AHB, APBPerforming Lint, CDC check, Timing closure, coverage closure analysisBasic understanding of UVM based test benchBasic understanding of scripting/programming language with PERL/Python, TCL and C/C++ Preferred: Knowledge in PCIe, NVMe, CXL, UAlink and implementations is a plus Additional Compensation and Benefit Elements Competitive salary, plus 13th-month salary and performance-based bonusRSUs (Restricted Stock Units) for new joiners and on-going annuallyPremium health accident insurance for you and your family (spouse and children)Annual medical check-up at a designated hospital arranged by MarvellGenerous paid leave policies: 15 annual leave days, 3 Recharge periods per year (company-wide off-work from Friday to Monday), 5 paid sick leave days, 3 days of volunteer time-off and 11 public holidaysExciting Employee Events: Participate in fun activities throughout the year such as team birthdays, sports tournaments, company trips, mid-autumn, appreciation week, charity, health seminars, year-end party, and more. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. Interview Integrity To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews. These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process. This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.

微程式（Microprogram，股票代號7721），為具備跨產業技術整合能力的產業資通訊共通設計中心​（ICT Design House​）。我們從產業需求設計、服務設計、解決方案規劃到軟硬體設計與開發，提供垂直式整合服務，透過智慧科技，協助交通、金融、零售、半導體製造、自行車等產業夥伴進行創新升級。目前聚焦於「電子支付、智慧設備、半導體感測控制」三大核心發展領域。　 　 ▍工作內容 協助使用 Flutter 開發 Android / iOS 平台的應用程式，並參與應用的維護與性能優化工作。與後端團隊合作，進行應用程式與後端系統的 API 介接，確保資料流的順暢傳遞。與產品設計師合作，參與提升應用程式的 UI/UX 設計，學習如何根據設計需求進行介面的優化。協助進行應用的效能調整，學習如何提升應用程式的運行速度和穩定性。使用AI輔助工具(mcp、skills、rules) 　 ▍必備條件 Flutter 核心技術： 精通 Dart 語言（含 Null Safety、Asynchronous programming），具備開發高效能、高穩定性 App 的經驗。狀態管理與架構： 熟練使用 Riverpod 或 BLoC 進行狀態管理，並具備基礎的架構設計能力（如 MVVM）。網路通訊： 熟練使用 Dio 或 Chopper 進行 RESTful API 串接，且具備基本的錯誤處理與 Token 管理經驗。團隊協作與規範： 熟悉 Git Flow 開發流程，具備處理 Conflict、Code Review 經驗，並能撰寫規範化的 Commit Message。上架與發佈： 具備獨立完成 App Store 與 Google Play 上架流程的經驗，熟悉憑證管理與隱私政策規範。 　 ▍加分條件 原生開發能力： 熟悉 Swift 或 Kotlin，具備閱讀原生代碼與開發/維護原生插件（Plugins）的能力。進階架構設計： 具備大型專案設計經驗，能落實 Clean Architecture 並兼顧程式碼的可測試性與可維護性。深度開發思維： 具備原生 (Native) 與跨平台開發思維，熟悉不同系統（Material Design 與 Cupertino）的 UI/UX 規範細節。工程自動化與分析： 熟悉 Firebase 完整生態系（如：透過 Remote Config 進行 A/B Testing、Crashlytics 效能追蹤），或具備 CI/CD 自動化部署經驗。溝通推動： 具備積極參與 API 規範（Swagger）討論的能力，能從開發端提出優化建議以提升前後端串接效率。 　 ▍關於我們的文化 在微程式，我們相信好的產品與服務來自彼此信任、坦誠溝通與持續共創。我們擁有： 開放的企業文化：團隊年輕有活力，熱愛想法激盪、討論與付諸實現。開創性工作內容：創新、創意是我們的DNA，不斷追求產品更加卓越。夥伴的價值共創：我們深信 1+12，團隊夥伴並肩共創走的更快更遠。

Established in 1987 and headquartered in Taiwan, TSMC pioneered the pure-play foundry business model with an exclusive focus on manufacturing its customers’ products. As of 2024, TSMC serves more than 500 customers and manufactures over 11,000 products for high-performance computing, smartphones, the Internet of Things (IoT), automotive, and digital consumer electronics. It is the world’s largest provider of logic ICs, with an annual capacity of 16 million 12-inch equivalent wafers. TSMC operates fabs in Taiwan as well as manufacturing subsidiaries in Washington State, Japan and China, and the Company began construction on a specialty technology fab in Dresden, Germany, in 2024. In Arizona, TSMC is building three fabs, with the first starting 4nm production in 2025, the second by 2028, and the third by the end of the decade. Intelligent Scheduling Development Department (ISDD) in TSMC's Intelligent Manufacturing Center (IMC) is responsible for the dispatch and scheduling of various TSMC fabs. It considers multiple constraints such as processes, machines, products, and waiting times, and employs three main methods: Automated rules (Rule based)Optimization through mathematical planning models (Model)Optimization with metaheuristic algorithms (Metaheuristic) The system determines the sequence of products that machines will produce in the future. Colleagues continuously refine the computational engine to improve solving performance and scheduling quality. They also utilize self-developed scheduling systems to help fabs adapt to various scenarios to achieve fab goals and tasks. Moreover, they constantly enhance fab production efficiency and increase wafer output by identifying and capitalizing on opportunities for improvement.Responsibilities: Develop and maintain Scheduling / Dispatching and Manufacturing Report System.Communicate with users to define requirements, design, implement, and deploy systems, and continuously improve them using software engineering methodology.Design system architecture of cross department projects.Lead system design review.Survey and introduce new IT solutions.

About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact Marvell Compute and Custom Solutions has been at the forefront of developing and delivering leading-edge, high-performance data processing silicon platforms. By delivering a stream of technical innovations through a diverse set of fast-growing product lines, Marvell technology is powering the next-generation data processing and workload acceleration platforms for the Carrier, Cloud/Enterprise and Automotive Compute market segments. What You Can Expect Develop and implement verification plans for Serdes/PHY chip designs.Create and maintain testbenches using industry-standard verification tools and methodologies.Perform functional and performance verification of complex digital designs.Collaborate with design and architecture teams to identify and resolve design issues.• Analyze and debug simulation failures and provide detailed reports on verification results.• Mentor and guide junior verification engineers. What We're Looking For BS/MS/PhD Degree in Electrical Engineering / Computer Engineering / Electronics and Telecommunications Engineering, or a related field.Proficiency in verification languages such as SystemVerilog, UVM, and scripting languages (Python, Perl, etc.).Understanding of ASIC design flow, strong understanding of digital design and verification methodologies.Experience with industry-standard EDA tools (e.g., Cadence, Synopsys, Mentor Graphics).Strong mathematical skills.Strong problem-solving skills.Fluent in English language, excellent communication skills,Preferred Qualifications: Experience with high-speed Serdes/PHY interfaces design/design verification. Additional Compensation and Benefit Elements Competitive salary, plus 13th-month salary and performance-based bonusRSUs (Restricted Stock Units) for new joiners and on-going annuallyPremium health accident insurance for you and your family (spouse and children)Annual medical check-up at a designated hospital arranged by MarvellGenerous paid leave policies: 15 annual leave days, 3 Recharge periods per year (company-wide off-work from Friday to Monday), 5 paid sick leave days, 3 days of volunteer time-off and 11 public holidaysExciting Employee Events: Participate in fun activities throughout the year such as team birthdays, sports tournaments, company trips, mid-autumn, appreciation week, charity, health seminars, year-end party, and more. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. Interview Integrity To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews. These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process. This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.

Berry AI builds AI-powered operations platforms for QSR restaurants — drive-thru analytics, loss prevention, and store management tooling deployed across thousands of locations across the US — and growing. We're hiring a Senior Full-Stack Engineer who ships product features fast and brings the operational discipline to run them reliably. What you'll work on • Ship product features end-to-end across our hybrid cloud-edge architecture — from edge services through cloud APIs to the daily analytics restaurant operators rely on. • Build out our data platform — data ingestion pipelines from thousands of stores, dbt models, and the warehouse powering our dashboards. • Collaborate with our AI engineers to turn their models into product features — clean APIs, intuitive UIs, and the insights they unlock. • Contribute to the operational backbone — Ansible playbooks, CI/CD pipelines, and observability — that lets us deploy, monitor, and operate the fleet. • Strengthen our on-call practice — leading postmortems, sharpening alerting and runbooks, and turning incidents into durable fixes.

We are seeking a PCB Hardware Design Engineer to participate in the design, development, and testing of FPGA-based signal processing systems for defense applications. Key responsibilities: Designing signal processing boards using Xilinx RFSoC Gen3 with integrated high-speed ADC/DAC.Developing schematics and multi-layer PCB layouts in compliance with VPX military/industrial standards.Integrating high-speed interfaces such as Ethernet, JESD204B/C, PCIe, UART, USB, CAN, I2C, RS422, RAM, and Flash memory.Designing power architecture, including power trees and power supply circuits for FPGA systems (Power Management, Switching Regulators, LDOs, etc.).Creating and managing BOMs, and working with manufacturers to ensure product quality and fabrication/assembly readiness.Collaborating closely with system, FPGA, embedded software, and mechanical teams to ensure cohesive design integration.Participating in board bring-up, signal validation, performance evaluation, and debugging using tools such as oscilloscopes, logic analyzers, and DMMs.Supporting final system integration, field testing, troubleshooting, and performance optimization.