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Google welcomes people with disabilities.Minimum qualifications: Bachelor's degree or equivalent practical experience. 2 years of experience with software development in one or more programming languages (e.g., Python, C++, Rust, Go). Preferred qualifications: Experience with aut

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.Role Overview Astera Labs is at the epicenter of the AI infrastructure revolution, building the intelligent connectivity solutions that power the world's most advanced data centers. As AI workloads scale to unprecedented levels, the demand for purpose-built, rack-scale platforms that seamlessly integrate high-speed connectivity, firmware intelligence, and composable architectures has never been greater — and neither has the opportunity to shape what comes next. The AI Platform Solutions Group is seeking a Distinguished Engineer to serve as the technical visionary for next-generation AI infrastructure, spanning server firmware, high-speed connectivity, and rack-scale system design. In this role, you will define the end-to-end architecture for AI platforms that integrate cutting-edge technologies such as PCIe Gen5/6, composable rack architectures, and advanced interconnect solutions including Astera Labs' portfolio of retimers, switches, and fabric controllers. This is a high-impact, high-visibility role where you will drive innovation across silicon integration, platform firmware, system performance, and rack-level orchestration — directly enabling hyperscale AI training and inference workloads. You will partner with silicon vendors, hyperscalers, OEMs, and ODMs while influencing industry standards and mentoring the next generation of platform architects. If you want to architect the future of AI infrastructure at a company that is defining the connectivity backbone of modern data centers, this is your role. Key Responsibilities AI Platform Rack-Scale Architecture Define the end-to-end architecture for AI platforms, from node-level design to rack-scale composable systems Drive adoption of PCIe-based fabrics for disaggregated compute, memory, and accelerator scalability Architect solutions for GPU/accelerator-dense systems optimized for AI training and inference workloads Lead integration of connectivity solutions — retimers, switches, and fabric controllers — aligned with Astera Labs' product ecosystem Firmware Platform Leadership Drive innovation in server BIOS/UEFI architecture, OpenBMC-based platform management, Redfish APIs for scalable infrastructure control, and lifecycle provisioning frameworks Lead system bring-up and ensure seamless firmware-hardware-software integration across complex AI platforms Define the technical vision and multi-year firmware roadmap for AI infrastructure platforms Performance Optimization Own end-to-end AI platform performance strategy including PCIe topology optimization, bandwidth scaling, latency reduction, and CPU performance tuning for AI orchestration workloads Drive memory performance optimization across DDR, NUMA, and emerging memory expansion technologies Lead performance tuning for multi-accelerator systems (GPU/ASIC/FPGA), high-throughput data pipelines, and distributed AI workloads Ecosystem Industry Leadership Collaborate with silicon vendors (CPU, GPU, AI accelerators), connectivity ecosystem partners, OEMs, ODMs, and hyperscalers Influence industry standards across OpenBMC, Redfish, OCP, and related consortia Mentor senior engineers and grow deep technical bench strength across the organization Represent Astera Labs as a recognized thought leader in AI infrastructure and platform innovation Basic Qualifications Bachelor's degree in Computer Science, Electrical Engineering, Computer Engineering, or a related field 15+ years of experience in system architecture, server firmware, or platform engineering Deep expertise in server BIOS/UEFI, OpenBMC and BMC firmware stacks, and Redfish or datacenter management frameworks Strong knowledge of PCIe architecture and performance optimization (Gen4/5/6) Experience with CPU, memory, and system-level performance tuning for high-performance computing or AI platforms Strong programming experience in C/C++ and low-level system software Proven track record of leading cross-functional, large-scale architecture initiatives Preferred Qualifications Master's degree or PhD in Computer Science, Electrical Engineering, or a related field Experience with rack-scale composable infrastructure and disaggregated architectures Background in AI training clusters, accelerator-based systems, or hyperscale datacenter design Expertise in high-speed interconnect solutions such as retimers, switches, and fabric ICs Experience with platform lifecycle management systems and fleet-level automation Contributions to industry standards bodies or open-source firmware ecosystems Demonstrated ability to define multi-year technical roadmaps and influence executive strategy We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com. Role Overview Astera Labs is at the epicenter of the AI infrastructure revolution, building the intelligent connectivity solutions that power the world's most advanced data centers. As AI workloads scale to unprecedented levels, the demand for purpose-built, rack-scale platforms that seamlessly integrate high-speed connectivity, firmware intelligence, and composable architectures has never been greater — and neither has the opportunity to shape what comes next. The AI Platform Solutions Group is seeking a Distinguished Engineer to serve as the technical visionary for next-generation AI infrastructure, spanning server firmware, high-speed connectivity, and rack-scale system design. In this role, you will define the end-to-end architecture for AI platforms that integrate cutting-edge technologies such as PCIe Gen5/6, UAlink, CXL, composable rack architectures, and advanced interconnect solutions including Astera Labs' portfolio of retimers, switches, and fabric controllers. This is a high-impact, high-visibility role where you will drive innovation across silicon integration, platform firmware, system performance, and rack-level orchestration — directly enabling hyperscale AI training and inference workloads. You will partner with silicon vendors, hyperscalers, OEMs, and ODMs while influencing industry standards and mentoring the next generation of platform architects. If you want to architect the future of AI infrastructure at a company that is defining the connectivity backbone of modern data centers, this is your role. Key Responsibilities AI Platform Rack-Scale Architecture Define the end-to-end architecture for AI platforms, from node-level design to rack-scale composable systems Drive adoption of PCIe/UAlink-based fabrics for disaggregated compute, memory, and accelerator scalability Architect solutions for GPU/accelerator-dense systems optimized for AI training and inference workloads Lead integration of connectivity solutions — retimers, switches, and fabric controllers — aligned with Astera Labs' product ecosystem System Architecture Platform Leadership Lead system architecture and design for high-performance compute platforms optimized for AI and accelerator-driven workloads Design and integrate PCIe-based subsystems including GPU, accelerator, and high-speed I/O components leveraging PCIe Gen5/6 technologies Define and implement GPU-enabled server platforms for AI training, inference, and HPC workloads Architect and optimize high-speed Ethernet networking interfaces (25G/100G/400G+) within platform designs Define the technical vision and multi-year product roadmap for AI infrastructure platforms Platform Management Cross-Functional Leadership Define and implement platform management solutions including BMC integration, telemetry, health monitoring, and system-level diagnostics Collaborate with cross-functional teams spanning hardware, firmware, BIOS, and OS to ensure seamless platform integration Partner with silicon vendors, OEMs, and hyperscalers on custom platform development aligned with Astera Labs' connectivity ecosystem Drive performance optimization across PCIe topology, accelerator interconnects, and memory subsystems Own end-to-end AI platform performance strategy including PCIe topology optimization, bandwidth scaling, latency reduction, and CPU performance tuning for AI orchestration workloads Lead performance tuning for multi-accelerator systems (GPU/ASIC/FPGA), high-throughput data pipelines, and distributed AI workloads Ecosystem Industry Leadership Collaborate with silicon vendors (CPU, GPU, AI accelerators), connectivity ecosystem partners, OEMs, ODMs, and hyperscalers Influence industry standards across OpenBMC, Redfish, OCP, and related consortia Mentor senior engineers and grow deep technical bench strength across the organization Represent Astera Labs as a recognized thought leader in AI infrastructure and platform innovation Basic Qualifications Bachelor's degree in Computer Science, Electrical Engineering, Computer Engineering, or a related field 15+ years of experience in system architecture, server firmware, or platform engineering Deep expertise in server BIOS/UEFI, OpenBMC and BMC firmware stacks, and Redfish or datacenter management frameworks Strong knowledge of PCIe architecture and performance optimization (Gen4/5/6) Experience with CPU, memory, and system-level performance tuning for high-performance computing or AI platforms Strong programming experience in C/C++ and low-level system software Proven track record of leading cross-functional, large-scale architecture initiatives Preferred Qualifications Master's degree or PhD in Computer Science, Electrical Engineering, or a related field Experience with rack-scale composable infrastructure and disaggregated architectures Background in AI training clusters, accelerator-based systems, or hyperscale datacenter design Expertise in high-speed interconnect solutions such as retimers, switches, and fabric ICs Experience with platform lifecycle management systems and fleet-level automation Contributions to industry standards bodies or open-source firmware ecosystems Demonstrated ability to define multi-year technical roadmaps and influence executive strategy We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Minimum qualifications: PhD degree in Electronics and Communication Engineering, Electrical Engineering, Computer Engineering or related technical field, or equivalent practical experience. Experience with accelerator architectures and data center workloads. Experience in programming languages (e.g., C++, Python, Verilog), Synopsys, Cadence tools. Preferred qualifications: 2 years of experience post PhD. Experience with performance modeling tools. Knowledge of arithmetic units, bus architectures, accelerators, or memory hierarchies. Knowledge of high performance and low power design techniques. About the jobIn this role, you will shape the future of AI/ML hardware acceleration as a Silicon Architect/Design Engineer and drive cutting-edge TPU (Tensor Processing Unit) technology that fuels Google's most demanding AI/ML applications. You will collaborate with hardware and software architects and designers to architect, model, analyze, define and design next-generation TPUs. You will have dynamic, multi-faceted responsibilities in areas such as product definition, design, and implementation, collaborating with the Engineering teams to drive the optimal balance between performance, power, features, schedule, and cost.The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide. We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.Responsibilities Revolutionize Machine Learning (ML) workload characterization and benchmarking, and propose capabilities and optimizations for next-generation TPUs. Develop architecture specifications that meet current and future computing requirements for AI/ML roadmap. Develop architectural and microarchitectural power/performance models, microarchitecture and RTL designs and evaluate quantitative and qualitative performance and power analysis. Partner with hardware design, software, compiler, Machine Learning (ML) model and research teams for effective hardware/software codesign, creating high performance hardware/software interfaces. Develop and adopt advanced AI/ML capabilities, drive accelerated and efficient design verification strategies and implementations. Use AI techniques for faster and optimal Physical Design Convergence -Timing, floor planning, power grid and clock tree design etc. Investigate, validate, and optimize DFT, post-silicon test, and debug strategies, contributing to the advancement of silicon bring-up and qualification processes. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.

Google welcomes people with disabilities.Minimum qualifications: Bachelor's degree in a technical field, or equivalent practical experience. 5 years of engineering program management experience in consumer electronics, phones, systems, or new technology introduction. Preferred qualifications: 5 years of experience managing cross-functional or cross-team projects. Knowledge of electrical engineering (EE) systems or mechanical engineering (ME), manufacturing processes, and collaboration with Contract Manufacturers (CM). Excellent team player and creative thinking skills, with the ability to lead the collaboration among technical teams, cross-functional groups, and vendors in accordance with plans. Excellent communication, organizational execution, and leadership skills. About the jobGoogle's projects, like our users, span the globe and require managers to keep the big picture in focus while being able to dive into the unique engineering challenges we face daily. As a Technical Program Manager at Google, you lead complex, multi-disciplinary engineering projects using your engineering expertise. You plan requirements with internal customers and usher projects through the entire project lifecycle. This includes managing project schedules, identifying risks and clearly communicating them to project stakeholders. You're equally at home explaining your team's analyses and recommendations to executives as you are discussing the technical trade-offs in product development with engineers.Using your extensive technical and leadership expertise, you manage projects of various size and scope, identifying future opportunities, improving processes and driving the technical directions of your programs. The Advanced Architecture TPgM will bring broad technical expertise coupled with program management experience. Fearless leaders and organizers -they work cross-functionally with internal teams and external suppliers. The Advanced Architecture TPgM sets strategy, streamlines productivity, executes on highly ambiguous early technology projects, and is responsible for managing/communicating status and issues.The Google Pixel team focuses on designing and delivering the world's most helpful mobile experience. The team works on shaping the future of Pixel devices and services through some of the most advanced designs, techniques, products, and experiences in consumer electronics. This includes bringing together the best of Google’s artificial intelligence, software, and hardware to build global smartphones and create transformative experiences for users across the world.Responsibilities Lead complex architecture for DSPG hardware projects through pre-NPI milestones. Work closely with cross-functional teams on design integration and validation. Drive new material validation and tracking. Partner with Engineering leadership to streamline team effectiveness. Drive early execution and schedule for proof-of-concept builds. Provide executive status on technical, logistical, and strategic issues with risk registers. Gather ad-hoc management requests (daily standup, budgeting). Provide structure for new architecture and material initiatives. Track performance metrics and support competitive analysis. Communicate project status to stakeholders and leadership. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.

Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 10 years of experience in ASIC development with Verilog/SystemVerilog, Vhsic Hardware Description Language (VHDL). Experience in micro-architecture and design IPs and subsystems. Experience in ASIC design verification, synthesis, timing/power analysis, and Design for Testing (DFT). Preferred qualifications: Experience with scripting languages (e.g., Python or Perl). Experience in SoC designs and integration flows. Knowledge of bus architectures, fabrics/NoC, processor design, accelerators, or memory hierarchies.. Knowledge of high-performance and low-power design techniques. About the jobIn this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. In this role, you will be part of a team developing Application-Specific Integrated Circuits (ASIC) used to accelerate and improve traffic efficiency in data centers. You will collaborate with members of architecture, verification, power and performance, physical design, etc. to specify and deliver high quality designs for next generation data center accelerators. You will solve technical problems with innovative micro-architecture and practical logic solutions, and evaluate design options with complexity, performance, power and area in mind.The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide. We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.Responsibilities Drive development of complex IPs and subsystems along with a team of engineers. Own micro-architecture and implementation of IPs and subsystems. Work with architecture, firmware and software teams to drive feature closure and develop micro-architecture specifications. Drive design methodology, libraries, debug, code review in coordination with other IPs Design Verification (DV) teams and physical design teams. Identify and drive power, performance and area improvements for the domains owned. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.

【職務內容】 - 參與系統基礎建設、CI/CD 流程建置、開發、測試、生產環境的建置 - 開發與設計伺服器基礎設施、建置可擴展性的架構來運行服務 - 使用雲端服務搭建所需系統和平台，以及持續的調整與優化 - 支持軟體的快速迭代包括部署、變更、發布、故障處理等 - 編寫網路架構設計相關文檔、評估時程 - 處理主管交辦事項 - 標配MAC電腦(本職務工作地點位於桃園) 【上班時間】 早上 9 點至下午 6 點並且有 30 分鐘彈性上下班 【公司福利】 勞健保、三節、尾牙、生日禮金。 我們公司設有咖啡休息區，免費零食、飲料、餐點，飲品，備有微波爐。 不定時

Responsibilities: High-Quality Code Delivery:Write clean, concise, easy-to-read, and well-documented code to ensure the system is maintainable and scalable.Ensure code is designed for scalability and performance, anticipating future growth and changes.System Analysis and Refactoring:Analyze existing system code, refactor and optimize it, and write tests to ensure system stability and performance.Propose and implement refactoring strategies that improve maintainability, performance, and readability of the system.Code Review and Team Collaboration:Actively participate in code reviews, provide constructive feedback on pull requests, and help the team continuously improve.Share best practices to elevate the overall code quality within the team.Requirements Understanding and System Design:Collaborate closely with product and business teams to thoroughly understand requirements and contribute to system architecture design, implementing effective technical solutions.Contribute to the design and architecture of scalable systems, ensuring alignment with overall product strategy.Identify potential technical challenges early and propose effective solutions.International Team Collaboration:Work with global engineering teams, engaging in technical communication and collaboration to drive product innovation.

產業類別： 電腦/週邊設備製造 職責要求 一、團隊與組織管理 1.領導企業營運開發團隊（SAP開發 / Integration / AI應用） 2.建立系統開發與交付機制（SDLC / Agile / DevOps） 3.負責團隊人力規劃、技術培育與績效管理（約 3–5 人） 4.與營運管理課協同，確保開發與維運順利銜接 二、系統與架構治理 1.主導企業系統架構設計（SAP S/4HANA + 異質系統整合） 2.規劃系統整合架構（API / Interface / Middleware） 3.設計資料架構與資料流（Data Model / Data F

【Company Highlights】 🌟 Specializing in AI-driven customer service solutions and virtual assistants, and using natural language processing and machine learning for automated interactions🌟 Aims to enhance customer experience and streamline business operations through AI technolog