Cake Job Search

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.Job Description: As an Analog/Mixed-Signal IC Design Engineer , you will be part of a key team designing sophisticated advanced node CMOS products. Your responsibilities will include developing and verifying circuits such as PLL, DLL, ADC, regulators, amplifiers, TX, RX, and CDRs to meet performance targets. You will also work on analog and clocking blocks for connectivity applications, using industry-standard tools like Spectre and MATLAB. The company seeks a highly motivated designer for this role Basic Qualifications: Pursuing a Master’s or PhD degree in EE is preferred Desired Experience: Hands-on experience in designing high-speed mixed-signal circuits including ADC/DAC data converters, RX front-end, TX driver/serializer, low-jitter PLLs, TX/RX calibration, low-jitter CLK distribution are other high-speed analog circuits is a must Have a deep understanding of biasing, band-gaps, reference circuits, opamps, comparators and other analog circuits Solid track-record for implementation of analog circuits high-speed data transmission. Design and tapeout experience in advanced CMOS nodes (ex. 20nm or newer) is a must Solid fundamentals in detailed transistor-level design, feedback/stability analysis, and noise/jitter analysis. Knowledge of TIA design and drivers for optical applications is highly desirable Experience in RFIC design for wireless or wireline communication systems is highly desirable. Strong technical independent contributor with a proven ability to drive results. Excellent teamwork, presentation, and documentation skills. Ability to collaborate with global teams across multiple time zones and deliver under pressure with strict deadlines. Strong experience in lab chip bring-up and debugging efforts. Relevant research publications and/or patents in analog or RF IC design. Familiarity in programming/scripting languages such as Python, Matlab, or C. Experience with PCB design. Familiarity with Verilog RTL or DSP design concepts. Knowledge of optical transceivers. Expertise in ESD protection techniques and IC packaging methodologies. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.Job Description: As an Analog/Mixed-Signal IC Design Engineer Intern, you will be part of a key team designing sophisticated advanced node CMOS products. Your responsibilities will include developing and verifying circuits such as PLL, DLL, ADC, regulators, amplifiers, TX, RX, and CDRs to meet performance targets. You will also work on analog and clocking blocks for connectivity applications, using industry-standard tools like Spectre and MATLAB. The company seeks a highly motivated designer for this role Basic Qualifications: Pursuing a Master’s or PhD degree in EE is preferred Desired Experience: Hands-on experience in designing high-speed mixed-signal circuits including ADC/DAC data converters, RX front-end, TX driver/serializer, low-jitter PLLs, TX/RX calibration, low-jitter CLK distribution are other high-speed analog circuits is a must Have a deep understanding of biasing, band-gaps, reference circuits, opamps, comparators and other analog circuits Solid track-record for implementation of analog circuits high-speed data transmission. Design and tapeout experience in advanced CMOS nodes (ex. 20nm or newer) is a must Solid fundamentals in detailed transistor-level design, feedback/stability analysis, and noise/jitter analysis. Knowledge of TIA design and drivers for optical applications is highly desirable Experience in RFIC design for wireless or wireline communication systems is highly desirable. Strong technical independent contributor with a proven ability to drive results. Excellent teamwork, presentation, and documentation skills. Ability to collaborate with global teams across multiple time zones and deliver under pressure with strict deadlines. Strong experience in lab chip bring-up and debugging efforts. Relevant research publications and/or patents in analog or RF IC design. Familiarity in programming/scripting languages such as Python, Matlab, or C. Experience with PCB design. Familiarity with Verilog RTL or DSP design concepts. Knowledge of optical transceivers. Expertise in ESD protection techniques and IC packaging methodologies. The pay range for this role is $55-65/hour + $500 housing stipend + cash relocation bonus (dependent on location) We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

DRAM IC circuit design:1. Digital circuit design, Mixed Signal design , design verified by Verilog and Hspice 2. 需理解數位邏輯及CMOS元件動作, 可建立電路及模擬驗證3. 對 Array structure memory periphery control 有經驗佳4. 對 High speed S2P/P2S, DLL clock de-skew, DCC 有經驗佳5. 對 Design For Testing (DFT) 及BIST有經驗佳6. 具備良好團隊合作精神及溝通能力, 主動且積極學習態度Digital IC function verification:1. build up verilog testbench2. fullchip verilog simulation/verification3. verilog behavior models creation4. pattern pool coverage raising up

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.Job Description: As an Analog/Mixed-Signal IC Design Engineer, you will be part of a key team designing sophisticated advanced node CMOS products. Your responsibilities will include developing and verifying circuits such as PLL, DLL, ADC, regulators, amplifiers, TX, RX, and CDRs to meet performance targets. You will also work on analog and clocking blocks for connectivity applications, using industry-standard tools like Spectre and MATLAB. The company seeks a highly motivated designer for this role Basic Qualifications: Strong academic and technical background in electrical engineering. A Master’s or PhD degree in EE is required, preferably from a top-tier university. 8+ years of experience supporting or developing complex analog IC designs. Required Experience: Hands-on experience in designing high-speed mixed-signal circuits including ADC/DAC data converters, RX front-end, TX driver/serializer, low-jitter PLLs, TX/RX calibration, low-jitter CLK distribution are other high-speed analog circuits is a must Have a deep understanding of biasing, band-gaps, reference circuits, opamps, comparators and other analog circuits Solid track-record for implementation of analog circuits high-speed data transmission. Design and tape out experience in advanced CMOS nodes (ex. 7nm, 5nm 3nmFinFET) is a must. Solid fundamentals in detailed transistor-level design, feedback/stability analysis, and noise/jitter analysis. Knowledge of TIA design and drivers for optical applications is highly desirable Experience in RFIC design for wireless or wireline communication systems is highly desirable. Strong technical independent contributor with a proven ability to drive results. Excellent teamwork, presentation, and documentation skills. Ability to collaborate with global teams across multiple time zones and deliver under pressure with strict deadlines. Strong experience in lab chip bring-up and debugging efforts. Preferred Experience: Relevant research publications and/or patents in analog or RF IC design. Familiarity in programming/scripting languages such as Python, Matlab, or C. Experience with PCB design. Familiarity with Verilog RTL or DSP design concepts. Knowledge of optical transceivers. Expertise in ESD protection techniques and IC packaging methodologies. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com. As an Integrated Circuit Designer, you will be part of a key team designing sophisticated advanced node CMOS products. Key Job Duties: The design and development of the layout for integrated circuits according to electronics engineering principles, using software to create design schematics and diagrams. This will include [developing and verifying circuits such as PLL, DLL, ADC, regulators, amplifiers, TX, RX, and CDRs to meet performance targets]. The management of manufacturing process of the products, including technology yield and performance of the products. The development of test programmes and procedures to ensure the products meet their performance specifications. This will include [working on analog and clocking blocks for connectivity applications, using industry-standard tools like Spectre and MATLAB]. The provision of advice on aspects of semiconductor process technology and maintain and repair semiconductor process equipment. Basic Qualifications Strong academic and technical background in electrical engineering. A Master’s or PhD degree in EE is required, preferably from a top-tier university. 6+ years of experience supporting or developing complex analog IC designs. Required Experience: Hands-on experience in designing high-speed mixed-signal circuits, including ADC/DAC data converters, RX front-end, TX driver/serializer, low-jitter PLLs, TX/RX calibration, low-jitter CLK distribution and other high-speed analog circuits is a must. Have a deep understanding of biasing, band-gaps, reference circuits, opamps, comparators and other analog circuits. Solid track-record for implementation of analog circuits high-speed data transmissions. Design and tapeout experience in advanced CMOS nodes (ex. 20nm or newer) is a must. Solid fundamentals in detailed transistor-level design, feedback/stability analysis, and noise/jitter analysis. Knowledge of TIA design and drivers for optical applications is highly desirable. Experience in RFIC design for wireless or wireline communication systems is highly desirable. Strong technical independent contributor with a proven ability to drive results. Excellent teamwork, presentation, and documentation skills. Ability to collaborate with global teams across multiple time zones and deliver under pressure with strict deadlines. Strong experience in lab chip bring-up and debugging efforts. Preferred Experience: Relevant research publications and/or patents in analog or RF IC design. Familiarity in programming/scripting languages such as Python, Matlab, or C. Experience with PCB design. Familiarity with Verilog RTL or DSP design concepts. Knowledge of optical transceivers. Expertise in ESD protection techniques and IC packaging methodologies. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

【Position Overview】Lead and support CIS (CMOS Image Sensor) Wafer-Level CSP packaging process development with OSAT partners in China and Taiwanto drive project execution, ensure manufacturing readiness, and conduct quality and system audits prior to mass production. The positionalso requires strong cross-functional coordination within the company.【Responsibilities】1. Develop and optimize CIS WLCSP packaging processes from NPI to mass production.2. Drive project execution and technical alignment with OSAT partners.3. Lead pre-HVM quality and system audits to ensure manufacturing readiness.4. Resolve packaging process, yield, and reliability issues for new technology.5. Collaborate with RD, Product, Quality, Supply Chain, and Manufacturing teams.6. Complete tasks assigned by supervisors.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.We are looking for a Analog / Mixed-Signal Layout Engineerto join our ASIC team working on the forefront of high-performance compute and networking standards in advanced CMOS process nodes. The ideal candidate will have an impeccable hardware engineering background with an emphasis on VLSI and/or computer architecture. We are looking for experience in design, verification, and validation of real-world systems. Exposure to high-speed interfaces PCIE, DDR, HBM, Serdes technologies would be great to have. Above all, curiosity and ability to learn is a must. In this position you will be responsible for design and/or verification of blocks using leading edge methodology and tools. Basic qualifications: Pursuing BS or MS in EE/CS or related fields. Hardware engineering background with an emphasis in VLSI or Computer Architecture. Exposure to Digital design or verification, VLSI design and circuits, Computer Architecture. Required experience: Hands-on and knowledge of RTL design languages and tools including Verilog, System Verilog. Familiarity with verification methodologies like UVM, functional coverage, assertions. Familiarity with any of the scripting languages Python, Perl etc and hands-on experience in C/C++. Preferred experience: Real-world design and/or verification in Verilog/System Verilog. Knowledge of high-speed interfaces like PCIe, DDR, HBM, Serdes. Familiarity with Synopsys EDA tools. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com. Job Overview: As an Analog Mixed-Signal IC Layout Lead Engineer, you will play a critical role in designing advanced node Bi-CMOS / CMOS products. You will be responsible for managing chip top-level layout and integration along with block level layout design and ensuring successful tapeout. You will work to build state-of-the art high speed circuits minimizing layout parasitics, while applying techniques to reduce skew and crosstalk. Meeting EM/IR compliance requirements is essential. You will ensure strict adherence to DRC, LVS, ANT, and density rules. Additionally, awareness of ESD and latch-up design practices is expected to ensure robust and reliable layout implementations. You will apply a solid foundation in device physics, along with demonstrating a strong three-dimensional understanding of device layout. You will collaborate with a dynamic, cross-functional team of analog designers and layout engineers across multiple time zones. We are looking for a highly motivated, team-oriented individual who thrives in a collaborative environment. Basic Qualifications: Bachelor’s degree or advanced diploma in Electrical Engineering (EE) Required Experience: 10+ years of experience in high-speed analog IC layout using Cadence Virtuoso Prior experience with BiCMOS layout is strongly preferred Proven experience handling at least one chip top-level through tapeout Proficiency in layout extraction and parasitic analysis for high-speed circuits Awareness of EMIR and antenna DRC rule-compliant layout practices Experience with Cadence SKILL and TCL scripting is highly recommended We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com. Job Overview: As an Analog Mixed-Signal IC Layout Lead Engineer, you will play a critical role in designing advanced node Bi-CMOS / CMOS products. You will be responsible for managing chip top-level layout and integration along with block level layout design and ensuring successful tapeout. You will work to build state-of-the art high speed circuits minimizing layout parasitics, while applying techniques to reduce skew and crosstalk. Meeting EM/IR compliance requirements is essential. You will ensure strict adherence to DRC, LVS, ANT, and density rules. Additionally, awareness of ESD and latch-up design practices is expected to ensure robust and reliable layout implementations. You will apply a solid foundation in device physics, along with demonstrating a strong three-dimensional understanding of device layout. You will collaborate with a dynamic, cross-functional team of analog designers and layout engineers across multiple time zones. We are looking for a highly motivated, team-oriented individual who thrives in a collaborative environment. Basic Qualifications: Bachelor’s degree or advanced diploma in Electrical Engineering (EE) Required Experience: 8+ years of experience in high-speed analog IC layout using Cadence Virtuoso Prior experience with BiCMOS layout is strongly preferred Proven experience handling at least one chip top-level through tapeout Proficiency in layout extraction and parasitic analysis for high-speed circuits Awareness of EMIR and antenna DRC rule-compliant layout practices Experience with Cadence SKILL and TCL scripting is highly recommended We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.OverviewJoin our team as Senior Digital Design Engineer to contribute to the design and implementation of next-generation digital designs for high-performance connectivity solutions. You'll work on complex blocks from micro-architecture through silicon bring-up, collaborating with verification, PD, and DFT teams to deliver high-performance products in a fast-paced, collaborative environment. Key Responsibilities Own the RTL implementation of complex digital designs from micro-architecture through sign-off. Collaborate with verification teams to review test plans and debug issues. Support efforts to achieve timing closure and implement Design-for-Test (DFT) features. Scripting and automation for ASIC methodology improvement. Accountable for quality and overall design success with the support of senior engineers. Required QualificationsEducation Experience: Bachelor’s degree in electrical engineering or equivalent 3-8 years of experience developing SoC/silicon products in Server, Storage, and/or Networking markets Digital Design Expertise: Expertise in RTL coding with SystemVerilog and synthesis with Synopsys or Cadence. Track record of delivering high quality digital designs from definition to production. Experience with functional and formal verification at block and chip level. Understanding of clocking, CDC and RDC Experience with CMOS nodes (≤7nm) Protocols Integration: Familiarity with high-speed protocols—PCIe, Ethernet, DDR, or similar Experience with IP development and integration Tools Methodologies: Proven SystemVerilog and Python expertise in a production environment Familiarity with Synopsys and/or Cadence digital design flows Basic understanding of UVM-based verification methodologies Professional Attributes: Strong eagerness to learn and grow with the ability to balance multiple priorities in a dynamic environment Good communication and collaboration skills; comfortable working cross-functionally with global teams Self-directed learner who adapts quickly to changing requirements Customer-focused mindset with the ability to prioritize and work independently to deliver high quality designs. Preferred Qualifications Experience with embedded firmware development or standard embedded processor subsystems (RISC-V, Arm, etc.) is a plus Familiarity with design methodology, CAD automation, or design infrastructure that have improved team productivity or design quality is a plus Base salary range is $160,000 USD-$195,000 USD, and will be determined based on the candidate's capabilities and employees in similar positions. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.