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Minimum qualifications: Bachelor's degree in Electrical Engineering or a related field, or equivalent practical experience. 3 years of experience in DFT specification definition architecture and insertion. Experience using electronic design automation (EDA) test tools (e.g., Spyglass, Tessent). Experience with ASIC DFT synthesis, STA, simulation, and verification flow. Preferred qualifications: Master's degree in Electrical Engineering. Experience in IP integration (e.g., memories, test controll

1. Responsible for IC DFT design methodology development and project support. 2. Flow development for Memory BIST, Scan, Boundary Scan, ATPG and so on. 3. In house EDA utility development

- DFT specification generation and review with customer co-work. - Implement block/chip level DC/AC SCAN, BSD, MBIST, Memory Repair, System BIST and IP macro test. - Deliver quality DFT timing constraints and support BE team timing closure. - Do all verifications on DFT structures, and Deliver quality production ATE patterns. - support ATE bring-up, and debug the ATE patterns for production flow, DFT diagnosis for yield improvement. - Lead DFT implementation team to support

Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 5 years of experience in DFT/DFD flows and methodologies. Experience working with fault modeling, test standards and industry DFT/DFD/ATPG tools and with Application-Specific Integrated Circuits (ASIC) DFT, synthesis, simulation and verification flow. Experience developing DFT specifications and driving DFT architecture. Preferred qu

Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. 3 years of experience in ASIC development with Verilog/SystemVerilog, VHDL, or Chisel. Experience in ASIC design verification, synthesis, timing/power analysis, and Design for Testing (DFT). Experience in one or more SoC integration domains and flows (e.g., clocking, debug, fabrics, security, or low power methodologies). Preferred quali

Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. 8 years of experience in ASIC development with Verilog/SystemVerilog, VHDL. Experience with ASIC design verification, synthesis, timing/power analysis, and Design for Testing (DFT). Experience in micro-architecture and design of IPs and subsystems in Networking domain such as packet processing, bandwidth management, congestion control,

Minimum qualifications: Bachelor's degree in Computer Science, Electronics or Electrical Engineering, or equivalent practical experience. 5 years of experience in ASIC design for test including complete silicon life cycle through DFT pattern bring-up on ATE and manufacturing. Experience with ATPG, Low Power designs, BIST, JTAG, IJTAG tools and flow. Experience with DFT EDA tools (e.g., Tessent). Preferred qualifications: Experience with DFT for subsystems with multiple physical partitions. Exper

Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 8 years of experience in ASIC development with Verilog/SystemVerilog, VHDL. Experience in ASIC design verification, synthesis, timing/power analysis, and Design for Testing (DFT). Experience in micro-architecture and design of IPs and Subsystems in Networking domain such as Packet processing, bandwidth management, congestion control,

Minimum qualifications: Bachelor's degree in Computer Science, Electrical Engineering, Computer Engineering, a related technical field, or equivalent practical experience. 3 years of experience in ASIC/SoC development with Verilog/SystemVerilog. Experience in design of Machine Learning IPs, or graphics IPs, managing low precision/mixed precision numerics. Experience in ASIC design verification, synthesis, timing/power analysis, and Design for Testing (DFT). Preferred qualifications: Experience w

Minimum qualifications: Bachelor’s degree in Electrical Engineering or equivalent practical experience. 7 years of experience with advanced design, including clock/voltage domain crossing, Design for Testing (DFT), and low power designs. Experience with System on a Chip (SoC) cycles. Experience in high-performance, high-frequency, and low-power designs. Preferred qualifications: Master’s degree in Electrical Engineering. Experience in coding with System Verilog and scripting with TCL. Experience