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Minimum qualifications: Bachelor's degree or equivalent practical experience. 8 years of experience in areas of physical design. Experience in working on at least two chip tape outs. Preferred qualifications: Experience in high performance designs like CPUs, GPUs etc. Experience in performance, or power analysis and optimization. About the jobBe part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.Responsibilities Develop all aspects of Application-Specific Integrated Circuit (ASIC) RTL2GDS implementation for high PPA designs. Manage block and full-chip level physical implementation and QoR (power, timing, area). Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.

We are looking for a strong Operations Excellence professional to design, build, and deploy scalable warehouse operating systems across our network.This role will own end-to-end process design, system implementation, and performance stabilization, with the goal of creating a replicable and scalable warehouse model.1) Warehouse System DesignDesign end-to-end warehouse flows and Layout (Inbound, Puta way, Replenishment, Picking, Packing, Outbound, Returns)Define operating principles, SOPs, and exception playbooksIdentify bottlenecks and optimize layout, process, and system logic.2) Implementation DeploymentLead warehouse setup and go-live execution (process, system, people readiness)Partner with WMS/Tech/BI teams to deploy system configurations and data setupEstablish governance model: daily operations cadence, issue tracking, escalation.3) Performance Stabilization Drive hypercare and stabilize operations to meet SLA and productivity targetsBuild control tower (backlog, SLA, productivity, quality, inventory signals)Package and roll out standardized models across multiple sites.

Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 8 years of experience with digital logic design principles, RTL design concepts, and languages, such as Verilog or SystemVerilog. Experience with logic synthesis techniques to optimize RTL code, performance and power, as well as low-power design techniques. Experience in SoC designs and integration flows. Preferred qualifications: Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science. Experience with a scripting language like Perl or Python. Knowledge of arithmetic units, bus architectures, processor design, accelerators, or memory hierarchies. About the jobBe part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. In this role, you will work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive Tensor Processing Unit (TPU) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML- driven systems.The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide. We're the driving team behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.Responsibilities Participate in the design, implementation and integration of Chassis, subsystems and SoC. Perform RTL coding, function/performance simulation debug, and Lint/Clock-Domain Crossing (CDC)/Formal Verification(FV)/Unified Power Format (UPF) checks. Participate in design debug, and code review in coordination with other IPs Design Verification (DV) teams and physical design teams. Coordinate with various IP teams to meet schedule and quality requirements. Communicate and work with multi-disciplined and multi-site teams. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.

ĐỂ XEM ĐẦY ĐỦ THÔNG TIN TUYỂN DỤNG, VUI LÒNG CLICK "ỨNG TUYỂN"/"APPLY NOW" ĐIỀU KIỆN ỨNG TUYỂNIP/SOC design verificationAssist in the design and implementation of RTL for integrated circuits under the guidance of senior engineersSupport floor planning, power planning, placement, routing, and physical verification activities.Participate in timing closure and signal integrity analysis processes to ensure design reliability.Collaborate closely with RTL designers, verification engineers, and technology teams to optimize design methodologies.Contribute to the development and maintenance of design methodologies, automation flows, and scripts.Engage in design reviews, debugging tasks, and problem-solving activities to meet project timelines.

Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 8 years of experience in ASIC design implementation flows and chip integration. 8 years of Management experience in ASIC development teams. Experience executing low-power physical design implementation using industry-standard synthesis and Static Timing Analysis (STA) tools. Experience in sign-off convergence including STA, electrical checks, and physical verification. Preferred qualifications: Experience in leading physical design teams working on digital designs. Experience in engineering across physical design, implementation, GDS tape-out. Experience in floorplanning, block integration, static timing analysis, sign-off. Knowledge of delivery of silicon in technology process nodes and Ability to lead cross-functional teams. Understanding of Circuit design, device physics and deep sub-micron technology. About the jobIn this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.Responsibilities Manage Physical design of SoC to Tape out while working with multiple team members. Evaluate and develop physical design methodologies and decide on the SoC flow. Work with architects and logic designers to drive architectural feasibility studies, develop timing, power and area design goals, and explore RTL/design trade-offs for physical design closure. Participate in design reviews and track issue resolution, and engage in technical and schedule trade-off discussions. Create execution plans for projects and manage team efforts from concept to working silicon in volume. Understand architecture and design specifications with the team, and define physical design strategies to meet quality and schedule goals. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.

Google will be prioritizing applicants who have a current right to work in Singapore, and do not require Google's sponsorship of a visa.Minimum qualifications: Bachelor's degree in Network Engineering or Telecom Engineering, a related technical field, or equivalent practical experience. 2 years of experience in Dense Wave-Division Multiplexing (DWDM) or Transmission Control Protocol/Internet Protocol (TCP/IP) or system design operations methodology. Preferred qualifications: Experience in layer 1 optical transmissions systems, layer 3 routing TCP/IP, wireless networking, or network design or operations. Experience in DWDM topology and architecture with toubleshooting of DWDM systems. Knowledge of fiber types and their application, physical fiber characteristics, and standard testing tools (e.g., OSA, BERT, OTDR). Knowledge of networking and fundamentals of network troubleshooting at layer 1. Knowledge of network transport design, equipment and infrastructure. Excellent communication skills. About the jobAs a Network Implementation Engineer, you will be the initial point of our efforts to execute deployment, maintenance, and operations of private data networks worldwide. You will work with Technical Program Managers, Network Engineers, Design and Infrastructure Engineers, Field Engineers within Google, as well as construction and telecommunications vendors and contractors, all to position your team and organization for success. You will facilitate faster, better, and more efficient, positive outcomes for the business and our customers. Your objective will be to build the world’s most reliable, cost-effective and scalable network to support all of our current and future customers and users globally. Google's network provides services to millions of Internet users around the world. Our metros are on the edge of our network where Google connects to its users. The Network Team is responsible for operating that network reliably and at scale. Our team owns the full life cycle of all space, power, and network assets in all of Google’s data centers and metro points of presence globally. From the foundation, we are involved from site acquisition to construction and are accountable for what space and power is delivered. We're involved in every facet of network delivery from architecture and design to installation, configuration, activation, and commissioning.Responsibilities Build and operate Google's network. Focus on delivering Infrastructure capacity for Asia Pacific (APAC) region. Design, plan, and install support for optical transport. Work with executive engineers to develop approaches for keeping operational costs low through tooling and process improvements. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.OverviewJoin our team as Senior Digital Design Engineer to contribute to the design and implementation of next-generation digital designs for high-performance connectivity solutions. You'll work on complex blocks from micro-architecture through silicon bring-up, collaborating with verification, PD, and DFT teams to deliver high-performance products in a fast-paced, collaborative environment. Key Responsibilities Own the RTL implementation of complex digital designs from micro-architecture through sign-off. Collaborate with verification teams to review test plans and debug issues. Support efforts to achieve timing closure and implement Design-for-Test (DFT) features. Scripting and automation for ASIC methodology improvement. Accountable for quality and overall design success with the support of senior engineers. Required QualificationsEducation Experience: Bachelor’s degree in electrical engineering or equivalent 3-8 years of experience developing SoC/silicon products in Server, Storage, and/or Networking markets Digital Design Expertise: Expertise in RTL coding with SystemVerilog and synthesis with Synopsys or Cadence. Track record of delivering high quality digital designs from definition to production. Experience with functional and formal verification at block and chip level. Understanding of clocking, CDC and RDC Experience with CMOS nodes (≤7nm) Protocols Integration: Familiarity with high-speed protocols—PCIe, Ethernet, DDR, or similar Experience with IP development and integration Tools Methodologies: Proven SystemVerilog and Python expertise in a production environment Familiarity with Synopsys and/or Cadence digital design flows Basic understanding of UVM-based verification methodologies Professional Attributes: Strong eagerness to learn and grow with the ability to balance multiple priorities in a dynamic environment Good communication and collaboration skills; comfortable working cross-functionally with global teams Self-directed learner who adapts quickly to changing requirements Customer-focused mindset with the ability to prioritize and work independently to deliver high quality designs. Preferred Qualifications Experience with embedded firmware development or standard embedded processor subsystems (RISC-V, Arm, etc.) is a plus Familiarity with design methodology, CAD automation, or design infrastructure that have improved team productivity or design quality is a plus Base salary range is $160,000 USD-$195,000 USD, and will be determined based on the candidate's capabilities and employees in similar positions. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Minimum qualifications: PhD degree in Electronics and Communication Engineering, Electrical Engineering, Computer Engineering or related technical field, or equivalent practical experience. Experience in programming languages (e.g., C++, Python, Verilog), Synopsys, Cadence tools. Experience with accelerator architectures and data center workloads. Preferred qualifications: 2 years of experience in Silicon domain post PhD.Experience with performance modeling tools. Knowledge of arithmetic units, bus architectures, accelerators, or memory hierarchies. Knowledge of high performance and low power design techniques. About the jobIn this role, you will shape the future of AI/ML hardware acceleration as a Silicon Architect/Design Engineer and drive TPU (Tensor Processing Unit) technology that fuels Google's most demanding AI/ML applications. You will collaborate with hardware and software architects and designers to architect, model, analyze, define and design next-generation TPUs. You will have dynamic, multi-faceted responsibilities in areas such as product definition, design, and implementation, collaborating with the Engineering teams to drive the optimal balance between performance, power, features, schedule, and cost.Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.Responsibilities Revolutionize Machine Learning (ML) workload characterization and benchmarking, and propose capabilities and optimizations for next-generation TPUs. Develop architecture specifications that meet current and future computing requirements for AI/ML roadmap. Develop architectural and microarchitectural power/performance models, microarchitecture and RTL designs and evaluate quantitative and qualitative performance and power analysis. Partner with hardware design, software, compiler, Machine Learning (ML) model and research teams for effective hardware/software codesign, creating high performance hardware/software interfaces. Develop and adopt advanced AI/ML capabilities, drive accelerated and efficient design verification strategies and implementations. Use AI techniques for faster and optimal physical design convergence -timing, floor planning, power grid and clock tree design etc. Investigate, validate, and optimize DFT, post-silicon test, and debug strategies, contributing to the advancement of silicon bring-up and qualification processes. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.

Minimum qualifications: Bachelor's degree or equivalent practical experience. 8 years of experience in software development. 5 years of experience in testing, and launching software products. Experience in working with distributed and parallel systems. Preferred qualifications: Experience with working on ML/AI/GenAI systems. Experience with Generative AI (GenAI) model inference, prompt engineering and approaches using Liquid Foundation Models (LFMs) (e.g., Code assist, Vibe coding). About the jobGoogle Cloud's software engineers develop the next-generation technologies that change how billions of users connect, explore, and interact with information and one another. We're looking for engineers who bring fresh ideas from all areas, including information retrieval, distributed computing, large-scale system design, networking and data storage, security, artificial intelligence, natural language processing, UI design and mobile; the list goes on and is growing every day. As a software engineer, you will work on a specific project critical to Google Cloud's needs with opportunities to switch teams and projects as you and our fast-paced business grow and evolve. You will anticipate our customer needs and be empowered to act like an owner, take action and innovate. We need our engineers to be versatile, display leadership qualities and be enthusiastic to take on new problems across the full-stack as we continue to push technology forward. Google Cloud accelerates every organization’s ability to digitally transform its business and industry. We deliver enterprise-grade solutions that leverage Google’s cutting-edge technology, and tools that help developers build more sustainably. Customers in more than 200 countries and territories turn to Google Cloud as their trusted partner to enable growth and solve their most critical business problems.Responsibilities Develop a platform for designing and deploying enterprise applications in the Application Design Center (ADC). Collaborate with cross-functional stakeholders, and other engineering teams to ensure that cloud-based applications are developed and rolled out effectively. Utilize a variety of technologies, including Go, Java, Angular, Terraform, and other Artificial Intelligence/Machine Learning (AI/ML) and Google technologies, to design and develop solutions. Contribute to the design and implementation of features that enhance the ADC's capabilities. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.

Minimum qualifications: PhD degree in Electronics and Communication Engineering, Electrical Engineering, Computer Engineering, a related technical field, or equivalent practical experience. Experience in programming languages (e.g., C++, Python, Verilog), Synopsys, Cadence tools. Experience with accelerator architectures and data center workloads. Preferred qualifications: 2 years of experience in Silicon engineering post PhD. Experience with performance modeling tools. Knowledge of arithmetic units, bus architectures, accelerators, or memory hierarchies. Knowledge of high-performance and low-power design techniques. About the jobIn this role, you will shape the future of AI/ML hardware acceleration as a Silicon Architect/Design Engineer and drive Tensor Processing Unit (TPU) technology that fuels Google's most demanding AI/ML applications. You will collaborate with hardware and software architects and designers to architect, model, analyze, define and design next-generation TPUs. You will have dynamic, multi-faceted responsibilities in areas such as product definition, design, and implementation, collaborating with the Engineering teams to drive the optimal balance between performance, power, features, schedule, and cost.Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.Responsibilities Revolutionize Machine Learning (ML) workload characterization and benchmarking, and propose capabilities and optimizations for next-generation TPUs. Develop architecture specifications that meet current and future computing requirements for AI/ML roadmap. Develop architectural and microarchitectural power/performance models, microarchitecture and RTL designs and evaluate quantitative and qualitative performance and power analysis. Partner with hardware design, software, compiler, Machine Learning (ML) model and research teams for effective hardware/software codesign, creating high performance hardware/software interfaces. Develop and adopt advanced AI/ML capabilities, drive accelerated and efficient design verification strategies and implementations. Use AI techniques for faster and optimal physical design convergence-timing, floor planning, power grid and clock tree design, etc. Investigate, validate, and optimize DFT, post-silicon test, and debug strategies, contributing to the advancement of silicon bring-up and qualification processes. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.