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Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 4 years of experience with digital logic design principles, RTL design concepts, and languages, such as Verilog or SystemVerilog. 3 years of experience in ASIC design flows and methodologies, IP integration (subsystems, memories, IO's and analog IP) and RTL design. Experience with logic synthesis techniques to optimize RTL code, performance and power, as well as low-power design techniques. Experience in the semiconductor industry, with experience in emulation or FPGA prototyping. Preferred qualifications: Master's or PhD degree in Electrical Engineering, Computer Engineering, or Computer Science. Experience in a scripting language like Perl or Python. Knowledge of high-performance and low-power design techniques, assertion-based formal verification, FPGA and emulation platforms, and SOC architecture. About the jobBe part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide. We're the driving team behind Google's groundbreaking innovations, empowering the development of our AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.Responsibilities Participate in synthesis, timing/power closure, and Field Programmable Gate Array (FPGA)/silicon bring-up. Participate in test plan and coverage analysis of the block and ASIC-level verification. Modify ASIC Register-Transfer Level (RTL) for a given IP/subsytem to a dedicated FPGA prototyping platform. Run the end-to-end FPGA flow (including synthesis, place and route, timing) for an IP/subsystem. Develop the necessary collaterals (tests, porting scripts) to bring-up the IP/subsystem on the FPGA platform. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.

Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 4 years of experience with digital logic design principles, RTL design concepts, and languages, such as Verilog or SystemVerilog. Experience with logic synthesis techniques to optimize RTL code, performance and power, as well as low-power design techniques. Preferred qualifications: Master's or PhD degree in Electrical Engineering, Computer Engineering, or Computer Science. Experience with a scripting language like Perl or Python. Experience with ASIC or FPGA design verification, synthesis, timing/power analysis, and DFT. Knowledge of high-performance and low-power design techniques, assertion-based formal verification, FPGA and emulation platforms, and SOC architecture. Knowledge of memory compression, fabric, coherence, cache, or DRAM. About the jobBe part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. In this role you will contribute in creating the micro-architecture of the mobile SOC's subsystems, integrating multiple first-party/ third-party components, and running extensive quality checks including Lint, Clock Domain Crossing (CDC), low power checks (VCLP), synthesis, and timing and power analysis. You will be able to timely deliver Subsystems and work with various cross-functional teams ( DV/DFT/PD/Power) to ensure quality. The Platforms and Devices team encompasses Google's various computing software platforms across environments (desktop, mobile, applications), as well as our first party devices and services that combine the best of Google AI, software, and hardware. Teams across this area research, design, and develop new technologies to make our user's interaction with computing faster and more seamless, building innovative experiences for our users around the world.Responsibilities Define the block-level design document (e.g., interface protocol, block diagram, transaction flow, pipeline, etc.). Perform RTL coding, function/performance simulation debug, and Lint/Cyber Defense Center (CDC)/Formal Verification (FV)/Unified Power Format (UPF) checks. Participate in synthesis, timing/power closure, and FPGA/silicon bring-up. Participate in test plan and coverage analysis of the block and ASIC-level verification. Communicate and work with multi-disciplined and multi-site teams. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.

Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 4 years of experience with digital logic design principles, RTL design concepts, and languages, such as Verilog or SystemVerilog. 3 years of experience in ASIC design flows and methodologies, IP integration (e.g., subsystems, memories, IO's and Analog IP) and RTL design. Experience with logic synthesis techniques to optimize RTL code, performance and power, as well as low-power design techniques. Preferred qualifications: Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science. Experience working on memory controller/direct memory access (DMA). Experience with industry standard ASIC design tools for RTL lint, VCS, Verdi. Experience in AI accelerator design, data-path design. Knowledge of high-performance and low-power design techniques, assertion-based formal verification, FPGA and emulation platforms, and SOC architecture. About the jobBe part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. In this role, you will own System Verilog implementation, lead PPA (Power, Performance, Area) optimization experiments early on, and collaborate across the verification and physical design teams.The Platforms and Devices team encompasses Google's various computing software platforms across environments (desktop, mobile, applications), as well as our first party devices and services that combine the best of Google AI, software, and hardware. Teams across this area research, design, and develop new technologies to make our user's interaction with computing faster and more seamless, building innovative experiences for our users around the world.Responsibilities Define the block-level design document (e.g., interface protocol, block diagram, transaction flow, pipeline, etc.). Perform RTL coding, function/performance simulation debug, and Lint/CDC/FV/UPF checks. Participate in synthesis, timing/power closure, and FPGA/silicon bring-up. Participate in test plan and coverage analysis of the block and ASIC-level verification. Communicate and work with multi-disciplined and multi-site teams. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.

Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. 4 years of experience with digital logic design principles, RTL design concepts, and languages, such as Verilog or SystemVerilog. Experience with logic synthesis techniques to optimize RTL code, performance and power, as well as low-power design techniques. Preferred qualifications: Master's or PhD degree in Electrical Engineering, Computer Engineering, or Computer Science. Experience with a scripting language like Perl or Python. Experience with ASIC or FPGA design verification, synthesis, timing/power analysis, and DFT. Knowledge of high-performance and low-power design techniques, assertion-based formal verification, FPGA and emulation platforms, and SOC architecture. Knowledge of memory compression, fabric, coherence, cache, or DRAM. About the jobBe part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. In this role, you will be a part of the team which designs the SoC and Subsystem. You will be working through all phases of design and implementation. You will be working with architects to come up with microarchitecture specifications. You will use your logic design skills to convert the micro-arch into System Verilog code. You will be involved in Power, Performance and Area (PPA) experiments/prototyping experiments early on to optimize PPA. You will also work closely with the verification team to verify the features implemented in design. You will also work with the Physical Design (PD) team to take the design through the PD cycle and eventual tape-out.The Platforms and Devices team encompasses Google's various computing software platforms across environments (desktop, mobile, applications), as well as our first party devices and services that combine the best of Google AI, software, and hardware. Teams across this area research, design, and develop new technologies to make our user's interaction with computing faster and more seamless, building innovative experiences for our users around the world.Responsibilities Define the block-level design document (e.g., interface protocol, block diagram, transaction flow, pipeline, etc.). Perform RTL coding, function/performance simulation debug, and Lint/CDC/FV/UPF checks. Participate in test plan and coverage analysis of the block and ASIC-level verification. Communicate and work with multi-disciplined and multi-site teams. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.

Minimum qualifications: Bachelor's degree or equivalent practical experience. 5 years of experience with full-chip/SoC verification (e.g., test definition, creation, execution, and debug). Experience developing full-chip/SoC tests using the environments/tools (e.g., ASM, C, C++, Perspec, OS, or drivers). Experience with industry standard emulator technologies (e.g., HAPS, Zebu, Veloce, or Palladium) ranging from build tools to advanced capabilities (e.g. power aware emulation). Experience with execution and RTL/firmware/software debug on hardware emulation (e.g., ZeBu Server, Palladium, Veloce) or FPGA (e.g., Xilinx, Altera). Preferred qualifications: Experience with EDA debug tools (e.g., Verdi, SimVision/Indago, GDB). Experience in programming and scripting in C, C++, Python, Perl, or TCL. Experience with AI usage for enhancing emulation flows and debug. Understanding of SoC architecture and interfaces (e.g., DDR, PCIe, etc.). Understanding of RTL to Emulation/FPGA flows including emulation test benches, DFT and virtual machines (e.g., transactors/accelerated VIPs, hybrid, in-circuit emulation). About the jobIn this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. In this role, you will help design, verify, and deploy ASIC projects through emulation based prototyping. You will work directly with other emulation Prototyping team members as well as Designers, Design Verification (DV) Engineers, Silicon Validation Engineers, and Software teams to deliver emulation based prototyping capabilities for our ASIC projects, including compiling projects managing our prototyping platforms, debugging issues in infrastructure and design, and assisting in the hardware and lab bring up and validation of our ASIC systems.The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide. We're the driving team behind Google's groundbreaking innovations, empowering the development of our AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.Responsibilities Build full chip emulation or FPGA prototypes from complex SoC designs and deliver to multiple customers such as Software, Firmware, Platform, and Post-Silicon Validation teams. Influence the Design and Verification teams to add emulation friendly model development. Bring up of system level emulation models through reset, boot, and bare metal content or OS. Work with Architects, Designers, Software Engineers, Pre and Post-Silicon Verification Engineers to develop test plans, coverage, and to reproduce failures on emulation. Develop, execute, and debug full-chip/System on a Chip (SoC) tests on emulation platforms. Explore new verification and emulation methodologies and implement them. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.

Logitech is the Sweet Spot for people who want their actions to have a positive global impact while having the flexibility to do it in their own way.The Role:We are expanding our Test Automation team in Chennai to support and contributeto the development, maintenance, and improvement of our automation frameworks especially with FPGA for our Test fixtures. This position is ideal for someone with a strong technical foundation and a desire to grow into a specialist in test automation for embedded systems and consumer electronics.Your Contribution:In this role you will:● Support the deployment, maintenance, and improvement of Python-based Test Frameworks.● Contribute to the development and execution of automated test scripts using Python.● Participate in manual and automated testing methodologies.● Understand and follow detailed test plans and procedures to validate products.● Add/Modify FW Modules in Xilinx based FPGA Boards.● Perform basic debugging and troubleshooting.● Document test procedures, results, and contribute to user-friendly tool documentation.● Collaborate with validation engineers to ensure test coverage and product quality.● Learn and apply best practices in test design, automation, and quality assurance.Key Qualifications:For consideration, you must bring the following minimum skills and behaviors to our team:● 6–10 years of experience in software testing, automation, or embedded systems validation.● Solid knowledge of Python programming.● Interest in embedded systems testing and automation tools.● Exposure to manual and automated testing methodologies.● Ability to understand and execute detailed test plans and procedures.● Knowledge of electronics engineering fundamentals.● Hands-on assembly and wiring of electronic test benches, including integration of sensors,connectors, and harnesses.● Debugging and troubleshooting of electronic circuits, signal integrity, and connectivity issues.● Proficiency with lab equipment: oscilloscopes, USB analysers, power supplies, voltmeters, etc.● Familiarity with communication protocols such as UART,USB, Ethernet, Bluetooth.● Strong problem-solving and analytical skills.● Good verbal and written communication skills in English.● A team player with a willingness to learn and take guidance from senior engineers.In addition, preferable certification/skills include:● Xilinx Certified VHDL and Verilog Designer● ISTQB or equivalent certificationEducation:● Bachelor’s Degree in ECE/EEEAcross Logitech we empower collaboration and foster play. We help teams collaborate/learn from anywhere, without compromising on productivity or continuity so it should be no surprise that most of our jobs are open to work from home from most locations. Our hybrid work model allows some employees to work remotely while others work on-premises. Within this structure, you may have teams or departments split between working remotely and working in-house.Logitech is an amazing place to work because it is full of authentic people who are inclusive by nature as well as by design. Being a global company, we value our diversity and celebrate all our differences. Don’t meet every single requirement? Not a problem. If you feel you are the right candidate for the opportunity, we strongly recommend that you apply. We want to meet you!We offer comprehensive and competitive benefits packages and working environments that are designed to be flexible and help you to care for yourself and your loved ones, now and in the future. We believe that good health means more than getting medical care when you need it. Logitech supports a culture that encourages individuals to achieve good physical, financial, emotional, intellectual and social wellbeing so we all can create, achieve and enjoy more and support our families. We can’t wait to tell you more about them being that there are too many to list here and they vary based on location.All qualified applicants will receive consideration for employment without regard to race, sex, age, color, religion, sexual orientation, gender identity, national origin, protected veteran status, or on the basis of disability.If you require an accommodation to complete any part of the application process, are limited in the ability, are unable to access or use this online application process and need an alternative method for applying, you may contact us toll free at 1-510-713-4866 for assistance and we will get back to you as soon as possible.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com. Astera Labs is seeking highly motivated Interns to join the Sales team in the TW team. If you are: A Junior going into Senior year or Senior graduating by the end of this year Have strong academics and technical background in Electrical Engineering Someone with a professional attitude, ability to prioritize a dynamic list of multiple tasks and work with minimal guidance and supervision Strong in analytical skills, self-motivated and a challenge taker What we are looking for: Develop regional sales analysis and planning materials by identifying market segments, opportunity sizing, and internal execution strategies Support sales initiatives by partnering closely with FAEs and internal stakeholders to prepare product information, roadmap materials, technology training content, and internal documentation Consolidate and analyze input from internal teams to support product planning, roadmap alignment, and internal issue tracking Coordinate cross-functional information flow among sales, operations, and supply-related teams to support quarterly revenue planning and mid-term demand projections Assist in market and ecosystem research across CPU, GPU, FPGA, Networking, Memory, and BMC segments to identify co-development and strategic opportunity areas If the above position excites you, we would love to hear from you. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.As aSenior Software Diagnostics Engineer onthe Astera Labs Hardware Engineering team you will be responsible for building diagnostics and manufacturing software to allow design, test, and manufacture of cutting-edge high-speed datacenter products. You will be working on a project from conception to the final production stage at contract manufacturer. The role requires a strong and broad software background and a good understanding of hardware design and manufacturing practices. At the same time, we welcome candidates with deep experience in smaller areas and desire to learn. Depending on your experience, you may be focusing on design/validation or automation/manufacturing. Key Responsibilities: Design, implement test production-grade diagnostics for high-speed digital boards and ASICS to help with hardware validation. Design, implement test manufacturing tests to validate mass production of digital boards used in data center networking product Bring-up newly manufactured boards and port the first level of software. Isolate and perform root-cause analysis of reported failures Support new platform software and hardware features Coordinate with the hardware engineering team on bring-up schedules and feature delivery Participate proactively in design discussions, design review and project management Basic Qualifications Bachelors in Computer Science/Computer Engineering or equivalent experience. Knowledge of modern software development Proficiency in Python, C or similar Ability to work cross-functionally in a fast-paced, highly technical environment. Required Experience 2+ years of Experience in subset of diagnostics, hardware bring-up, test or manufacturing automation Strong debugging skills across hardware, firmware, and system layers Preferred Experience/Nice to Have Experience working with datacenter-level complex electronic equipment bring-up/diagnostic/manufacturing Ability to read schematic/layout System debug experience Embedded programming and good knowledge of OS internals (Linux/Unix) Has knowledge of common interconnecting buses and interfaces such as PCIe, I2C, XAUI, 10G Ethernet drivers, FPGA, Switch chips, SSL offload, TCAM programming. Experience with DDR5 The base salary range is $120,000 - $195,000. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Google welcomes people with disabilities.Note: By applying to this position you will have an opportunity to share your preferred working location from the following: New Taipei, Banqiao District, New Taipei City, Taiwan; Zhubei, Zhubei City, Hsinchu County, Taiwan.Minimum qualifications: Bachelor's degree in Electrical Engineering, a related field, or equivalent practical experience. 3 years of experience developing random stress tests, silicon validation frameworks, or related infrastructure. Experience programming in C/C++. Experience in Advanced RISC Machines (ARM) architecture and in IP level power management, Dynamic Voltage and Frequency Scaling (DVFS), or SoC/CPU/memory power management. Preferred qualifications: Experience executing tests on emulation platforms or Field Programmable Gate Array (FPGA) and with board level debug. Experience with complex system debug, embedded operating systems, and bare metal programming. Experience with JTAG debuggers (e.g., Lauterbach). Knowledge of low power design and architecture techniques. Knowledge of operating system fundamentals. Familiarity with Power Management Integrated Circuit (PMIC) and power modeling techniques. About the jobGoogle engineers develop the next-generation technologies that change how users connect, explore, and interact with information and one another. As a member of an extraordinarily creative, motivated and talented team, you develop new products that are used by millions of people. We need our engineers to be versatile and passionate to take on new problems as we continue to push technology forward. If you get excited about building new things and working across discipline lines, then our team might be your next career step. In this role, you will be a part of Google’s Silicon team, working to enable Google’s continuous innovations. You'll be responsible for bare-metal and operating system based validation, including both pre-silicon verification and post-silicon bring-up and validation, ensuring the delivery of high-quality silicon.Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.Responsibilities Plan, develop, and execute tests to validate IP, subsystem, and system level power management. Manage power correlation and power management design validation on pre-silicon and post-silicon platforms. Interface with Software, Architecture, Design, and Design Verification teams to create and execute test plans Support silicon debug and field failures. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.The Role and Its Impact OurTaurus product lineincludes Ethernetretimersand gearboxes deployed in active electrical cables and in-system applications, providing critical signal conditioning for high-speed connectivity in AI infrastructure. The firmware you develop will manage complex system and IP integration, SERDES configuration, link training sequences, and diagnostic capabilities for these devices deployed in data centers worldwide. As a Principal Engineer in our Signal Connectivity Engineering group,you'llcontribute tofirmware that directlyimpactsthe performance and reliability of Ethernet connectivity solutions powering AI infrastructure globally. Working closely with the SoC software, transceiver module software, and system validation teams,you'lltake ownership of feature development and rollout, software integration testing, and customer debug activities. Working at the intersection of embedded systems and high-speed Ethernet connectivity,you'llcollaborate closely to bring these systems to production. We'rea startup, and this role reflects that reality.You'llhave responsibilities spanning firmware development, customer engagement,debugand validation support, and cross-functional coordination.We'relooking for someone who thrives wearing multiple hats and is energized by jumping into whatever needs doing. We recognize this breadth and reward it accordingly. This position offers strong mentorship opportunities as you work alongside experienced engineers and help bring products from development through customer deployment. Level is negotiable based on experience and qualifications. Location This is an on-site position based in our San Jose, CA office. Core Responsibilities Firmware Development Debug Develop andmaintainembedded firmware for Ethernetretimersand gearboxes, from low-level hardware abstraction through customer-facing APIs Drive Layer 1 PHY and SERDES debug activities, including link bring-up issues, signal integrity problems, and interoperability failures Support complex IP integration efforts across multiple subsystems within the SoC Implement andoptimizelink training sequences, equalization tuning, and diagnostic features Assistwith software quality gates and validation criteria at each development phase Product Rollout Customer Integration Partner with the softwareleadto drive product rollout activities from development through production deployment Support customer integration efforts through firmware customization, debugassistance, and technical guidance Investigate field-reported issues and coordinate resolution with internal teams Develop andmaintainSDK/API interfaces that enable customer platform integration Cross-Functional Collaboration Work extensively with digital SoC teams to understand hardware behavior, register interfaces, and IP integration requirements Collaborate with field applications engineers to support customer bring-up and resolve deployment issues Partner with platform applications teams to ensure firmware meets system-level requirements Work alongside silicon and system validation teams to develop test plans, automate characterization flows, and verify firmware behavior across corner cases Provide regular project updates on progress, risks, dependencies, and technical challenges What You Bring Required Qualifications: BS/MS in Computer Science, Electrical Engineering, Computer Engineering, or related field 10+ years of embedded C/C++ firmware development in resource-constrained environments Deep understanding of microcontroller architecture, memory-mapped peripherals,interrupthandling, and bare-metal firmware design Experience with Layer 1 PHY firmware, SERDES bring-up, or SDK/API development for networking devices Strongproficiencywith Linux development tools:gcc/clang, make, bash scripting,gdb, and git Excellent verbal and written communication skills; ability to explain complex technical concepts clearly Demonstrated problem-solving ability and systematic debugging approach on real hardware Comfort with ambiguity and a willingness to take on whatever challenges arise in a fast-moving startup environment Highly Valued Skills: Experience with PMA, FEC, or related PHY-layer subsystems beyond the PMD/SERDES Familiarity with NIC or switch management software, for system test purposes Exposure to SAI (Switch Abstraction Interface) orOpenBMC Experience with Python for test automation, data analysis, or general scripting Hands-on experience building andmaintainingJenkins CI/CD pipelines and automated test infrastructure Background inretimeror gearbox firmware/API, active electrical cables, or high-speed Ethernet connectivity Experience with lab equipment: oscilloscopes, power supplies, logic analyzers, BERT, Viavi/Lecroy/Exfo/Keysight/Tektronix or similar Understanding of signal integrity concepts: equalization, channel loss, jitter, eye diagrams, and link margin Familiarity with FPGA emulation, pre-silicon validation, or hardware simulation environments Experience with RTOS, device drivers, or coroutines Prior technical lead, mentorship, or team lead experience Compensation Salary range is $185,000 USD - $203,000 USD depending on experience, level, and business need. This role will include a discretionary bonus, competitive equity package, comprehensive health/dental/vision coverage, professional development opportunities, and a culture that values technical excellence, collaboration, and innovation.We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.