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Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 8 years of experience with digital logic design principles, RTL design concepts, and languages, such as Verilog or SystemVerilog. 8 years of experience with multiple IPs/SoCs with silicon success. Experience with logic synthesis techniques to optimize RTL code, performance and power, as well as low-power design techniques. Preferred qualifications: Master's or PhD degree in Electrical Engineering, Computer Engineering or Computer Science. Experience with a scripting language like Perl or Python. Experience with ASIC or FPGA design verification, synthesis, timing/power analysis, and DFT. Knowledge of high-performance and low-power design techniques, assertion-based formal verification, FPGA and emulation platforms, and SOC architecture. Knowledge of memory compression, fabric, coherence, cache, or DRAM. About the jobBe part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.Responsibilities Define the block-level design document (e.g., interface protocol, block diagram, transaction flow, pipeline, etc.). Perform RTL coding, function/performance simulation debug, and Lint/Clock Domain Crossing (CDC)/Formal Verification (FV)/Unified Power Format (UPF) checks. Participate in synthesis, timing/power closure, and FPGA/silicon bring-up. Participate in test plan and coverage analysis of the block and ASIC-level verification. Communicate and work with multi-disciplined and multi-site teams. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.

Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 8 years of experience with digital logic design principles, RTL design concepts, and languages, such as Verilog or SystemVerilog. Experience with logic synthesis techniques to optimize RTL code, performance and power, as well as low-power design techniques. Preferred qualifications: Master's or PhD degree in Electrical Engineering, Computer Engineering or Computer Science. Experience with a scripting language like Perl or Python. Experience with ASIC or FPGA design verification, synthesis, timing/power analysis, and DFT. Knowledge of high-performance and low-power design techniques, assertion-based formal verification, FPGA and emulation platforms, and SOC architecture. Knowledge of memory compression, fabric, coherence, cache, or DRAM. About the jobBe part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.The Platforms and Devices team encompasses Google's various computing software platforms across environments (desktop, mobile, applications), as well as our first party devices and services that combine the best of Google AI, software, and hardware. Teams across this area research, design, and develop new technologies to make our user's interaction with computing faster and more seamless, building innovative experiences for our users around the world.Responsibilities Set technical direction for the team within the capacity of technical lead and people manager. Engage with Machine Learning System Architects and Software teams to define specifications and implement digital logic using Chisel, Verilog, and/or SystemVerilog. Engage with Verification and Silicon Validation teams to ensure functionality of the design. Perform power, area, and performance trade-offs of digital designs and architectures. Apply engineering best practices (e.g., code review, testing, refactoring) to the design and implementation of ASIC blocks. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.

Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. 4 years of experience with digital logic design principles, RTL design concepts, and languages, such as Verilog or SystemVerilog. Experience with logic synthesis techniques to optimize RTL code, performance and power, as well as low-power design techniques. Preferred qualifications: Master's or PhD degree in Electrical Engineering, Computer Engineering, or Computer Science. Experience with a scripting language like Perl or Python. Experience with ASIC or FPGA design verification, synthesis, timing/power analysis, and DFT. Knowledge of high-performance and low-power design techniques, assertion-based formal verification, FPGA and emulation platforms, and SOC architecture. Knowledge of memory compression, fabric, coherence, cache, or DRAM. About the jobBe part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. In this role, you will be a part of the team which designs the SoC and Subsystem. You will be working through all phases of design and implementation. You will be working with architects to come up with microarchitecture specifications. You will use your logic design skills to convert the micro-arch into System Verilog code. You will be involved in Power, Performance and Area (PPA) experiments/prototyping experiments early on to optimize PPA. You will also work closely with the verification team to verify the features implemented in design. You will also work with the Physical Design (PD) team to take the design through the PD cycle and eventual tape-out.The Platforms and Devices team encompasses Google's various computing software platforms across environments (desktop, mobile, applications), as well as our first party devices and services that combine the best of Google AI, software, and hardware. Teams across this area research, design, and develop new technologies to make our user's interaction with computing faster and more seamless, building innovative experiences for our users around the world.Responsibilities Define the block-level design document (e.g., interface protocol, block diagram, transaction flow, pipeline, etc.). Perform RTL coding, function/performance simulation debug, and Lint/CDC/FV/UPF checks. Participate in test plan and coverage analysis of the block and ASIC-level verification. Communicate and work with multi-disciplined and multi-site teams. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.

Logitech is the Sweet Spot for people who want their actions to have a positive global impact while having the flexibility to do it in their own way.The Role:We are expanding our Test Automation team in Chennai to support and contributeto the development, maintenance, and improvement of our automation frameworks especially with FPGA for our Test fixtures. This position is ideal for someone with a strong technical foundation and a desire to grow into a specialist in test automation for embedded systems and consumer electronics.Your Contribution:In this role you will:● Support the deployment, maintenance, and improvement of Python-based Test Frameworks.● Contribute to the development and execution of automated test scripts using Python.● Participate in manual and automated testing methodologies.● Understand and follow detailed test plans and procedures to validate products.● Add/Modify FW Modules in Xilinx based FPGA Boards.● Perform basic debugging and troubleshooting.● Document test procedures, results, and contribute to user-friendly tool documentation.● Collaborate with validation engineers to ensure test coverage and product quality.● Learn and apply best practices in test design, automation, and quality assurance.Key Qualifications:For consideration, you must bring the following minimum skills and behaviors to our team:● 6–10 years of experience in software testing, automation, or embedded systems validation.● Solid knowledge of Python programming.● Interest in embedded systems testing and automation tools.● Exposure to manual and automated testing methodologies.● Ability to understand and execute detailed test plans and procedures.● Knowledge of electronics engineering fundamentals.● Hands-on assembly and wiring of electronic test benches, including integration of sensors,connectors, and harnesses.● Debugging and troubleshooting of electronic circuits, signal integrity, and connectivity issues.● Proficiency with lab equipment: oscilloscopes, USB analysers, power supplies, voltmeters, etc.● Familiarity with communication protocols such as UART,USB, Ethernet, Bluetooth.● Strong problem-solving and analytical skills.● Good verbal and written communication skills in English.● A team player with a willingness to learn and take guidance from senior engineers.In addition, preferable certification/skills include:● Xilinx Certified VHDL and Verilog Designer● ISTQB or equivalent certificationEducation:● Bachelor’s Degree in ECE/EEEAcross Logitech we empower collaboration and foster play. We help teams collaborate/learn from anywhere, without compromising on productivity or continuity so it should be no surprise that most of our jobs are open to work from home from most locations. Our hybrid work model allows some employees to work remotely while others work on-premises. Within this structure, you may have teams or departments split between working remotely and working in-house.Logitech is an amazing place to work because it is full of authentic people who are inclusive by nature as well as by design. Being a global company, we value our diversity and celebrate all our differences. Don’t meet every single requirement? Not a problem. If you feel you are the right candidate for the opportunity, we strongly recommend that you apply. We want to meet you!We offer comprehensive and competitive benefits packages and working environments that are designed to be flexible and help you to care for yourself and your loved ones, now and in the future. We believe that good health means more than getting medical care when you need it. Logitech supports a culture that encourages individuals to achieve good physical, financial, emotional, intellectual and social wellbeing so we all can create, achieve and enjoy more and support our families. We can’t wait to tell you more about them being that there are too many to list here and they vary based on location.All qualified applicants will receive consideration for employment without regard to race, sex, age, color, religion, sexual orientation, gender identity, national origin, protected veteran status, or on the basis of disability.If you require an accommodation to complete any part of the application process, are limited in the ability, are unable to access or use this online application process and need an alternative method for applying, you may contact us toll free at 1-510-713-4866 for assistance and we will get back to you as soon as possible.