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Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 8 years of experience with digital logic design principles, RTL design concepts, and languages, such as Verilog or SystemVerilog. 8 years of experience with multiple IPs/SoCs with silicon success. Experience with logic synthesis techniques to optimize RTL code, performance and power, as well as low-power design techniques. Preferred qualifications: Master's or PhD degree in Electrical Engineering, Computer Engineering or Computer Science. Experience with a scripting language like Perl or Python. Experience with ASIC or FPGA design verification, synthesis, timing/power analysis, and DFT. Knowledge of high-performance and low-power design techniques, assertion-based formal verification, FPGA and emulation platforms, and SOC architecture. Knowledge of memory compression, fabric, coherence, cache, or DRAM. About the jobBe part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.Responsibilities Define the block-level design document (e.g., interface protocol, block diagram, transaction flow, pipeline, etc.). Perform RTL coding, function/performance simulation debug, and Lint/Clock Domain Crossing (CDC)/Formal Verification (FV)/Unified Power Format (UPF) checks. Participate in synthesis, timing/power closure, and FPGA/silicon bring-up. Participate in test plan and coverage analysis of the block and ASIC-level verification. Communicate and work with multi-disciplined and multi-site teams. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.

Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 4 years of experience with digital logic design principles, RTL design concepts, and languages, such as Verilog or SystemVerilog. Experience with logic synthesis techniques to optimize RTL code, performance and power, as well as low-power design techniques. Preferred qualifications: Master's or PhD degree in Electrical Engineering, Computer Engineering, or Computer Science. Experience with a scripting language like Perl or Python. Experience with ASIC or FPGA design verification, synthesis, timing/power analysis, and DFT. Knowledge of high-performance and low-power design techniques, assertion-based formal verification, FPGA and emulation platforms, and SOC architecture. Knowledge of memory compression, fabric, coherence, cache, or Dynamic Random Access Memory (DRAM). About the jobBe part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. In this role, you will be creating the micro-architecture and design of the critical IPs widely used across multiple mobile SOC's subsystems and running extensive quality checks including Lint, Clock Domain Crossing (CDC), low power checks (VCLP), synthesis, and timing and power analysis. You should be able to timely deliver IPs and work with various cross-functional teams (DV/DFT/PD/power) to ensure quality.The Platforms and Devices team encompasses Google's various computing software platforms across environments (desktop, mobile, applications), as well as our first party devices and services that combine the best of Google AI, software, and hardware. Teams across this area research, design, and develop new technologies to make our user's interaction with computing faster and more seamless, building innovative experiences for our users around the world.Responsibilities Define the block-level design document (e.g., interface protocol, block diagram, transaction flow, pipeline, etc.). Perform Register-Transfer Level (RTL) coding, function/performance simulation debug, and Lint/CDC/FV/UPF checks. Participate in synthesis, timing/power closure, and Field Programmable Gate Array (FPGA)/silicon bring-up. Participate in test plan and coverage analysis of the block and Application Specific Integrated Circuit (ASIC) level verification. Communicate and work with multi-disciplined and multi-site teams. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.

Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 4 years of experience with digital logic design principles, RTL design concepts, and languages, such as Verilog or SystemVerilog. Experience with logic synthesis techniques to optimize RTL code, performance and power, as well as low-power design techniques. Preferred qualifications: Master's or PhD degree in Electrical Engineering, Computer Engineering, or Computer Science. Experience with a scripting language like Perl or Python. Experience with ASIC or FPGA design verification, synthesis, timing/power analysis, and DFT. Knowledge of high-performance and low-power design techniques, assertion-based formal verification, FPGA and emulation platforms, and SOC architecture. Knowledge of memory compression, fabric, coherence, cache, or DRAM. About the jobBe part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. In this role you will contribute in creating the micro-architecture of the mobile SOC's subsystems, integrating multiple first-party/ third-party components, and running extensive quality checks including Lint, Clock Domain Crossing (CDC), low power checks (VCLP), synthesis, and timing and power analysis. You will be able to timely deliver Subsystems and work with various cross-functional teams ( DV/DFT/PD/Power) to ensure quality. The Platforms and Devices team encompasses Google's various computing software platforms across environments (desktop, mobile, applications), as well as our first party devices and services that combine the best of Google AI, software, and hardware. Teams across this area research, design, and develop new technologies to make our user's interaction with computing faster and more seamless, building innovative experiences for our users around the world.Responsibilities Define the block-level design document (e.g., interface protocol, block diagram, transaction flow, pipeline, etc.). Perform RTL coding, function/performance simulation debug, and Lint/Cyber Defense Center (CDC)/Formal Verification (FV)/Unified Power Format (UPF) checks. Participate in synthesis, timing/power closure, and FPGA/silicon bring-up. Participate in test plan and coverage analysis of the block and ASIC-level verification. Communicate and work with multi-disciplined and multi-site teams. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.

Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 8 years of experience with digital logic design principles, RTL design concepts, and languages, such as Verilog or SystemVerilog. Experience with logic synthesis techniques to optimize RTL code, performance and power, as well as low-power design techniques. Preferred qualifications: Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, or a related field. Experience with a scripting language like Perl or Python. Experience with ASIC or FPGA design verification, synthesis, timing/power analysis, and DFT. Experience in one or more functional areas, such as coherent fabrics (e.g., AMBA CHI/AXI), memory controllers (e.g., LPDDR5, DDR5), or I/O controllers (e.g., PCIe, CXL). Experience with design sign-off and quality tools (e.g., Lint, CDC, etc.). Knowledge of memory compression, fabric, coherence, cache, or DRAM. About the jobBe part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.Responsibilities Perform RTL coding, function/performance simulation debug, and Lint/Clock Domain Crossing (CDC)/Formal Verification (FV)/Unified Power Format (UPF) checks. Participate in synthesis, timing/power closure, and FPGA/silicon bring-up. Own and execute the RTL design and micro-architecture for high-performance Fabrics and Network-on-Chip (NoC) subsystems from concept to tape-out. Write production-quality SystemVerilog code for complex logic including credit-based flow control, asynchronous bridges, and cache coherency controllers. Debug complex silicon issues and architectural bugs by digging into waveforms and gate-level simulations. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.

Logitech is the Sweet Spot for people who want their actions to have a positive global impact while having the flexibility to do it in their own way.The Role:We are expanding our Test Automation team in Chennai to support and contributeto the development, maintenance, and improvement of our automation frameworks especially with FPGA for our Test fixtures. This position is ideal for someone with a strong technical foundation and a desire to grow into a specialist in test automation for embedded systems and consumer electronics.Your Contribution:In this role you will:● Support the deployment, maintenance, and improvement of Python-based Test Frameworks.● Contribute to the development and execution of automated test scripts using Python.● Participate in manual and automated testing methodologies.● Understand and follow detailed test plans and procedures to validate products.● Add/Modify FW Modules in Xilinx based FPGA Boards.● Perform basic debugging and troubleshooting.● Document test procedures, results, and contribute to user-friendly tool documentation.● Collaborate with validation engineers to ensure test coverage and product quality.● Learn and apply best practices in test design, automation, and quality assurance.Key Qualifications:For consideration, you must bring the following minimum skills and behaviors to our team:● 6–10 years of experience in software testing, automation, or embedded systems validation.● Solid knowledge of Python programming.● Interest in embedded systems testing and automation tools.● Exposure to manual and automated testing methodologies.● Ability to understand and execute detailed test plans and procedures.● Knowledge of electronics engineering fundamentals.● Hands-on assembly and wiring of electronic test benches, including integration of sensors,connectors, and harnesses.● Debugging and troubleshooting of electronic circuits, signal integrity, and connectivity issues.● Proficiency with lab equipment: oscilloscopes, USB analysers, power supplies, voltmeters, etc.● Familiarity with communication protocols such as UART,USB, Ethernet, Bluetooth.● Strong problem-solving and analytical skills.● Good verbal and written communication skills in English.● A team player with a willingness to learn and take guidance from senior engineers.In addition, preferable certification/skills include:● Xilinx Certified VHDL and Verilog Designer● ISTQB or equivalent certificationEducation:● Bachelor’s Degree in ECE/EEEAcross Logitech we empower collaboration and foster play. We help teams collaborate/learn from anywhere, without compromising on productivity or continuity so it should be no surprise that most of our jobs are open to work from home from most locations. Our hybrid work model allows some employees to work remotely while others work on-premises. Within this structure, you may have teams or departments split between working remotely and working in-house.Logitech is an amazing place to work because it is full of authentic people who are inclusive by nature as well as by design. Being a global company, we value our diversity and celebrate all our differences. Don’t meet every single requirement? Not a problem. If you feel you are the right candidate for the opportunity, we strongly recommend that you apply. We want to meet you!We offer comprehensive and competitive benefits packages and working environments that are designed to be flexible and help you to care for yourself and your loved ones, now and in the future. We believe that good health means more than getting medical care when you need it. Logitech supports a culture that encourages individuals to achieve good physical, financial, emotional, intellectual and social wellbeing so we all can create, achieve and enjoy more and support our families. We can’t wait to tell you more about them being that there are too many to list here and they vary based on location.All qualified applicants will receive consideration for employment without regard to race, sex, age, color, religion, sexual orientation, gender identity, national origin, protected veteran status, or on the basis of disability.If you require an accommodation to complete any part of the application process, are limited in the ability, are unable to access or use this online application process and need an alternative method for applying, you may contact us toll free at 1-510-713-4866 for assistance and we will get back to you as soon as possible.

Please complete your application before July 31, 2026.Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Bengaluru, Karnataka, India; Hyderabad, Telangana, India.Minimum qualifications: Currently pursuing a PhD degree in Computer Engineering, Computer Science, Electronics and Communication Engineering, Electrical Engineering, or a related technical field Experience in programming languages (e.g., C++, Python, Verilog, UVM), Synopsys and Cadence tools Experience in one or more of the following areas: hardware system integration, product design, computer architecture, digital design verification, digital circuits, ASIC physical design, FPGAs, embedded systems, memory systems Preferred qualifications: Experience with performance modeling tools, C++, Python or silicon design tools in front end/design verification/physical design Knowledge of arithmetic units, bus architectures, accelerators or memory hierarchies; computer architecture; linear algebra; or ML/DL background Knowledge of high performance and low power design techniques Currently attending a degree program in India and available to work full time for 12 weeks outside of university term time About the jobAs a Silicon Engineering Intern, you will work in a team that is shaping the future of Google Cloud Silicon, including TPUs, arm-based servers, and network products. You will collaborate with hardware and software architects and designers to architect, model, analyze, define, and design next-generation Cloud Silicon. You will have dynamic, multi-faceted responsibilities in areas such as product definition, design and implementation, collaborating with the Engineering teams to drive the optimal balance between performance, power, features, schedule, and cost.The ML, Systems, and Cloud AI (MSCA) organization at Google designs, implements and manages the hardware, software, machine learning and systems infrastructure for all Google services (e.g., Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers, and people who use Google services around the world. We prioritize security, efficiency, and reliability across everything we do - from developing our latest Cloud Silicon products to running a global network, while driving towards shaping the future of hyperscale computing. Google is and always will be an engineering company. We hire people with a broad set of technical skills who are ready to address some of technology's greatest challenges and make an impact on millions, if not billions, of users. At Google, engineers not only revolutionize search, they routinely work on massive scalability and storage solutions, large-scale applications and entirely new platforms for developers around the world. From Google Ads to Chrome, Android to YouTube, Social to Local, Google engineers are changing the world one technological achievement after another.Responsibilities Responsibilities may vary based on specific teams. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.

Minimum qualifications: Bachelor's degree in Electrical Engineering or equivalent practical experience. 4 years of experience in Verification, verifying digital logic at RTL level using SystemVerilog or Specman/E for Field Programmable Gate Arrays (FPGAs) or ASICs. Experience in verification and debug of Internet Protocol (IP)/subsystem/SoCs in the Networking domain such as packet processing, bandwidth management and congestion control. Experience verifying digital systems using standard IP components/interconnects (e.g., microprocessor cores, hierarchical memory subsystems). Preferred qualifications: Master's degree in Electrical Engineering or a related field. Experience with industry-standard simulators, revision control systems, and regression systems. Experience in Artificial Intelligence/Machine Learning (AI/ML) Accelerators or vector processing units. Experience with the full verification life cycle. Excellent problem-solving and communication skills. About the jobIn this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. In this role, you will own the full verification life-cycle from verification planning and test execution to coverage closure, with an emphasis on meeting stringent AI/ML performance and accuracy goals, build constrained-random verification environments capable of exposing corner-case bugs and ensuring the reliability of Artificial Intelligence/Machine Learning (AI/ML) workloads on Tensor Processing Unit (TPU) hardware. You will collaborate closely with design and verification engineers in active projects and perform verification.The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide. We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.Responsibilities Plan the verification of digital design blocks and interact with design engineers to identify important verification scenarios. Identify and write all types of coverage measures for stimulus and corner-cases. Debug tests with design engineers to deliver functionally correct design blocks. Measure to identify verification holes and to show progress towards tape-out. Create a constrained-random verification environment using SystemVerilog and Universal Verification Methodology (UVM). Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.

Minimum qualifications: Bachelor's degree in business, finance, economics, statistics, or another quantitative field, or equivalent practical experience. 4 years of experience in financial planning and analysis (FPA), consulting, or a related function, or an advanced degree. Experience executing full-cycle FPA functions including budgeting, forecasting, variance analysis, and modeling within a multinational company setting. Preferred qualifications: Experience leading cross-functional project teams through strong problem-framing and problem-structuring skills and project management skills. Expertise with SQL and data visualization tools. Ability to communicate insights and narratives to a wide range of stakeholders including financial leadership and technical management teams. Ability to thrive in a fast-paced, dynamic environment. Excellent analytical and quantitative modeling skills. About the jobFinancial Analysts ensure that Google makes sound financial decisions. As a Financial Analyst, your work, whether it's modeling business scenarios or tracking performance metrics, is used by our leaders to make strategic company decisions. While working on multiple projects at a time, you are focused on the details while finding creative ways to solve big picture challenges. In Google Cloud Security finance, our mission is to support our VP/GMs leading the development of Google Cloud’s strategic security portfolio. We partner with an organization whose mission is to develop our security products in order to be a trusted security partner in the AI era. We partner directly with our engineering, product management and product operations organizations who are responsible for developing these products in a competitive market. Google Cloud’s Security products span from prevention to active defense to ensure our customers and partners are secure in the agentic era. We help our partners deliver these critical products while managing profitability from top line to bottom line.Responsibilities Partner with engineering and product leadership to evaluate long-term financial plan, investment strategies, and new technology and product launches. Contribute to financial planning, forecasting, reporting, and allocation processes as well as automate and scale financial processes. Drive actionable analyses and recommendations for investment prioritization, resource optimization and efficiency improvements. Apply strong business judgment to develop a wide variety of reporting, Analytic tools and key performance indicators and to construct a deep understanding of how to optimize infrastructure cost and to guide business decisions. Partner with business and finance stakeholders on overall PL management. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.

Logitech is the Sweet Spot for people who want their actions to have a positive global impact while having the flexibility to do it in their own way.EPM tECH LEAD (OnESTREAM)Information Technology  Guindy, Chennai, Tamil NaduDESCRIPTIONPosition at LogitechThe Role:The Role EPM Tech Lead is responsible for the implementation of financial planning, reporting, consolidation, closing and other process solutions using Onestream software for the stakeholders in finance department. The candidate will lead Onestream solutions through the full cycle of an implementation including requirements, design, testing, development, testing, training, documentation, and support.Your Contribution:Be Yourself. Be Open. Stay Hungry and Humble. Collaborate. Challenge. Decide and just Do. These are the behaviors you’ll need for success at Logitech. In this role you will:·       Lead the stabilization and performance optimization of the OneStream platform, addressing system bottlenecks and improving user experience, especially for Excel-based reporting·       Drive large-scale transition of reporting and planning processes from Essbase to OneStream, ensuring data accuracy, reconciliation, and business continuity·       Work closely with Finance stakeholders (FPA, Accounting, Regional Finance teams) to gather, define, and deliver scalable and sustainable solutions·       Evaluate standard functionality and recommend enhancements to improve financial processes and system efficiency·       Participate in all phases of software development including planning, analysis, design, development, testing, integration, documentation, and training·       Develop and optimize Cube Views, Quick Views, XF reports, business rules, and workflows·       Lead and coordinate testing efforts including unit testing, integration testing, and user acceptance testing·       Build and enhance integrations with upstream and downstream systems·       Support expansion of data models to incorporate additional dimensions as required and enable future reporting and planning capabilities·       Strengthen governance by implementing SOX-compliant controls and best practices across development and deployment processes·       Collaborate with architects, business analysts, and external partners to define and deliver solutions·       Mentor junior team members and provide technical leadership across the OneStream platform·       Support ongoing user enablement, report conversion, and adoption as part of enterprise-wide rolloutKey Qualifications:For consideration, you must bring the following minimum skills and behaviors to our team:·       Minimum of 6–9 years of overall relevant experience with at least 2 years of hands-on experience in full lifecycle OneStream implementations·       Strong experience in designing, developing, and delivering enterprise-scale EPM solutions·       Strong functional knowledge of financial planning, reporting, consolidation, and close processes·       Proven expertise in Cube Views, Quick Views, XF reporting, business rules, workflows, system security, and configurations·       Strong experience in performance tuning, troubleshooting, and optimizing reporting applications·       Experience working with business stakeholders to define and deliver requirements·       Experience in integrating OneStream with other enterprise systems using REST APIs or other methods·       Proficiency in .NET/C# and SQL for developing technical solutions·       Experience with data integration, data transformations, and reconciliation across systems·       Strong understanding of SOX and ITGC controls in financial systems·       Ability to independently manage deliverables and contribute to complex projects·       Strong communication and presentation skills·       Proficiency in Microsoft Office toolsIn addition, preferable skills and behaviors include:·       OneStream Certified Professional (OCP) certification·       Experience with reporting tools such as Tableau and OBIEE·       Familiarity with Oracle ERP and Snowflake data warehouse·       Experience in large-scale EPM transformation or system migration programs·       Exposure to performance optimization and post-go-live stabilization initiatives Education:BS/MS in Computer Science, Information Systems or a related technical field or equivalent industry expertise.Logitech is the sweet spot for people who are passionate about products, making a mark, and having fun doing it. As a company, we’re small and flexible enough for every person to take initiative and make things happen. But we’re big enough in our portfolio, and reach, for those actions to have a global impact. That’s a pretty sweet spot to be in and we’re always striving to keep it that way.Across Logitech we empower collaboration and foster play. We help teams collaborate/learn from anywhere, without compromising on productivity or continuity so it should be no surprise that most of our jobs are open to work from home from most locations. Our hybrid work model allows some employees to work remotely while others work on-premises. Within this structure, you may have teams or departments split between working remotely and working in-house.Logitech is an amazing place to work because it is full of authentic people who are inclusive by nature as well as by design. Being a global company, we value our diversity and celebrate all our differences. Don’t meet every single requirement? Not a problem. If you feel you are the right candidate for the opportunity, we strongly recommend that you apply. We want to meet you!We offer comprehensive and competitive benefits packages and working environments that are designed to be flexible and help you to care for yourself and your loved ones, now and in the future. We believe that good health means more than getting medical care when you need it. Logitech supports a culture that encourages individuals to achieve good physical, financial, emotional, intellectual and social wellbeing so we all can create, achieve and enjoy more and support our families. We can’t wait to tell you more about them being that there are too many to list here and they vary based on location.All qualified applicants will receive consideration for employment without regard to race, sex, age, color, religion, sexual orientation, gender identity, national origin, protected veteran status, or on the basis of disability.If you require an accommodation to complete any part of the application process, are limited in the ability, are unable to access or use this online application process and need an alternative method for applying, you may contact us toll free at 1-510-713-4866 for assistance and we will get back to you as soon as possible.