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Note: This is a mirrored copy of the posting from AMD's Career Page. For the official and most up-to-date listing, please refer to AMD's Career Page.---WHAT YOU DO AT AMD CHANGES EVERYTHINGAt AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. The Role:We are seeking a high-caliber FPGA Design Engineer to develop our next-generation IO-based connectivity systems. drive the design from initial concept through to hardware validation.Key Responsibilities: - System Architecture Implementation: Lead the design, documentation, and implementation of complex IO-based connectivity systems, ensuring high-speed data integrity and system reliability. - Front-End Methodology Leadership: Drive advanced RTL design flows, including resource optimization (Area/Power), multi-clock domain crossing (CDC) analysis, and reset domain crossing (RDC) strategies. - Technical Documentation Lifecycle Management: Synthesize comprehensive Requirement Specifications, Design Specs, and Test Plans. You will ensure these documents account for complex interactions between hardware, firmware, and software drivers. - Cross-Functional Collaboration: Partner closely with Architects, Hardware Engineers, and Firmware teams to define feature sets, negotiate interfaces, and ensure seamless system integration.Required Technical Qualifications: - Xilinx Expertise: Minimum of 6 years of hands-on experience in RTL design with a deep-seated understanding of AMD-Xilinx UltraScale+ FPGA architectures. - Toolchain Proficiency: Expert-level command of the Vivado Design Suite (Synthesis, Implementation, and Timing Closure). - System-Level Architecture: Proven track record with high-speed bus protocols (AXI4/AXI-Stream), memory controllers, and interconnect bridges. - High-Speed Connectivity: Direct experience implementing and debugging one or more high-speed protocols: PCIe (Gen3/4/5), 10/25/100G Ethernet, TCP/IP offload engines, or USB 3.x. - Verification Debug: Proficient in RTL simulation (Xcelium, Questa, or Vivado Simulator) and hardware-in-the-loop debugging using Xilinx ChipScope/ILA.Professional Attributes: - Ownership: A self-starting mindset with the ability to navigate ambiguity and independently drive tasks to production-ready completion. - Problem-Solving: Exceptional analytical skills for triaging complex system-level hardware/software bugs. - Communication: Ability to articulate technical trade-offs to both technical and non-technical stakeholders.Academic Credentials: - Bachelor’s or Master’s degree in electrical/computer engineering or related field preferred.Location:Taipei Taiwan#LI-VJ1 Benefits offered are described: AMD benefits at a glance.AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.This posting is for an existing vacancy.

Note: This is a mirrored copy of the posting from AMD's Career Page. For the official and most up-to-date listing, please refer to AMD's Career Page.---WHAT YOU DO AT AMD CHANGES EVERYTHINGAt AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. The Role:We are seeking a high-caliber FPGA Design Engineer to develop our next-generation IO-based connectivity systems. drive the design from initial concept through to hardware validation.Key Responsibilities: - System Architecture Implementation: Lead the design, documentation, and implementation of complex IO-based connectivity systems, ensuring high-speed data integrity and system reliability. - Front-End Methodology Leadership: Drive advanced RTL design flows, including resource optimization (Area/Power), multi-clock domain crossing (CDC) analysis, and reset domain crossing (RDC) strategies. - Technical Documentation Lifecycle Management: Synthesize comprehensive Requirement Specifications, Design Specs, and Test Plans. You will ensure these documents account for complex interactions between hardware, firmware, and software drivers. - Cross-Functional Collaboration: Partner closely with Architects, Hardware Engineers, and Firmware teams to define feature sets, negotiate interfaces, and ensure seamless system integration.Required Technical Qualifications: - Xilinx Expertise: Minimum of 6 years of hands-on experience in RTL design with a deep-seated understanding of AMD-Xilinx UltraScale+ FPGA architectures. - Toolchain Proficiency: Expert-level command of the Vivado Design Suite (Synthesis, Implementation, and Timing Closure). - System-Level Architecture: Proven track record with high-speed bus protocols (AXI4/AXI-Stream), memory controllers, and interconnect bridges. - High-Speed Connectivity: Direct experience implementing and debugging one or more high-speed protocols: PCIe (Gen3/4/5), 10/25/100G Ethernet, TCP/IP offload engines, or USB 3.x. - Verification Debug: Proficient in RTL simulation (Xcelium, Questa, or Vivado Simulator) and hardware-in-the-loop debugging using Xilinx ChipScope/ILA.Professional Attributes: - Ownership: A self-starting mindset with the ability to navigate ambiguity and independently drive tasks to production-ready completion. - Problem-Solving: Exceptional analytical skills for triaging complex system-level hardware/software bugs. - Communication: Ability to articulate technical trade-offs to both technical and non-technical stakeholders.Academic Credentials: - Bachelor’s or Master’s degree in electrical/computer engineering or related field preferred.Location:Taipei Taiwan#LI-VJ1 Benefits offered are described: AMD benefits at a glance.AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.This posting is for an existing vacancy.

Note: This is a mirrored copy of the posting from AMD's Career Page. For the official and most up-to-date listing, please refer to AMD's Career Page.---WHAT YOU DO AT AMD CHANGES EVERYTHINGAt AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE:As a Power Engineer in the ODM Enablement, Data Center Platform Engineering (DPEG), you will be responsible to work with ODM/OEM/Customer for the Power Design and validation for the AMD Data Center GPU products in this expanding and strategic market for AMD. To accomplish this, you will need to interact with other key engineering teams such as silicon design, boarding engineering, power delivery, validation, and manufacturing within AMD. Collaborate closely with Architecture, Hardware, Thermal, SI/PI, and Layout experts to deliver robust designs. You’ll own supporting ODM/customer on the full product lifecycle – from simulation and schematic design to hands-on lab validation and debugging – ensuring power integrity meets rigorous performance standards. Here, you’ll constantly push boundaries in to support customer on power efficiency, work with advanced tools, solve complex technical puzzles, and systems validation that shape the future of computing.THE PERSON:We are seeking a talentedPlatform Power Design Engineerto join us, supporting ODM/OEM/Customer focusing on the development of cutting-edge DC-DC power delivery solutions for next-generation Server motherboard and Rack System Power. Solving tough technical challenges. A natural problem-solver, meticulous in validation and debugging but also think big-picture to optimize system-level performance. KEY RESPONSIBILITIES: - Work with ODM/OEM/Customer on Design review, simulate, verification and optimize high-efficiency DC-DC power solutions (e.g., multi-phase buck converters, VRMs) for battery life and high-performance CPU/GPU platforms. - Review customer schematic, PCB layout reviews, and component selection to meet power delivery requirement (e.g., voltage ripple, transient response, efficiency etc.). - Collaborate with cross-functional teams (Arch, EE, thermal, layout, SI/PI etc.) to provide motherboard reference board and server Rack power shelf requirement on time. - Conduct PDN(power delivery network) simulation and analysis, ensure power integrity - Co-work with multiple stakeholders to ensure signal integrity and thermal compliance for motherboard and System power. - Validate and debug power solution in the lab using oscilloscopes, e-loads etc. - Document test reports, design spec, and best practices for power solution. - Stay updated on industry trends in power electronics, energy-efficient technologies.PREFERRED EXPERIENCE: - Proficiency in Server or Data center rack, including power shelf technology, battery management, charger, deeply understand EC/BIOS/ACPI - Proficiency in DC-DC converter topologies (buck, boost, multiphase), PWM controllers, MOSFET, and power stage. - Experience with simulation tools (e.g., Simplis, SPICE, PowerDC, Ansys SIWave). - Strong knowledge of PCB layout considerations for power circuits (e.g., parasitic reduction). - PDN and PI analysis capability - Familiarity with lab equipment: oscilloscopes, spectrum analyzers, and power integrity test setups. - Knowledge of EMI/EMC mitigation techniques in power designs. - Familiarity with x86 system power management feature. - Familiarity with thermal management solutions for high-power-density systems. - Exposure to MCU-based, FPGA-based prototyping or scripting (Python, MATLAB, LabVIEW) for automation. - Good English communication - Problem-solving mindset, teamwork.ACADEMIC CREDENTIALS: - BS or above in Electrical/Electronic/Power Engineering, or related field - 5+ years of hands-on experience in power hardware design, preferably for high-speed computing platforms (e.g., CPUs, GPUs, ASICs).#LI-IH1 Benefits offered are described: AMD benefits at a glance.AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.This posting is for an existing vacancy.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com. Astera Labs is seeking highly motivated Interns to join the Sales team in the TW team. If you are: A Junior going into Senior year or Senior graduating by the end of this year Have strong academics and technical background in Electrical Engineering Someone with a professional attitude, ability to prioritize a dynamic list of multiple tasks and work with minimal guidance and supervision Strong in analytical skills, self-motivated and a challenge taker What we are looking for: Develop regional sales analysis and planning materials by identifying market segments, opportunity sizing, and internal execution strategies Support sales initiatives by partnering closely with FAEs and internal stakeholders to prepare product information, roadmap materials, technology training content, and internal documentation Consolidate and analyze input from internal teams to support product planning, roadmap alignment, and internal issue tracking Coordinate cross-functional information flow among sales, operations, and supply-related teams to support quarterly revenue planning and mid-term demand projections Assist in market and ecosystem research across CPU, GPU, FPGA, Networking, Memory, and BMC segments to identify co-development and strategic opportunity areas If the above position excites you, we would love to hear from you. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com. Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions grounded in open standards. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. Discover more atwww.asteralabs.com. Job Description: As member of Astera Labs Hardware Engineering team you will be responsible for building diagnostics and manufacturing software to allow design, test, and manufacture cutting edge high speed datacenter products. You will be working on project from conception to the final production stage at contract manufacturer. The role requires strong and broad software background and good understanding of hardware design and manufacturing practices. At the same time we welcome candidates with deep experience in smaller areas and desire to learn. Depending on your experience you may be focusing on design/validation or automation/manufacturing. Key Responsibilities Design, implement test production-grade diagnostics for high-speed digital boards and ASICS to help with hardware validation. Design, implement test manufacturing tests to validate mass production of digital boards used in data center networking product Bring-up newly manufactured boards. Isolate and perform root-cause analysis of reported failures Support new platform software and hardware features Coordinate with the hardware engineering team on bring-up schedules and feature delivery Participate proactively in design discussions, design review, and project management Work independently as well as in team roles, mentor younger team members Business travel to China will be required as needed Basic Qualifications/Required Experience Bachelor’s in CS/CE or equivalent experience. 2+ years of Experience in subset of diag, hardware bring-up, test or manufacturing automation Knowledge of modern software development Proficiency in Python Preferred experience Experience working with datacenter-level complex electronic equipment bring-up/diagnostic/manufacturing Ability to read schematic/layout System debug experience Embedded programming and good knowledge of OS internals (Linux/Unix) Has knowledge of common inter connecting buses and interfaces such as PCIe, I2C, XAUI, 10G Ethernet drivers, FPGA, Switch chips, SSL offload, TCAM programming. Experience with DDR5 We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.