Tìm kiếm việc làm online mới nhất!

Req ID: 130622Remote Position: NoRegion: AsiaCountry: TaiwanState/Province: TaiwanCity: TaipeiGeneral OverviewFunctional Area: Engineering Career Stream: Design Engineering Hardware IC/MGR: Individual Contributor Direct/Indirect Indicator: Indirect SummaryThe Senior Staff Engi

Req ID: 135773Remote Position: NoRegion: AsiaCountry: ThailandState/Province: ChonburiCity: Laem ChabangGeneral OverviewFunctional Area:Engineering Career Stream: Design - Software EngineeringSAP Short Name:ENG-ENG-DSEJob Level:Level 07IC/MGR: Individual Contributor Direct/Indi

Note: This is a mirrored copy of the posting from AMD's Career Page. For the official and most up-to-date listing, please refer to AMD's Career Page.---WHAT YOU DO AT AMD CHANGES EVERYTHINGAt AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. The Role:We are seeking a high-caliber FPGA Design Engineer to develop our next-generation IO-based connectivity systems. drive the design from initial concept through to hardware validation.Key Responsibilities: - System Architecture Implementation: Lead the design, documentation, and implementation of complex IO-based connectivity systems, ensuring high-speed data integrity and system reliability. - Front-End Methodology Leadership: Drive advanced RTL design flows, including resource optimization (Area/Power), multi-clock domain crossing (CDC) analysis, and reset domain crossing (RDC) strategies. - Technical Documentation Lifecycle Management: Synthesize comprehensive Requirement Specifications, Design Specs, and Test Plans. You will ensure these documents account for complex interactions between hardware, firmware, and software drivers. - Cross-Functional Collaboration: Partner closely with Architects, Hardware Engineers, and Firmware teams to define feature sets, negotiate interfaces, and ensure seamless system integration.Required Technical Qualifications: - Xilinx Expertise: Minimum of 6 years of hands-on experience in RTL design with a deep-seated understanding of AMD-Xilinx UltraScale+ FPGA architectures. - Toolchain Proficiency: Expert-level command of the Vivado Design Suite (Synthesis, Implementation, and Timing Closure). - System-Level Architecture: Proven track record with high-speed bus protocols (AXI4/AXI-Stream), memory controllers, and interconnect bridges. - High-Speed Connectivity: Direct experience implementing and debugging one or more high-speed protocols: PCIe (Gen3/4/5), 10/25/100G Ethernet, TCP/IP offload engines, or USB 3.x. - Verification Debug: Proficient in RTL simulation (Xcelium, Questa, or Vivado Simulator) and hardware-in-the-loop debugging using Xilinx ChipScope/ILA.Professional Attributes: - Ownership: A self-starting mindset with the ability to navigate ambiguity and independently drive tasks to production-ready completion. - Problem-Solving: Exceptional analytical skills for triaging complex system-level hardware/software bugs. - Communication: Ability to articulate technical trade-offs to both technical and non-technical stakeholders.Academic Credentials: - Bachelor’s or Master’s degree in electrical/computer engineering or related field preferred.Location:Taipei Taiwan#LI-VJ1 Benefits offered are described: AMD benefits at a glance.AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.This posting is for an existing vacancy.

Note: This is a mirrored copy of the posting from AMD's Career Page. For the official and most up-to-date listing, please refer to AMD's Career Page.---WHAT YOU DO AT AMD CHANGES EVERYTHINGAt AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. The Role:We are seeking a high-caliber FPGA Design Engineer to develop our next-generation IO-based connectivity systems. drive the design from initial concept through to hardware validation.Key Responsibilities: - System Architecture Implementation: Lead the design, documentation, and implementation of complex IO-based connectivity systems, ensuring high-speed data integrity and system reliability. - Front-End Methodology Leadership: Drive advanced RTL design flows, including resource optimization (Area/Power), multi-clock domain crossing (CDC) analysis, and reset domain crossing (RDC) strategies. - Technical Documentation Lifecycle Management: Synthesize comprehensive Requirement Specifications, Design Specs, and Test Plans. You will ensure these documents account for complex interactions between hardware, firmware, and software drivers. - Cross-Functional Collaboration: Partner closely with Architects, Hardware Engineers, and Firmware teams to define feature sets, negotiate interfaces, and ensure seamless system integration.Required Technical Qualifications: - Xilinx Expertise: Minimum of 6 years of hands-on experience in RTL design with a deep-seated understanding of AMD-Xilinx UltraScale+ FPGA architectures. - Toolchain Proficiency: Expert-level command of the Vivado Design Suite (Synthesis, Implementation, and Timing Closure). - System-Level Architecture: Proven track record with high-speed bus protocols (AXI4/AXI-Stream), memory controllers, and interconnect bridges. - High-Speed Connectivity: Direct experience implementing and debugging one or more high-speed protocols: PCIe (Gen3/4/5), 10/25/100G Ethernet, TCP/IP offload engines, or USB 3.x. - Verification Debug: Proficient in RTL simulation (Xcelium, Questa, or Vivado Simulator) and hardware-in-the-loop debugging using Xilinx ChipScope/ILA.Professional Attributes: - Ownership: A self-starting mindset with the ability to navigate ambiguity and independently drive tasks to production-ready completion. - Problem-Solving: Exceptional analytical skills for triaging complex system-level hardware/software bugs. - Communication: Ability to articulate technical trade-offs to both technical and non-technical stakeholders.Academic Credentials: - Bachelor’s or Master’s degree in electrical/computer engineering or related field preferred.Location:Taipei Taiwan#LI-VJ1 Benefits offered are described: AMD benefits at a glance.AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.This posting is for an existing vacancy.

1. Lidar 精密光機電產品 FPGA開發工程師- 負責開發熱成像模組與設計光達及其他精密光機電產品FPGA數位邏輯電路- 使用Verilog開發LiDAR相關功能與驗證- 根據需求開發IP及功能驗證- 熟悉Lidar、ToF、Radar相關開發經驗佳- 熟悉Thermal camera/RGB camera相關演算法開發經驗佳2. 嵌入式系統開發工程師- 負責熱成像模組或光達及其他精密光機電產品嵌入式系統相關程式開發與驗證- 具備嵌入式系統開發經驗(Linux、RTOS、Bare Metal開發經驗)- 周邊傳輸介面驅動開發經驗(MIPI、VDMA、URAT、SPI、I2C、Ethernet等)- 嵌入式系統平台整合和測試維護- 熟悉LiDAR、ToF、Radar相關開發經驗佳- 熟悉Thermal camera/RGB camera相關演算法開發經驗佳

About the Role: FPT Telecom is building the next generation of Edge AI computing solutions. We are looking for a highly skilled FPGA Engineer with specialized experience in AI Acceleration using AMD/Xilinx Versal ACAP architectures. In this role, you will bridge the gap between AI algorithms and hardware execution, developing high-performance, low-latency, and power-efficient AI accelerators for AI Server. Key Responsibilities: AI Hardware Deployment: Compile and deploy AI models (CNNs, Transformers) from frameworks (PyTorch/TensorFlow) to FPGA/SoC hardware using Vitis AI.AI Engine (AIE) Programming: Design, implement (in C/C++), and optimize parallel computing algorithms onto the AI Engine array of Xilinx Versal devices.Dataflow Optimization: Architect high-throughput data movement between Programmable Logic (PL), Processing System (PS), and AIE using AXI-Stream, DMA, and Network-on-Chip (NoC).System Integration: Collaborate with AI Engineers for model quantization (INT8/FP16) and HW Engineers to integrate custom pre/post-processing blocks (Verilog/HLS) into the system.Verification Profiling: Perform hardware-in-the-loop testing, bottleneck analysis, and profiling using Vitis Analyzer on actual evaluation boards.

ORAN O-RU and gNB PHY 軟體開發

Note: This is a mirrored copy of the posting from AMD's Career Page. For the official and most up-to-date listing, please refer to AMD's Career Page.---WHAT YOU DO AT AMD CHANGES EVERYTHINGAt AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE:As a Power Engineer in the ODM Enablement, Data Center Platform Engineering (DPEG), you will be responsible to work with ODM/OEM/Customer for the Power Design and validation for the AMD Data Center GPU products in this expanding and strategic market for AMD. To accomplish this, you will need to interact with other key engineering teams such as silicon design, boarding engineering, power delivery, validation, and manufacturing within AMD. Collaborate closely with Architecture, Hardware, Thermal, SI/PI, and Layout experts to deliver robust designs. You’ll own supporting ODM/customer on the full product lifecycle – from simulation and schematic design to hands-on lab validation and debugging – ensuring power integrity meets rigorous performance standards. Here, you’ll constantly push boundaries in to support customer on power efficiency, work with advanced tools, solve complex technical puzzles, and systems validation that shape the future of computing.THE PERSON:We are seeking a talentedPlatform Power Design Engineerto join us, supporting ODM/OEM/Customer focusing on the development of cutting-edge DC-DC power delivery solutions for next-generation Server motherboard and Rack System Power. Solving tough technical challenges. A natural problem-solver, meticulous in validation and debugging but also think big-picture to optimize system-level performance. KEY RESPONSIBILITIES: - Work with ODM/OEM/Customer on Design review, simulate, verification and optimize high-efficiency DC-DC power solutions (e.g., multi-phase buck converters, VRMs) for battery life and high-performance CPU/GPU platforms. - Review customer schematic, PCB layout reviews, and component selection to meet power delivery requirement (e.g., voltage ripple, transient response, efficiency etc.). - Collaborate with cross-functional teams (Arch, EE, thermal, layout, SI/PI etc.) to provide motherboard reference board and server Rack power shelf requirement on time. - Conduct PDN(power delivery network) simulation and analysis, ensure power integrity - Co-work with multiple stakeholders to ensure signal integrity and thermal compliance for motherboard and System power. - Validate and debug power solution in the lab using oscilloscopes, e-loads etc. - Document test reports, design spec, and best practices for power solution. - Stay updated on industry trends in power electronics, energy-efficient technologies.PREFERRED EXPERIENCE: - Proficiency in Server or Data center rack, including power shelf technology, battery management, charger, deeply understand EC/BIOS/ACPI - Proficiency in DC-DC converter topologies (buck, boost, multiphase), PWM controllers, MOSFET, and power stage. - Experience with simulation tools (e.g., Simplis, SPICE, PowerDC, Ansys SIWave). - Strong knowledge of PCB layout considerations for power circuits (e.g., parasitic reduction). - PDN and PI analysis capability - Familiarity with lab equipment: oscilloscopes, spectrum analyzers, and power integrity test setups. - Knowledge of EMI/EMC mitigation techniques in power designs. - Familiarity with x86 system power management feature. - Familiarity with thermal management solutions for high-power-density systems. - Exposure to MCU-based, FPGA-based prototyping or scripting (Python, MATLAB, LabVIEW) for automation. - Good English communication - Problem-solving mindset, teamwork.ACADEMIC CREDENTIALS: - BS or above in Electrical/Electronic/Power Engineering, or related field - 5+ years of hands-on experience in power hardware design, preferably for high-speed computing platforms (e.g., CPUs, GPUs, ASICs).#LI-IH1 Benefits offered are described: AMD benefits at a glance.AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.This posting is for an existing vacancy.

Note: This is a mirrored copy of the posting from AMD's Career Page. For the official and most up-to-date listing, please refer to AMD's Career Page.---WHAT YOU DO AT AMD CHANGES EVERYTHINGAt AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE:The AMD Adaptive and Embedded Computing Group is seeking an experienced and self-motivated package design engineer. As a key member of the Package/Board group, you will work across chip, technology and systems teams to define cost effective and high performance solutions. THE PERSON: This is a high visibility position working on custom ASIC packages that include FPGA IP. The ideal candidate should have the ability to understand electrical requirements and translate to the proper package technology requirements that is cost effective and manufacturable. This role requires good communication skills to work with other teams and engineers at the various design centers to carry the projects from design start to signoff stages. KEY RESPONSIBILITIES:  - A packaging design engineer who has experiences on substrate layout design, ballmap assignment in terms of PCB design requirement, high speed interface (PAM-4 112Gbps/high speed DDR) design practices, advanced PKG (2.5D/3D PKG) design knowledge, low-cost PKG solution design including FCCSP, InFO, and thin-core design. - Come up with performance metrics for organic package technologies in order to design high speed chips and systems - Conduct routing, stack-up component placement studies in addition to completing the package design activities. Translate requirements (Design guidelines, technology, stackup, manufacturing time etc) for various device packaging. - Tradeoff PCB Layout guidelines/features to optimize the package ballmap and work with chip team to optimize the die size - Develop scripts for checking package parameters across device families, maintain a database of electrical design guidelines and rules for IO and PDN package layout implementations. - Support substrate layout review and work with layout designer to achieve electrical performance and DFx requirement during the design stage and final design review stage. PREFERRED EXPERIENCE:  - Have a good understanding of various Organic/PCB technologies in order to interpret/negotiate layout guidelines - Package/PCB layout experience. Experience in high power, Gbs IO products is a plus. - Current working Knowledge of Cadence package design tool is a must. knowledge of SKILL is a plus. - Working knowledge of 2D/3D package design and modeling tools, such as Cadence, Ansys, AutoCAD etc. - Knowledge on DoE, DFM/DFR is a plus. - Good knowledge of SerDes design and package/PCB layout constraints ACADEMIC CREDENTIALS:  - Bachelors or Masters degree in computer engineering/Electrical Engineering#LI-SH1#LI-HYBRID Benefits offered are described: AMD benefits at a glance.AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.This posting is for an existing vacancy.

1. RTL/Digital circuit design, synthesis, and simulation/verification.2. SOC security IP, DDR IP, Ethernet IP integration and design verification / FPGA emulation.3. FPGA synthesis, verification.4. SOC architecture development integration, algorithm implementation.5. High speed Serdes IO design verification.