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Note: This is a mirrored copy of the posting from AMD's Career Page. For the official and most up-to-date listing, please refer to AMD's Career Page.---WHAT YOU DO AT AMD CHANGES EVERYTHINGAt AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. The Role:We are seeking a high-caliber FPGA Design Engineer to develop our next-generation IO-based connectivity systems. drive the design from initial concept through to hardware validation.Key Responsibilities: - System Architecture Implementation: Lead the design, documentation, and implementation of complex IO-based connectivity systems, ensuring high-speed data integrity and system reliability. - Front-End Methodology Leadership: Drive advanced RTL design flows, including resource optimization (Area/Power), multi-clock domain crossing (CDC) analysis, and reset domain crossing (RDC) strategies. - Technical Documentation Lifecycle Management: Synthesize comprehensive Requirement Specifications, Design Specs, and Test Plans. You will ensure these documents account for complex interactions between hardware, firmware, and software drivers. - Cross-Functional Collaboration: Partner closely with Architects, Hardware Engineers, and Firmware teams to define feature sets, negotiate interfaces, and ensure seamless system integration.Required Technical Qualifications: - Xilinx Expertise: Minimum of 6 years of hands-on experience in RTL design with a deep-seated understanding of AMD-Xilinx UltraScale+ FPGA architectures. - Toolchain Proficiency: Expert-level command of the Vivado Design Suite (Synthesis, Implementation, and Timing Closure). - System-Level Architecture: Proven track record with high-speed bus protocols (AXI4/AXI-Stream), memory controllers, and interconnect bridges. - High-Speed Connectivity: Direct experience implementing and debugging one or more high-speed protocols: PCIe (Gen3/4/5), 10/25/100G Ethernet, TCP/IP offload engines, or USB 3.x. - Verification Debug: Proficient in RTL simulation (Xcelium, Questa, or Vivado Simulator) and hardware-in-the-loop debugging using Xilinx ChipScope/ILA.Professional Attributes: - Ownership: A self-starting mindset with the ability to navigate ambiguity and independently drive tasks to production-ready completion. - Problem-Solving: Exceptional analytical skills for triaging complex system-level hardware/software bugs. - Communication: Ability to articulate technical trade-offs to both technical and non-technical stakeholders.Academic Credentials: - Bachelor’s or Master’s degree in electrical/computer engineering or related field preferred.Location:Taipei Taiwan#LI-VJ1 Benefits offered are described: AMD benefits at a glance.AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.This posting is for an existing vacancy.

Note: This is a mirrored copy of the posting from AMD's Career Page. For the official and most up-to-date listing, please refer to AMD's Career Page.---WHAT YOU DO AT AMD CHANGES EVERYTHINGAt AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. The Role:We are seeking a high-caliber FPGA Design Engineer to develop our next-generation IO-based connectivity systems. drive the design from initial concept through to hardware validation.Key Responsibilities: - System Architecture Implementation: Lead the design, documentation, and implementation of complex IO-based connectivity systems, ensuring high-speed data integrity and system reliability. - Front-End Methodology Leadership: Drive advanced RTL design flows, including resource optimization (Area/Power), multi-clock domain crossing (CDC) analysis, and reset domain crossing (RDC) strategies. - Technical Documentation Lifecycle Management: Synthesize comprehensive Requirement Specifications, Design Specs, and Test Plans. You will ensure these documents account for complex interactions between hardware, firmware, and software drivers. - Cross-Functional Collaboration: Partner closely with Architects, Hardware Engineers, and Firmware teams to define feature sets, negotiate interfaces, and ensure seamless system integration.Required Technical Qualifications: - Xilinx Expertise: Minimum of 6 years of hands-on experience in RTL design with a deep-seated understanding of AMD-Xilinx UltraScale+ FPGA architectures. - Toolchain Proficiency: Expert-level command of the Vivado Design Suite (Synthesis, Implementation, and Timing Closure). - System-Level Architecture: Proven track record with high-speed bus protocols (AXI4/AXI-Stream), memory controllers, and interconnect bridges. - High-Speed Connectivity: Direct experience implementing and debugging one or more high-speed protocols: PCIe (Gen3/4/5), 10/25/100G Ethernet, TCP/IP offload engines, or USB 3.x. - Verification Debug: Proficient in RTL simulation (Xcelium, Questa, or Vivado Simulator) and hardware-in-the-loop debugging using Xilinx ChipScope/ILA.Professional Attributes: - Ownership: A self-starting mindset with the ability to navigate ambiguity and independently drive tasks to production-ready completion. - Problem-Solving: Exceptional analytical skills for triaging complex system-level hardware/software bugs. - Communication: Ability to articulate technical trade-offs to both technical and non-technical stakeholders.Academic Credentials: - Bachelor’s or Master’s degree in electrical/computer engineering or related field preferred.Location:Taipei Taiwan#LI-VJ1 Benefits offered are described: AMD benefits at a glance.AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.This posting is for an existing vacancy.

About the Role: FPT Telecom is building the next generation of Edge AI computing solutions. We are looking for a highly skilled FPGA Engineer with specialized experience in AI Acceleration using AMD/Xilinx Versal ACAP architectures. In this role, you will bridge the gap between AI algorithms and hardware execution, developing high-performance, low-latency, and power-efficient AI accelerators for AI Server. Key Responsibilities: AI Hardware Deployment: Compile and deploy AI models (CNNs, Transformers) from frameworks (PyTorch/TensorFlow) to FPGA/SoC hardware using Vitis AI.AI Engine (AIE) Programming: Design, implement (in C/C++), and optimize parallel computing algorithms onto the AI Engine array of Xilinx Versal devices.Dataflow Optimization: Architect high-throughput data movement between Programmable Logic (PL), Processing System (PS), and AIE using AXI-Stream, DMA, and Network-on-Chip (NoC).System Integration: Collaborate with AI Engineers for model quantization (INT8/FP16) and HW Engineers to integrate custom pre/post-processing blocks (Verilog/HLS) into the system.Verification Profiling: Perform hardware-in-the-loop testing, bottleneck analysis, and profiling using Vitis Analyzer on actual evaluation boards.

Note: This is a mirrored copy of the posting from AMD's Career Page. For the official and most up-to-date listing, please refer to AMD's Career Page.---WHAT YOU DO AT AMD CHANGES EVERYTHINGAt AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE:The AMD Adaptive and Embedded Computing Group is seeking an experienced and self-motivated package design engineer. As a key member of the Package/Board group, you will work across chip, technology and systems teams to define cost effective and high performance solutions. THE PERSON: This is a high visibility position working on custom ASIC packages that include FPGA IP. The ideal candidate should have the ability to understand electrical requirements and translate to the proper package technology requirements that is cost effective and manufacturable. This role requires good communication skills to work with other teams and engineers at the various design centers to carry the projects from design start to signoff stages. KEY RESPONSIBILITIES:  - A packaging design engineer who has experiences on substrate layout design, ballmap assignment in terms of PCB design requirement, high speed interface (PAM-4 112Gbps/high speed DDR) design practices, advanced PKG (2.5D/3D PKG) design knowledge, low-cost PKG solution design including FCCSP, InFO, and thin-core design. - Come up with performance metrics for organic package technologies in order to design high speed chips and systems - Conduct routing, stack-up component placement studies in addition to completing the package design activities. Translate requirements (Design guidelines, technology, stackup, manufacturing time etc) for various device packaging. - Tradeoff PCB Layout guidelines/features to optimize the package ballmap and work with chip team to optimize the die size - Develop scripts for checking package parameters across device families, maintain a database of electrical design guidelines and rules for IO and PDN package layout implementations. - Support substrate layout review and work with layout designer to achieve electrical performance and DFx requirement during the design stage and final design review stage. PREFERRED EXPERIENCE:  - Have a good understanding of various Organic/PCB technologies in order to interpret/negotiate layout guidelines - Package/PCB layout experience. Experience in high power, Gbs IO products is a plus. - Current working Knowledge of Cadence package design tool is a must. knowledge of SKILL is a plus. - Working knowledge of 2D/3D package design and modeling tools, such as Cadence, Ansys, AutoCAD etc. - Knowledge on DoE, DFM/DFR is a plus. - Good knowledge of SerDes design and package/PCB layout constraints ACADEMIC CREDENTIALS:  - Bachelors or Masters degree in computer engineering/Electrical Engineering#LI-SH1#LI-HYBRID Benefits offered are described: AMD benefits at a glance.AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.This posting is for an existing vacancy.

Note: This is a mirrored copy of the posting from AMD's Career Page. For the official and most up-to-date listing, please refer to AMD's Career Page.---WHAT YOU DO AT AMD CHANGES EVERYTHINGAt AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE:As a Power Engineer in the ODM Enablement, Data Center Platform Engineering (DPEG), you will be responsible to work with ODM/OEM/Customer for the Power Design and validation for the AMD Data Center GPU products in this expanding and strategic market for AMD. To accomplish this, you will need to interact with other key engineering teams such as silicon design, boarding engineering, power delivery, validation, and manufacturing within AMD. Collaborate closely with Architecture, Hardware, Thermal, SI/PI, and Layout experts to deliver robust designs. You’ll own supporting ODM/customer on the full product lifecycle – from simulation and schematic design to hands-on lab validation and debugging – ensuring power integrity meets rigorous performance standards. Here, you’ll constantly push boundaries in to support customer on power efficiency, work with advanced tools, solve complex technical puzzles, and systems validation that shape the future of computing.THE PERSON:We are seeking a talentedPlatform Power Design Engineerto join us, supporting ODM/OEM/Customer focusing on the development of cutting-edge DC-DC power delivery solutions for next-generation Server motherboard and Rack System Power. Solving tough technical challenges. A natural problem-solver, meticulous in validation and debugging but also think big-picture to optimize system-level performance. KEY RESPONSIBILITIES: - Work with ODM/OEM/Customer on Design review, simulate, verification and optimize high-efficiency DC-DC power solutions (e.g., multi-phase buck converters, VRMs) for battery life and high-performance CPU/GPU platforms. - Review customer schematic, PCB layout reviews, and component selection to meet power delivery requirement (e.g., voltage ripple, transient response, efficiency etc.). - Collaborate with cross-functional teams (Arch, EE, thermal, layout, SI/PI etc.) to provide motherboard reference board and server Rack power shelf requirement on time. - Conduct PDN(power delivery network) simulation and analysis, ensure power integrity - Co-work with multiple stakeholders to ensure signal integrity and thermal compliance for motherboard and System power. - Validate and debug power solution in the lab using oscilloscopes, e-loads etc. - Document test reports, design spec, and best practices for power solution. - Stay updated on industry trends in power electronics, energy-efficient technologies.PREFERRED EXPERIENCE: - Proficiency in Server or Data center rack, including power shelf technology, battery management, charger, deeply understand EC/BIOS/ACPI - Proficiency in DC-DC converter topologies (buck, boost, multiphase), PWM controllers, MOSFET, and power stage. - Experience with simulation tools (e.g., Simplis, SPICE, PowerDC, Ansys SIWave). - Strong knowledge of PCB layout considerations for power circuits (e.g., parasitic reduction). - PDN and PI analysis capability - Familiarity with lab equipment: oscilloscopes, spectrum analyzers, and power integrity test setups. - Knowledge of EMI/EMC mitigation techniques in power designs. - Familiarity with x86 system power management feature. - Familiarity with thermal management solutions for high-power-density systems. - Exposure to MCU-based, FPGA-based prototyping or scripting (Python, MATLAB, LabVIEW) for automation. - Good English communication - Problem-solving mindset, teamwork.ACADEMIC CREDENTIALS: - BS or above in Electrical/Electronic/Power Engineering, or related field - 5+ years of hands-on experience in power hardware design, preferably for high-speed computing platforms (e.g., CPUs, GPUs, ASICs).#LI-IH1 Benefits offered are described: AMD benefits at a glance.AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.This posting is for an existing vacancy.

Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 8 years of experience with digital logic design principles, RTL design concepts, and languages, such as Verilog or SystemVerilog. 8 years of experience with multiple IPs/SoCs with silicon success. Experience with logic synthesis techniques to optimize RTL code, performance and power, as well as low-power design techniques. Preferred qualifications: Master's or PhD degree in Electrical Engineering, Computer Engineering or Computer Science. Experience with a scripting language like Perl or Python. Experience with ASIC or FPGA design verification, synthesis, timing/power analysis, and DFT. Knowledge of high-performance and low-power design techniques, assertion-based formal verification, FPGA and emulation platforms, and SOC architecture. Knowledge of memory compression, fabric, coherence, cache, or DRAM. About the jobBe part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.Responsibilities Define the block-level design document (e.g., interface protocol, block diagram, transaction flow, pipeline, etc.). Perform RTL coding, function/performance simulation debug, and Lint/Clock Domain Crossing (CDC)/Formal Verification (FV)/Unified Power Format (UPF) checks. Participate in synthesis, timing/power closure, and FPGA/silicon bring-up. Participate in test plan and coverage analysis of the block and ASIC-level verification. Communicate and work with multi-disciplined and multi-site teams. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.

Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 4 years of experience with digital logic design principles, RTL design concepts, and languages, such as Verilog or SystemVerilog. Experience with logic synthesis techniques to optimize RTL code, performance and power, as well as low-power design techniques. Preferred qualifications: Master's or PhD degree in Electrical Engineering, Computer Engineering, or Computer Science. Experience with a scripting language like Perl or Python. Experience with ASIC or FPGA design verification, synthesis, timing/power analysis, and DFT. Knowledge of high-performance and low-power design techniques, assertion-based formal verification, FPGA and emulation platforms, and SOC architecture. Knowledge of memory compression, fabric, coherence, cache, or Dynamic Random Access Memory (DRAM). About the jobBe part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. In this role, you will be creating the micro-architecture and design of the critical IPs widely used across multiple mobile SOC's subsystems and running extensive quality checks including Lint, Clock Domain Crossing (CDC), low power checks (VCLP), synthesis, and timing and power analysis. You should be able to timely deliver IPs and work with various cross-functional teams (DV/DFT/PD/power) to ensure quality.The Platforms and Devices team encompasses Google's various computing software platforms across environments (desktop, mobile, applications), as well as our first party devices and services that combine the best of Google AI, software, and hardware. Teams across this area research, design, and develop new technologies to make our user's interaction with computing faster and more seamless, building innovative experiences for our users around the world.Responsibilities Define the block-level design document (e.g., interface protocol, block diagram, transaction flow, pipeline, etc.). Perform Register-Transfer Level (RTL) coding, function/performance simulation debug, and Lint/CDC/FV/UPF checks. Participate in synthesis, timing/power closure, and Field Programmable Gate Array (FPGA)/silicon bring-up. Participate in test plan and coverage analysis of the block and Application Specific Integrated Circuit (ASIC) level verification. Communicate and work with multi-disciplined and multi-site teams. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.Role Overview The AI infrastructure landscape is evolving at breakneck speed, and Astera Labs is at the center of it — delivering the intelligent connectivity solutions that enable the most demanding AI and cloud workloads on the planet. As server platforms grow increasingly complex with multi-socket architectures, accelerator-dense configurations, and high-speed interconnect fabrics, the need for world-class hardware architects who can define and deliver these systems end-to-end has never been more critical. The AI Platform Solutions Group is seeking a Senior Principal Hardware / System Architect to lead the architecture, design, and development of next-generation x86 and accelerator-based server platforms. You will own system-level architecture decisions spanning compute, memory, storage, and interconnect subsystems — driving hardware platform development from concept through bring-up and validation. This role sits at the intersection of silicon, board design, FPGA/ASIC development, and platform integration, with direct impact on how AI infrastructure scales at the rack and cluster level. This is a high-impact technical leadership role where you will partner across hardware, firmware, and platform engineering teams while collaborating with customers, silicon vendors, and hyperscalers to deliver custom, high-performance compute solutions. If you thrive on solving the hardest hardware architecture challenges and want to shape the platforms that power the next wave of AI, this is the opportunity. Key Responsibilities System Architecture Platform Design Lead end-to-end system architecture and design for server platforms including x86 multi-socket and accelerator-based systems Define and maintain multi-platform design standards and architectures that scale across product lines Drive hardware platform development including board design, system bring-up, and validation Oversee system-level integration across compute, storage, and interconnect subsystems — including PCIe Gen5/6 and high-speed fabric connectivity FPGA Hardware Development Leadership Lead FPGA architecture and development including simulation, synthesis, validation, and common framework definition Drive signal integrity analysis, functional validation, and defect resolution across complex hardware systems Own hardware debug and bring-up in lab environments, ensuring seamless integration with firmware and software stacks Cross-Functional Customer Engagement Provide technical leadership and mentorship to distributed engineering teams across hardware, firmware, and platform disciplines Coordinate cross-functional activities to ensure alignment between hardware design, firmware integration, and system validation Collaborate with customers and stakeholders on custom system solutions, technical briefings, and field issue resolution Partner with silicon vendors, OEMs, and hyperscalers to drive platform innovation aligned with Astera Labs' connectivity ecosystem Basic Qualifications Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field 12+ years of experience in hardware development or system architecture Deep expertise in x86 server architecture, including multi-processor systems Experience with FPGA and/or ASIC design including simulation, synthesis, and validation Strong knowledge of high-speed interconnects (PCIe, UPI/QPI, Ethernet) and signal integrity principles Proven experience with system bring-up, debug, and validation in lab environments Experience leading complex hardware programs and cross-functional engineering teams Strong knowledge of memory subsystems, cache coherency, and PCB design Preferred Qualifications Master's degree in Electrical Engineering, Computer Engineering, or Computer Science Experience with accelerator-based systems (GPU, AI/ML workloads) or AI training cluster hardware Familiarity with heterogeneous computing architectures or composable infrastructure Experience with EDA tools such as Cadence, Allegro, Quartus, or Xilinx environments Programming experience in C, Python, or scripting languages for hardware automation and validation Background in enterprise server, data center hardware, or custom system development Experience working with global development teams and customer-facing engineering engagements Knowledge of fault-tolerant design or secure communication systems We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Google welcomes people with disabilities.Minimum qualifications: Bachelor's degree or equivalent practical experience. 2 years of experience with software development in one or more programming languages (C or C++). Experience with embedded systems design, development, and debugging. Preferred qualifications: Experience with C/C++ and embedded systems. Experience with emulation platforms, FPGAs, or silicon bring up. Experience with Linux and Android device driver development. Experience with firmware, realtime operating system, or Android platform development. Experience with display technologies, such as DPU, DSI, and Displayport. About the jobGoogle's software engineers develop the next-generation technologies that change how billions of users connect, explore, and interact with information and one another. Our products need to handle information at massive scale, and extend well beyond web search. We're looking for engineers who bring fresh ideas from all areas, including information retrieval, distributed computing, large-scale system design, networking and data storage, security, artificial intelligence, natural language processing, UI design and mobile; the list goes on and is growing every day. As a software engineer, you will work on a specific project critical to Google’s needs with opportunities to switch teams and projects as you and our fast-paced business grow and evolve. We need our engineers to be versatile, display leadership qualities and be enthusiastic to take on new problems across the full-stack as we continue to push technology forward. As a member of the Silicon Validation software team, you will develop a platform with drivers and tools to enable validation of Google Tensor. The software you developed will be executed in a variety of environments ranging from bare metal to embedded Linux, on a variety of platforms ranging from FPGA emulation to post-silicon hardware.In addition, you will support users of the software through collaboration with teams inside and outside of the silicon group. You will build a deep understanding of the various components of the hardware pipeline.Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.Responsibilities Design and implement the validation software for Google Tensor. Create and integrate software on emulation, FPGA, and silicon environments. Develop, maintain, and integrate software test infrastructure, unit tests, and integration tests. Collaborate with internal and external partners to support the development and execution of the validation plans. Support users in development of production device drivers and debug failures. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.

We are seeking a PCB Hardware Design Engineer to participate in the design, development, and testing of FPGA-based signal processing systems for defense applications. Key responsibilities: Designing signal processing boards using Xilinx RFSoC Gen3 with integrated high-speed ADC/DAC.Developing schematics and multi-layer PCB layouts in compliance with VPX military/industrial standards.Integrating high-speed interfaces such as Ethernet, JESD204B/C, PCIe, UART, USB, CAN, I2C, RS422, RAM, and Flash memory.Designing power architecture, including power trees and power supply circuits for FPGA systems (Power Management, Switching Regulators, LDOs, etc.).Creating and managing BOMs, and working with manufacturers to ensure product quality and fabrication/assembly readiness.Collaborating closely with system, FPGA, embedded software, and mechanical teams to ensure cohesive design integration.Participating in board bring-up, signal validation, performance evaluation, and debugging using tools such as oscilloscopes, logic analyzers, and DMMs.Supporting final system integration, field testing, troubleshooting, and performance optimization.