Cake Job Search

・

Nangang District, Taipei City, Taiwan

Negotiable

3 years of experience required

No management responsibility

"RTL"

"PCIe"

"FPGA"

・

・

Nangang District, Taipei City, Taiwan

Negotiable

3 years of experience required

No management responsibility

Note: This is a mirrored copy of the posting from AMD's Career Page. For the official and most up-to-date listing, please refer to AMD's Career Page.---WHAT YOU DO AT AMD CHANGES EVERYTHINGAt AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE:The AMD Adaptive and Embedded Computing Group is seeking an experienced and self-motivated package design engineer. As a key member of the Package/Board group, you will work across chip, technology and systems teams to define cost effective and high performance solutions. THE PERSON: This is a high visibility position working on custom ASIC packages that include FPGA IP. The ideal candidate should have the ability to understand electrical requirements and translate to the proper package technology requirements that is cost effective and manufacturable. This role requires good communication skills to work with other teams and engineers at the various design centers to carry the projects from design start to signoff stages. KEY RESPONSIBILITIES:  - A packaging design engineer who has experiences on substrate layout design, ballmap assignment in terms of PCB design requirement, high speed interface (PAM-4 112Gbps/high speed DDR) design practices, advanced PKG (2.5D/3D PKG) design knowledge, low-cost PKG solution design including FCCSP, InFO, and thin-core design. - Come up with performance metrics for organic package technologies in order to design high speed chips and systems - Conduct routing, stack-up component placement studies in addition to completing the package design activities. Translate requirements (Design guidelines, technology, stackup, manufacturing time etc) for various device packaging. - Tradeoff PCB Layout guidelines/features to optimize the package ballmap and work with chip team to optimize the die size - Develop scripts for checking package parameters across device families, maintain a database of electrical design guidelines and rules for IO and PDN package layout implementations. - Support substrate layout review and work with layout designer to achieve electrical performance and DFx requirement during the design stage and final design review stage. PREFERRED EXPERIENCE:  - Have a good understanding of various Organic/PCB technologies in order to interpret/negotiate layout guidelines - Package/PCB layout experience. Experience in high power, Gbs IO products is a plus. - Current working Knowledge of Cadence package design tool is a must. knowledge of SKILL is a plus. - Working knowledge of 2D/3D package design and modeling tools, such as Cadence, Ansys, AutoCAD etc. - Knowledge on DoE, DFM/DFR is a plus. - Good knowledge of SerDes design and package/PCB layout constraints ACADEMIC CREDENTIALS:  - Bachelors or Masters degree in computer engineering/Electrical Engineering#LI-SH1#LI-HYBRID Benefits offered are described: AMD benefits at a glance.AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.This posting is for an existing vacancy.

"SerDes"

"Power"

"FPGA"

・

・

E. District, Hsinchu City, Taiwan

Negotiable

3 years of experience required

No management responsibility

Note: This is a mirrored copy of the posting from AMD's Career Page. For the official and most up-to-date listing, please refer to AMD's Career Page.---WHAT YOU DO AT AMD CHANGES EVERYTHINGAt AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE:As a Power Engineer in the ODM Enablement, Data Center Platform Engineering (DPEG), you will be responsible to work with ODM/OEM/Customer for the Power Design and validation for the AMD Data Center GPU products in this expanding and strategic market for AMD. To accomplish this, you will need to interact with other key engineering teams such as silicon design, boarding engineering, power delivery, validation, and manufacturing within AMD. Collaborate closely with Architecture, Hardware, Thermal, SI/PI, and Layout experts to deliver robust designs. You’ll own supporting ODM/customer on the full product lifecycle – from simulation and schematic design to hands-on lab validation and debugging – ensuring power integrity meets rigorous performance standards. Here, you’ll constantly push boundaries in to support customer on power efficiency, work with advanced tools, solve complex technical puzzles, and systems validation that shape the future of computing.THE PERSON:We are seeking a talentedPlatform Power Design Engineerto join us, supporting ODM/OEM/Customer focusing on the development of cutting-edge DC-DC power delivery solutions for next-generation Server motherboard and Rack System Power. Solving tough technical challenges. A natural problem-solver, meticulous in validation and debugging but also think big-picture to optimize system-level performance. KEY RESPONSIBILITIES: - Work with ODM/OEM/Customer on Design review, simulate, verification and optimize high-efficiency DC-DC power solutions (e.g., multi-phase buck converters, VRMs) for battery life and high-performance CPU/GPU platforms. - Review customer schematic, PCB layout reviews, and component selection to meet power delivery requirement (e.g., voltage ripple, transient response, efficiency etc.). - Collaborate with cross-functional teams (Arch, EE, thermal, layout, SI/PI etc.) to provide motherboard reference board and server Rack power shelf requirement on time. - Conduct PDN(power delivery network) simulation and analysis, ensure power integrity - Co-work with multiple stakeholders to ensure signal integrity and thermal compliance for motherboard and System power. - Validate and debug power solution in the lab using oscilloscopes, e-loads etc. - Document test reports, design spec, and best practices for power solution. - Stay updated on industry trends in power electronics, energy-efficient technologies.PREFERRED EXPERIENCE: - Proficiency in Server or Data center rack, including power shelf technology, battery management, charger, deeply understand EC/BIOS/ACPI - Proficiency in DC-DC converter topologies (buck, boost, multiphase), PWM controllers, MOSFET, and power stage. - Experience with simulation tools (e.g., Simplis, SPICE, PowerDC, Ansys SIWave). - Strong knowledge of PCB layout considerations for power circuits (e.g., parasitic reduction). - PDN and PI analysis capability - Familiarity with lab equipment: oscilloscopes, spectrum analyzers, and power integrity test setups. - Knowledge of EMI/EMC mitigation techniques in power designs. - Familiarity with x86 system power management feature. - Familiarity with thermal management solutions for high-power-density systems. - Exposure to MCU-based, FPGA-based prototyping or scripting (Python, MATLAB, LabVIEW) for automation. - Good English communication - Problem-solving mindset, teamwork.ACADEMIC CREDENTIALS: - BS or above in Electrical/Electronic/Power Engineering, or related field - 5+ years of hands-on experience in power hardware design, preferably for high-speed computing platforms (e.g., CPUs, GPUs, ASICs).#LI-IH1 Benefits offered are described: AMD benefits at a glance.AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.This posting is for an existing vacancy.

"Server"

"Python"

"FPGA"

・

・

Nangang District, Taipei City, Taiwan

Negotiable

3 years of experience required

No management responsibility

Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 8 years of experience with digital logic design principles, RTL design concepts, and languages, such as Verilog or SystemVerilog. 8 years of experience with multiple IPs/SoCs with silicon success. Experience with logic synthesis techniques to optimize RTL code, performance and power, as well as low-power design techniques. Preferred qualifications: Master's or PhD degree in Electrical Engineering, Computer Engineering or Computer Science. Experience with a scripting language like Perl or Python. Experience with ASIC or FPGA design verification, synthesis, timing/power analysis, and DFT. Knowledge of high-performance and low-power design techniques, assertion-based formal verification, FPGA and emulation platforms, and SOC architecture. Knowledge of memory compression, fabric, coherence, cache, or DRAM. About the jobBe part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.Responsibilities Define the block-level design document (e.g., interface protocol, block diagram, transaction flow, pipeline, etc.). Perform RTL coding, function/performance simulation debug, and Lint/Clock Domain Crossing (CDC)/Formal Verification (FV)/Unified Power Format (UPF) checks. Participate in synthesis, timing/power closure, and FPGA/silicon bring-up. Participate in test plan and coverage analysis of the block and ASIC-level verification. Communicate and work with multi-disciplined and multi-site teams. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.

・

・

Bengaluru Urban, Karnataka, India

・

Negotiable

No requirement for relevant working experience

Google welcomes people with disabilities.Minimum qualifications: Bachelor's degree or equivalent practical experience. 2 years of experience with software development in one or more programming languages (C or C++). Experience with embedded systems design, development, and debugging. Preferred qualifications: Experience with C/C++ and embedded systems. Experience with emulation platforms, FPGAs, or silicon bring up. Experience with Linux and Android device driver development. Experience with firmware, realtime operating system, or Android platform development. Experience with display technologies, such as DPU, DSI, and Displayport. About the jobGoogle's software engineers develop the next-generation technologies that change how billions of users connect, explore, and interact with information and one another. Our products need to handle information at massive scale, and extend well beyond web search. We're looking for engineers who bring fresh ideas from all areas, including information retrieval, distributed computing, large-scale system design, networking and data storage, security, artificial intelligence, natural language processing, UI design and mobile; the list goes on and is growing every day. As a software engineer, you will work on a specific project critical to Google’s needs with opportunities to switch teams and projects as you and our fast-paced business grow and evolve. We need our engineers to be versatile, display leadership qualities and be enthusiastic to take on new problems across the full-stack as we continue to push technology forward. As a member of the Silicon Validation software team, you will develop a platform with drivers and tools to enable validation of Google Tensor. The software you developed will be executed in a variety of environments ranging from bare metal to embedded Linux, on a variety of platforms ranging from FPGA emulation to post-silicon hardware.In addition, you will support users of the software through collaboration with teams inside and outside of the silicon group. You will build a deep understanding of the various components of the hardware pipeline.Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.Responsibilities Design and implement the validation software for Google Tensor. Create and integrate software on emulation, FPGA, and silicon environments. Develop, maintain, and integrate software test infrastructure, unit tests, and integration tests. Collaborate with internal and external partners to support the development and execution of the validation plans. Support users in development of production device drivers and debug failures. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.

・

・

Banqiao District, New Taipei, Taiwan

New Taipei, Taiwan

・

Negotiable

No requirement for relevant working experience

Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 8 years of experience with digital logic design principles, RTL design concepts, and languages, such as Verilog or SystemVerilog. Experience with logic synthesis techniques to optimize RTL code, performance and power, as well as low-power design techniques. Preferred qualifications: Master's or PhD degree in Electrical Engineering, Computer Engineering or Computer Science. Experience with a scripting language like Perl or Python. Experience with ASIC or FPGA design verification, synthesis, timing/power analysis, and DFT. Knowledge of high-performance and low-power design techniques, assertion-based formal verification, FPGA and emulation platforms, and SOC architecture. Knowledge of memory compression, fabric, coherence, cache, or DRAM. About the jobBe part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.The Platforms and Devices team encompasses Google's various computing software platforms across environments (desktop, mobile, applications), as well as our first party devices and services that combine the best of Google AI, software, and hardware. Teams across this area research, design, and develop new technologies to make our user's interaction with computing faster and more seamless, building innovative experiences for our users around the world.Responsibilities Set technical direction for the team within the capacity of technical lead and people manager. Engage with Machine Learning System Architects and Software teams to define specifications and implement digital logic using Chisel, Verilog, and/or SystemVerilog. Engage with Verification and Silicon Validation teams to ensure functionality of the design. Perform power, area, and performance trade-offs of digital designs and architectures. Apply engineering best practices (e.g., code review, testing, refactoring) to the design and implementation of ASIC blocks. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.

・

・

Bengaluru Urban, Karnataka, India

・

Negotiable

No requirement for relevant working experience

Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. 4 years of experience with digital logic design principles, RTL design concepts, and languages, such as Verilog or SystemVerilog. Experience with logic synthesis techniques to optimize RTL code, performance and power, as well as low-power design techniques. Preferred qualifications: Master's or PhD degree in Electrical Engineering, Computer Engineering, or Computer Science. Experience with a scripting language like Perl or Python. Experience with ASIC or FPGA design verification, synthesis, timing/power analysis, and DFT. Knowledge of high-performance and low-power design techniques, assertion-based formal verification, FPGA and emulation platforms, and SOC architecture. Knowledge of memory compression, fabric, coherence, cache, or DRAM. About the jobBe part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. In this role, you will be a part of the team which designs the SoC and Subsystem. You will be working through all phases of design and implementation. You will be working with architects to come up with microarchitecture specifications. You will use your logic design skills to convert the micro-arch into System Verilog code. You will be involved in Power, Performance and Area (PPA) experiments/prototyping experiments early on to optimize PPA. You will also work closely with the verification team to verify the features implemented in design. You will also work with the Physical Design (PD) team to take the design through the PD cycle and eventual tape-out.The Platforms and Devices team encompasses Google's various computing software platforms across environments (desktop, mobile, applications), as well as our first party devices and services that combine the best of Google AI, software, and hardware. Teams across this area research, design, and develop new technologies to make our user's interaction with computing faster and more seamless, building innovative experiences for our users around the world.Responsibilities Define the block-level design document (e.g., interface protocol, block diagram, transaction flow, pipeline, etc.). Perform RTL coding, function/performance simulation debug, and Lint/CDC/FV/UPF checks. Participate in test plan and coverage analysis of the block and ASIC-level verification. Communicate and work with multi-disciplined and multi-site teams. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.

・

・

Bengaluru Urban, Karnataka, India

・

Negotiable

No requirement for relevant working experience

Logitech is the Sweet Spot for people who want their actions to have a positive global impact while having the flexibility to do it in their own way.The Role:We are expanding our Test Automation team in Chennai to support and contributeto the development, maintenance, and improvement of our automation frameworks especially with FPGA for our Test fixtures. This position is ideal for someone with a strong technical foundation and a desire to grow into a specialist in test automation for embedded systems and consumer electronics.Your Contribution:In this role you will:● Support the deployment, maintenance, and improvement of Python-based Test Frameworks.● Contribute to the development and execution of automated test scripts using Python.● Participate in manual and automated testing methodologies.● Understand and follow detailed test plans and procedures to validate products.● Add/Modify FW Modules in Xilinx based FPGA Boards.● Perform basic debugging and troubleshooting.● Document test procedures, results, and contribute to user-friendly tool documentation.● Collaborate with validation engineers to ensure test coverage and product quality.● Learn and apply best practices in test design, automation, and quality assurance.Key Qualifications:For consideration, you must bring the following minimum skills and behaviors to our team:● 6–10 years of experience in software testing, automation, or embedded systems validation.● Solid knowledge of Python programming.● Interest in embedded systems testing and automation tools.● Exposure to manual and automated testing methodologies.● Ability to understand and execute detailed test plans and procedures.● Knowledge of electronics engineering fundamentals.● Hands-on assembly and wiring of electronic test benches, including integration of sensors,connectors, and harnesses.● Debugging and troubleshooting of electronic circuits, signal integrity, and connectivity issues.● Proficiency with lab equipment: oscilloscopes, USB analysers, power supplies, voltmeters, etc.● Familiarity with communication protocols such as UART,USB, Ethernet, Bluetooth.● Strong problem-solving and analytical skills.● Good verbal and written communication skills in English.● A team player with a willingness to learn and take guidance from senior engineers.In addition, preferable certification/skills include:● Xilinx Certified VHDL and Verilog Designer● ISTQB or equivalent certificationEducation:● Bachelor’s Degree in ECE/EEEAcross Logitech we empower collaboration and foster play. We help teams collaborate/learn from anywhere, without compromising on productivity or continuity so it should be no surprise that most of our jobs are open to work from home from most locations. Our hybrid work model allows some employees to work remotely while others work on-premises. Within this structure, you may have teams or departments split between working remotely and working in-house.Logitech is an amazing place to work because it is full of authentic people who are inclusive by nature as well as by design. Being a global company, we value our diversity and celebrate all our differences. Don’t meet every single requirement? Not a problem. If you feel you are the right candidate for the opportunity, we strongly recommend that you apply. We want to meet you!We offer comprehensive and competitive benefits packages and working environments that are designed to be flexible and help you to care for yourself and your loved ones, now and in the future. We believe that good health means more than getting medical care when you need it. Logitech supports a culture that encourages individuals to achieve good physical, financial, emotional, intellectual and social wellbeing so we all can create, achieve and enjoy more and support our families. We can’t wait to tell you more about them being that there are too many to list here and they vary based on location.All qualified applicants will receive consideration for employment without regard to race, sex, age, color, religion, sexual orientation, gender identity, national origin, protected veteran status, or on the basis of disability.If you require an accommodation to complete any part of the application process, are limited in the ability, are unable to access or use this online application process and need an alternative method for applying, you may contact us toll free at 1-510-713-4866 for assistance and we will get back to you as soon as possible.

・

・

Chennai district, Tamil Nadu, India

・

Negotiable

No requirement for relevant working experience

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com. Astera Labs is seeking highly motivated Interns to join the Sales team in the TW team. If you are: A Junior going into Senior year or Senior graduating by the end of this year Have strong academics and technical background in Electrical Engineering Someone with a professional attitude, ability to prioritize a dynamic list of multiple tasks and work with minimal guidance and supervision Strong in analytical skills, self-motivated and a challenge taker What we are looking for: Develop regional sales analysis and planning materials by identifying market segments, opportunity sizing, and internal execution strategies Support sales initiatives by partnering closely with FAEs and internal stakeholders to prepare product information, roadmap materials, technology training content, and internal documentation Consolidate and analyze input from internal teams to support product planning, roadmap alignment, and internal issue tracking Coordinate cross-functional information flow among sales, operations, and supply-related teams to support quarterly revenue planning and mid-term demand projections Assist in market and ecosystem research across CPU, GPU, FPGA, Networking, Memory, and BMC segments to identify co-development and strategic opportunity areas If the above position excites you, we would love to hear from you. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

・

・

Taipei City, Taiwan

Negotiable

No requirement for relevant working experience