1. Perform physical synthesis from RTL or gate-to-gate optimization 2. Take responsibility for netlist, SDC and design quality check with customer 3. Chip I/O arrangement and verification with in-house tool 4. Perform low power structure verification (UPF/CPF) 5. Perform power replay and power analysis 6. Review/check implementation quality in each design stage 7. Cooperate with P&R in timing analysis 8. Planning chip
5 years of experience required
No management responsibility