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▍團隊介紹：你的未來夥伴 我們不只是在修補漏洞，我們是在建構「原生安全」的產品環境。資安工程師是我們技術團隊中的特種部隊，負責在駭客行動前找出弱點，並透過工程手段（Engineering）將防禦自動化。我們與 SRE、DevOps 團隊深度整合，共同打造高韌性的雲端架構。 ▍團隊文化：我們如何工作 - 實戰導向（Hands-on Mentality）我們重視程式碼與系統實作，不只是看報表。我們鼓勵同仁參與 CTF 比賽、挖掘漏洞，並將研究成果轉化為公司的防禦工具。- 自動化優先（Security as Code）手動掃描是過去式。我們追求將安全檢測整合進 CI/CD Pipeline，實現自動化 DAST/SAST，讓安全檢查如同單元測試一般自然。- 紅藍軍對抗（Red Blue Teaming）我們維持內部持續性的演練文化。透過紅軍（攻擊）發現盲點，藍軍（防禦）強化監控與回應機制，在真實威脅發生前完成進階部署。- 技術共好與分享（Knowledge Sharing）資安領域變化極快，我們每週舉行技術拆解會，分析最新 CVE 漏洞原理或新型攻擊載體，確保團隊始終站在技術前沿。 ▍關於職務：你將負責的工作內容 1. 滲透測試與弱點分析：執行 Web、API 及雲端架構的滲透測試，並提供具體的程式碼修復建議。2. DevSecOps 流程建置：在開發流程中嵌入安全自動化工具，建立漏洞自動化掃描與管理平台。3. 入侵偵測與應變（IR）：設計與維護 SOC 告警規則，主導重大資安事故的技術鑑定與數位鑑識。4. 雲端安全加固：針對 K8s 容器安全、雲端權限（IAM）及網路架構進行深度硬化（Hardening)。5. 安全工具開發：使用 Go 或 Python 開發內部專用的資安輔助工具或自動化檢測腳本。6. 特權帳號管理（PAM）：確保所有高權限操作皆有稽核軌跡（Audit Trails）。7. 資安自動化：開發自動化工具時，須確保工具本身的安全性（Secure coding for security tools）。 ▍我們提供的福利與環境 - 薪資範圍：月薪 NTD $70,000 - $120,000（依技術實力討論，資深者可面議）。- 戰力補助：全額補助資安證照考試費用（如 OSCP 等高階認證）、國內外資安大會門票、AI工具補助。- 工作彈性：遠距工作、彈性上下班。- 資安人專屬：提供高性能開發工作站與測試環境、不定期舉辦內部技術「攻防賽」、定期部門生日會、活動、聚餐。

▍團隊介紹：你的未來夥伴 資安不是限制，而是信任的基石。幣託資安團隊是組織的防護盾，更是業務擴展的推手。我們跳脫傳統「查核限制」的框架，致力於將安全整合進開發流程（DevSecOps），並建構具備韌性的防禦體系。你將與雲端架構師、SRE 及法律合規團隊緊密協作，守護台灣百萬用戶的數據資產。 ▍團隊文化：我們如何工作 - 安全左移文化（Shift-Left Security) 我們不當最後一關的警察。我們與開發團隊合作，從程式碼撰寫與架構設計階段就納入安全考量，致力於在漏洞產生前就將其排除。- 持續演進的防禦（Adaptive Defense）威脅是不斷變動的，我們的策略也是。團隊鼓勵持續研究新型攻擊手段（如 AI 社交工程、勒索軟體演變），並主動進行紅藍軍演練 （Red/Blue Teaming）。- 合規即代碼（Compliance as Code）我們厭倦了繁瑣的人工查核。團隊目標是將資安政策轉化為自動化偵測腳本，透過系統監控確保 ISO 27001 或相關法規的持續落實。- 透明與應變（Transparency Resilience）發生資安事件時，我們第一時間專注於損害控制與透明通報。我們重視事後分析（Post-mortem），將每一次挑戰轉化為防禦架構的升級機會。 ▍關於職務：你將負責的工作內容 1. 資安體系維護：維護並優化 ISMS 資訊安全管理體系（如 ISO 27001, TPIPA），確保公司運作符合法律法規。2. 威脅偵測與回應：監控 SOC 告警，主持資安事件應變流程（IR），進行弱點掃描 (VAPT) 與滲透測試後的追蹤改善。3. 安全架構設計：參與雲端環境（AWS/GCP/Azure）的安全設計，包含 IAM 權限管理、網路邊界防護（WAF/Zero Trust）。4. 資安意識推廣：設計並執行員工資安教育訓練及社交工程演練，建構全公司的安全文化。5. 供應鏈安全管理：執行第三方合作夥伴的資安評鑑與風險評估。6. 隱私保護：需處理個資保護（GDPR/PDPA）與資料去識別化流程評估。7. 應變計畫：負責制定並定期演練 BCP（營運持續計畫）與 DRP（災害復原計畫）。 ▍我們提供的福利與環境 - 薪資範圍：月薪 NTD $60,000 - $120,000（依經驗與能力討論，資深者可面議）。- 技術成長：補助資安認證考試費用（CISSP/CCSP 等）、資安年會（HITCON/iThome Cybersec）門票、AI工具補助。- 工作彈性：遠距工作、彈性上下班。- 部門限定福利：定期資安案例分享會（Deep Dive 國內外最新駭客事故）、專屬資安測試環境（提供環境練習滲透與攻防實務）、定期部門生日會、活動、聚餐。

About BTSE:BTSE Group is a global leader in fintech and blockchain technology, anchored by threecore business pillars: Exchange, Payments, and Infrastructure Development. Servingover 100 corporate clients worldwide, we provide white-label exchange and paymentsolutions. Our offerings encompass everything from exchange infrastructure hostingand development to custody, wallets, payments, blockchain integration, trading, andmore.We are looking for talented professionals in marketing, operations, customer support,and other departments. The roles offered may be on-site, remote, or hybrid, incollaboration with our local partner.About the opportunity:We are seeking a highly skilled Quant Developer to join our trading system developmentteam. You will play a critical role in building, optimising, and maintaining a high-performance, low-latency trading system. This is an exciting opportunity to work in afast-paced, collaborative environment and make a direct impact on trading strategiesand operations.ResponsibilitiesDesign, research, and validatesystematic alpha factorsacross price, order book, funding, flow, and microstructure dataBuild and maintain astructured alpha research pipeline(data → feature → signal → evaluation → iteration)Conduct factor analysis includingIC, IR, decay, stability, regime sensitivity, and turnover analysisCollaborate with engineering teams to ensureresearch outputs are production-readyContinuously iterate and improve existing alpha signals, even if historical performance has decayedExploreAI-assisted research workflowsfor factor generation, feature selection, and hypothesis exploration (bonus)Requirements3+ years of quantitative research experiencein systematic trading, alpha research, or related fieldsStrong proficiency inPython, with hands-on experience usingJupyter Notebookas a primary research environmentSolid understanding of theend-to-end alpha research process, including: Data cleaning normalization, Feature engineering, Factor construction, Signal evaluation validation.Have built and operated acomplete alpha research framework(personal or professional)Proven experience discovering alpha factors withstrong historical predictive power, e.g.: 1.Information Coefficient (IC)consistently above0.05–0.1on daily frequency or higher IC on lower-frequency signals with reasonable stability (factors that later decayed are acceptable, as long as the original research process was sound)Strong analytical thinking and ability to explainwhy a factor works, not just that it worksNice to haveExperience usingAI / ML models(e.g. tree models, neural networks, representation learning) for alpha researchHands-on experience withlocal deployment of AI models(not just calling APIs)Familiarity with AI-assisted factor discovery workflows (feature generation, signal screening, regime detection, etc.)Background in crypto, derivatives, or high-frequency / microstructure-driven markets#LI-MC1

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.Staff Physical Design Engineer About the Role We are seeking a Staff Physical Design Engineer to join our high-performance design team working on next-generation transceiver IPs targeting the TSMC 5nm, 3nm technology node. In this role, you will take ownership of physical implementation from RTL to GDSII, ensure timing and power closure for ultra-high-speed designs, and collaborate closely with cross-functional teams to resolve challenges unique to advanced nodes and multi-gigabit transceiver architectures. Key Responsibilities Perform full-chip and block-level physical implementation including floor planning, placement, clock tree synthesis (CTS), routing, and physical verification for high-speed designs in TSMC 3nm. Collaborate with RTL and STA teams to ensure clean handoffs and convergent timing, area, and power. Work on advanced physical design techniques to support multiple voltage/frequency domains, hierarchical design, and physical-aware synthesis. Handle advanced physical design topics: EM/IR analysis and power grid optimization Congestion analysis and mitigation Clock domain crossing and skew optimization RC extraction-aware placement and routing Integrate IPs and top-level blocks with attention to physical interfaces, constraints, and timing alignment. Participate in defining floorplan strategy and chip partitioning for multi-gigabit transceivers. Perform ECO implementation and support tapeout signoff activities. Ensure DRC/LVS/ANT/CELL/ERC clean database using industry-standard physical verification tools. Use industry-standard tools (e.g., ICC2, Innovus, Voltus, RedHawk, Calibre) for implementation and signoff. Develop and maintain automation scripts (Tcl, Python, Perl) for physical design flows and regressions. Required Qualifications Bachelor’s or Master’s degree in Electrical Engineering, Electronics Engineering, or related field. 4+ years of experience in physical design with advanced technology nodes (preferably ≤ 5nm). Strong experience with: Floor planning, placement, CTS, routing, and IR drop mitigation Signoff checks (DRC/LVS/ANT/ERC) and debugging Timing closure collaboration with STA team Hands-on experience with tools such as Synopsys ICC2, Cadence Innovus, Calibre, Voltus. Experience in integrating high-speed IPs (e.g., SerDes, PHYs) into SoC or chiplet environments. Experience in high frequence data path, DSP designs. Solid scripting skills for automation and productivity enhancement. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

About BTSE:彼特思方舟 is a specialized service provider dedicated to delivering a full spectrum of front-office and back-office support solutions, each of which are tailored to the unique needs of global financial technology firms. 彼特思方舟 is engaged by BTSE Group to offer several key positions, enabling the delivery of cutting-edge technology and tailored solutions that meet the evolving demands of the fintech industry in a competitive global market.BTSE Group is a leading global fintech and blockchain company that is committed to building innovative technology and infrastructure. BTSE empowers businesses and corporate clients with the advanced tools they need to excel in a rapidly evolving and competitive market. BTSE has pioneered numerous trading technologies that have been widely adopted across the industry, setting new benchmarks for innovation, performance, and security in fintech. BTSE’s diverse business lines serve both retail (B2C) customers and institutional (B2B) clients, enabling them to launch, operate, and scale fintech businesses. BTSE is seeking ambitious, motivated professionals to join our B2C and B2B teams.ResponsibilitiesDesign, research, and validatesystematic alpha factorsacross price, order book, funding, flow, and microstructure dataBuild and maintain astructured alpha research pipeline(data → feature → signal → evaluation → iteration)Conduct factor analysis includingIC, IR, decay, stability, regime sensitivity, and turnover analysisCollaborate with engineering teams to ensureresearch outputs are production-readyContinuously iterate and improve existing alpha signals, even if historical performance has decayedExploreAI-assisted research workflowsfor factor generation, feature selection, and hypothesis exploration (bonus)Requirements3+ years of quantitative research experiencein systematic trading, alpha research, or related fieldsStrong proficiency inPython, with hands-on experience usingJupyter Notebookas a primary research environmentSolid understanding of theend-to-end alpha research process, including: Data cleaning normalization, Feature engineering, Factor construction, Signal evaluation validation.Have built and operated acomplete alpha research framework(personal or professional)Proven experience discovering alpha factors withstrong historical predictive power, e.g.: 1.Information Coefficient (IC)consistently above0.05–0.1on daily frequency or higher IC on lower-frequency signals with reasonable stability (factors that later decayed are acceptable, as long as the original research process was sound)Strong analytical thinking and ability to explainwhy a factor works, not just that it worksNice to haveExperience usingAI / ML models(e.g. tree models, neural networks, representation learning) for alpha researchHands-on experience withlocal deployment of AI models(not just calling APIs)Familiarity with AI-assisted factor discovery workflows (feature generation, signal screening, regime detection, etc.)Background in crypto, derivatives, or high-frequency / microstructure-driven markets#LI-MC1

Logitech is the Sweet Spot for people who want their actions to have a positive global impact while having the flexibility to do it in their own way.The team and the role:The Personal Workspace Solution group from Logitech is committed to help people create and communicate their passion and work to the world, anytime anywhere. Putting users front and center, we strive to innovate and elevate their experiences. This is more than computer mice, keyboards, webcams and presentation remotes - it’s about enabling the future beyond todays tools and in a sustainable way. Everything goes through great design and exceptional user experience conveyed in great hardware and elevated by software.We are looking for an experienced Principle Image Engineer to join the team responsible for Logitech’s next-generation webcams. You will play a pivotal role in defining the visual experience of our products, taking them from initial concept through to mass production.In this role, you will be hands-on with our latest hardware architecture based on Sigmastar or other Embedded Linux / RTOS based SoC. You will be contributing to the tuning of the Image Signal Processor (ISP) for both RGB and IR sensors, ensuring we meet the rigorous standards required for Microsoft Teams, Zoom, and Windows Hello certifications amongst others. You will work in a fast-paced environment, leveraging our state-of-the-art video lab to validate performance against both subjective and objective metrics.You will stay on top of the latest innovation in both hardware for webcams (sensor, SoC, …) and equipment required to test and validate them. As standards for video are constantly evolving, you will monitor their evolution and identify opportunities for Logitech to retain its competitive edge.Your Contribution:Be Yourself. Be Open. Stay Hungry and Humble. Collaborate. Challenge. Decide and Do. These are the behaviors you’ll need for success at Logitech. In this role you will:Define the Visual Standard: You will take ownership of the webcam’s ISP pipeline, fine-tuning parameters (Black Level, Demosaic, Gamma, CCM, 3DNR) to transform raw sensor data into the crystal-clear, vivid video that defines the Logitech experience.Master the Light: You will calibrate and optimize the vendor-provided Auto Exposure (AE) and Auto White Balance (AWB) algorithms, ensuring our webcams adapt seamlessly to challenging lighting conditions—from dim home offices to harsh, backlit windows.Enable Secure Biometric Authentication: You will drive the tuning strategy for our IR sensors, prioritizing contrast, uniformity, and signal integrity to ensure flawless performance for Windows Hello facial recognition.Drive Certification Success: You will serve as the IQ lead for compliance, ensuring our products meet and exceed the objective testing criteria required for Microsoft Teams, Zoom and other communication platform certification.Champion Quality Assurance: You will utilize our video lab to execute a rigorous validation strategy, balancing objective data with subjective evaluations to deliver a product that feels as good as it measures.Architect the System: You will collaborate closely with Firmware engineers, Optical engineers, and other disciplines to integrate your tuning work into the Embedded Linux build, ensuring a cohesive and stable imaging system.Support qualification and preparation for MP: You will collaborate with FW/SW QA to ensure product quality during EVT, DVT, PVT stages. You will also work closely with TDEs to establish production test criterias and support debugging during pilot builds.Your theoretical knowledge and hands-on expertise in imaging will be applied to all Video components of the webcam system resulting in optimized and balanced performance.Key Qualifications:For consideration, you must bring the following minimum skills and behaviors to our team:Experience: 7 years of experience in Image Signal Processing (ISP) tuning for consumer electronics (Webcams, IP cameras, Action cameras/drones, or Dashcams).SoC Expertise: Hands-on experience tuning ISPs on embedded SoCs.Acceptable: Ambarella, Novatek, HiSilicon, Realtek, or QualcommA plus: SigmastarColor Science Mastery: Deep understanding of color science, radiometry, photometry, and camera optics. Familiarity with imaging standards, certification and organizations, Rec.709, BT.2020, Microsoft Teams, Zoom, Windows Hello, VCX, SPIE, ...3A Knowledge: Proven track record in tuning Auto Exposure and Auto White Balance parameters (convergence speed, stability, weighting tables).Lab Tools: Proficiency with image quality testing tools (Imatest, highly calibrated light sources, …) and familiarity with VCX testing protocols.OS Familiarity: Comfortable working in an Embedded Linux and RTOS environments (shell scripting, command line tools, interacting with V4L2 drivers).Education:MS Computer Science or equivalent with 15 years of relevant working experience in consumer electronics (Webcams, IP cameras, Action cameras/drones, or Dashcams)#LI-AL2/104Across Logitech we empower collaboration and foster play. We help teams collaborate/learn from anywhere, without compromising on productivity or continuity so it should be no surprise that most of our jobs are open to work from home from most locations. Our hybrid work model allows some employees to work remotely while others work on-premises. Within this structure, you may have teams or departments split between working remotely and working in-house.Logitech is an amazing place to work because it is full of authentic people who are inclusive by nature as well as by design. Being a global company, we value our diversity and celebrate all our differences. Don’t meet every single requirement? Not a problem. If you feel you are the right candidate for the opportunity, we strongly recommend that you apply. We want to meet you!We offer comprehensive and competitive benefits packages and working environments that are designed to be flexible and help you to care for yourself and your loved ones, now and in the future. We believe that good health means more than getting medical care when you need it. Logitech supports a culture that encourages individuals to achieve good physical, financial, emotional, intellectual and social wellbeing so we all can create, achieve and enjoy more and support our families. We can’t wait to tell you more about them being that there are too many to list here and they vary based on location.All qualified applicants will receive consideration for employment without regard to race, sex, age, color, religion, sexual orientation, gender identity, national origin, protected veteran status, or on the basis of disability.If you require an accommodation to complete any part of the application process, are limited in the ability, are unable to access or use this online application process and need an alternative method for applying, you may contact us toll free at 1-510-713-4866 for assistance and we will get back to you as soon as possible.

品牌優勢： 台灣 SaaS 領導品牌，市場關注度高。實戰能量： 深度參與法說會籌辦、年報編製及法規申報，累積紮實 IR 功力。國際視野： 需處理英文簡報與外資溝通，強化職場競爭力。資訊揭露與申報：執行各類法定資訊揭露作業，確保申報時效與內容符合證交法規。法說會與溝通支援：協助主管籌辦法人說明會、投資人會議，並負責會後會議紀錄與追蹤。文件製作與彙整：負責編製年報、股東會議事手冊等 IR 文件，及法說會簡報之初稿製作。數據蒐集與分析：蒐集同業資訊、監測市場趨勢與股價異動，提供主管分析使用。

【工作內容】 1. 集團財務策略與資本管理 • 制定集團財務策略、資本配置與資金運用計畫 • 規劃年度預算、現金流管理、營運風險管控 • 協助推動資本市場、融資、增資或治理相關議題（如有需要） 2. 財務報表與內控治理 • 依 IFRS 與上市櫃規範，負責財務報表、稅務與合併報表 • 建立與優化內部控制制度，強化跨國據點的財務治理 • 與會計師、法律顧問、銀行與監理單位溝通協作 3. 營運財務與管理會計 • 進行營運績效分析（KPI、成本、毛利、預算差異） • 與製造、採購、供應鏈合作，提升營運效率與成本競爭力 • 建置財務預警與營運分析機制，支援決策制定 4. 投資、併購與策略合作 • 評估投資案、併購案、策略合作案之財務可行性 • 進行企業價值評估（DCF、Comparable、Transaction 等） • 協助維繫投資人關係（IR）與法人溝通 • 全球布局 5. 團隊管理與跨國協作 • 帶領台灣/海外財會團隊，提升組織能量 • 推動數位財務（ERP、BI、RPA 等）優化專案 • 建立財務人才發展與跨國管理制度

Performs tasks such as, but not limited to, the following:* Lead thermal evaluations for new products, design decisions, and risk mitigation.* Guide thermal management in DFx, PCB layout, and heat dissipation design (compliance with ASHRAE, NEBS).* Collaborate with cross-functional teams (design, manufacturing, quality, reliability) to solve thermal issues.* Drive root cause analysis with CFD simulations; manage failure analysis at manufacturing sites.* Lead verification plans for certification programs; review reliability test results.* Develop thermal testing standards; guide team in using thermal testing tools (thermocouples, IR cameras, wind tunnels).* Support thermal certification of second-source components; review heat dissipation compatibility.* Participate in factory readiness and production line thermal setup.* Coordinate cross-project resources (equipment, manpower) to avoid conflicts.* Conduct training, build knowledge base, and share best practices on thermal debugging.* Research next-gen cooling technologies (liquid cooling, AI workload thermal management) and evaluate feasibility.

– Responsible for the full physical design cycle from Synthesis to GDSII – Perform tasks like Synthesis, floor-planning, placement, CTS, routing, and timing analysis – Perform the signoff check like: STA/ EMIR (IR, DvD, P-EM, S-EM)/ PV(LVS/ANT/DRC/DFM) /Low power check ... tape-out procedures – Ensure the design meets performance, power, and area constraints – Utilize Electronic Design Automation (EDA) tools for design, simulation, and verification – Work closely with stakeholders like: Design team, constraint team, DFT team, DV team, IP team to ensure the physical layout meets design specifications – Perform physical verifications such as layout versus schematic (LVS) and design rule checking (DRC) – Conduct parasitic extraction and analysis to optimize the performance of the IC – Resolve design and flow issues related to physical design, identify potential solutions, and drive execution – Optimize designs for power, area, and performance – Stay up to date with the latest technology trends (7nm/5nm/3nm and beyond), industry standards, and EDA tools – Conduct logic synthesis, floor planning, power and clock distribution, timing optimization, signal integrity and place and route – Work closely with team members to resolve design and flow