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Provide day-to-day technical support to end users and ensure the smooth running of computers, network devices and printersTroubleshoot and resolve end user application issues, maintain and update technical support documentationHandle asset management, maintain inventory and liaise with vendorsMaintain and monitor office network infrastructure, IT security and antivirus toolsOther duties include performing first level troubleshooting and support for scheduled server backups, system monitoring and reportsWork on shift of follow by Team lead arrange

1. Data Analytics Problem SolvingAnalyze operational and network data (volume, capacity, productivity, cost) to identify gaps and improvement opportunities.Develop simulation or capacity models to support decision-making on network expansion, warehouse layout, and space utilization.Prepare data-driven business cases for infrastructure investment.Provide insights to optimize hub/SOC performance and long-term infrastructure planning.2. Logistics Solution DesignCollaborate with Operations, OPEX to design optimal Logistics solutions to enhance First-Last Mile Hub Capacity Efficiency.Translate operational requirements into practical solution design and equipment solutions.Evaluate and propose logistics innovations that improve efficiency, reduce cost, and enhance workplace safety.3. Project Management ImplementationLead end-to-end infrastructure projects — from planning, budgeting, execution, to handover.Coordinate with internal stakeholders (Ops, HSE, Procurement, Landlord, Vendor) to ensure project delivery on time and within budget. 

WorldQuant develops and deploys systematic financial strategies across a broad range of asset classes and global markets. We seek to produce high-quality predictive signals (alphas) through our proprietary research platform to employ financial strategies focused on market inefficiencies. Our teams work collaboratively to drive the production of alphas and financial strategies – the foundation of a balanced, global investment platform. WorldQuant is built on a culture that pairs academic sensibility with accountability for results. Employees are encouraged to think openly about problems, balancing intellectualism and practicality. Excellent ideas come from anyone, anywhere. Employees are encouraged to challenge conventional thinking and possess an attitude of continuous improvement. Our goal is to hire the best and the brightest. We value intellectual horsepower first and foremost, and people who demonstrate an outstanding talent. There is no roadmap to future success, so we need people who can help us build it.Technologists at WorldQuant research, design, code, test and deploy firmwide platforms and tooling while working collaboratively with researchers. Our environment is relaxed yet intellectually driven. We seek people who think in code and are motivated by being around like-minded people. The Role: We're seeking a Senior Site Reliability Engineer to join the team. You will build and operate the infrastructure and tooling behind WorldQuant's data ingestion pipelines — systems that onboard, validate, and deliver large-scale datasets to the firm's research platform.This is a 70% build / 30% operate role. You'll spend most of your time engineering automation, observability, and developer tooling, while also participating in on-call rotations and incident response for production data pipelines. You'll partner with engineering, analyst, and research teams to ensure reliability at scale — this requires excellent analytical skills, clear communication, and the ability to collaborate across teams. What You'll Do: Build (70%): Design and develop automation, monitoring, CI/CD, and reliability features for the data onboarding pipeline Develop and maintain internal infrastructure and services that reduce toil and improve pipeline reliability Build observability solutions — dashboards, alerting, log aggregation — using Grafana, the ELK stack, and Vector Design and implement CI/CD pipelines, test automation, and release management workflowsWrite infrastructure-as-code for provisioning, scaling, and managing platform components: Kubernetes, bare metal hosts Integrate and extend tools such as Redis, Celery, MySQL Operate (30%): Keep production data pipelines healthy and respond to incidents Participate in on-call rotation, respond to production incidents, and drive post-mortems Define and track SLOs/SLIs for pipeline reliability, latency, and data freshness Diagnose platform performance and reliability issues, driving them to root cause Create and maintain runbooks for common operational scenarios Plan capacity and optimize resource utilization What You'll Bring 8+ years of experience in SRE, DevOps, or platform engineering roles Linux expertise: Power user proficiency in Linux with ability to manage infrastructure, deploy services, and troubleshoot production systems Python proficiency: Strong scripting and automation skills; experience building CLI tools, API clients, monitoring integrations, and operational tooling in Python Kubernetes containers: Deep hands-on experience with Kubernetes — deploying, scaling, debugging, and managing production workloads. Familiarity with Helm, resource management. Solid experience with Docker Observability: Hands-on experience with monitoring stacks — Grafana, Prometheus, ELK (Elasticsearch, Logstash, Kibana), or similar. Experience designing dashboards, alerts, and SLO-based reliability tracking CI/CD infrastructure-as-code: Experience designing and maintaining CI/CD pipelines (GitLab CI, or similar), including test automation and release management. Familiarity with Ansible or similar IaC tools Databases: Working knowledge of relational databases (MySQL/PostgreSQL), query tuning, and operational database management Message queues streaming: Experience with Kafka, Redis pub/sub, or Celery for event-driven architectures Networking APIs: Understanding of network fundamentals, DNS, load balancing, and REST/gRPC APIs Incident management: Experience with on-call rotations, incident response, post-mortems, and runbook-driven operations Leadership management: Proven track record of leading a team — mentoring engineers, driving technical roadmaps, coordinating cross-team initiatives, and managing priorities. Comfortable owning team delivery and representing the team to stakeholders AI-agent readiness: Openness to working alongside AI coding agents and LLM-powered tools as part of the development and operations workflow — treating AI as a force multiplier for automation, incident analysis, and toil reduction Nice to Have: Cloud platforms: Exposure to GCP or AWS for compute, storage, and managed services Data tools: Familiarity with Apache Arrow, gRPC, or columnar data formats Big data platforms: Familiarity with Hadoop or Apache Spark for large-scale data processing Programming languages: C/C++, Golang, Scala, JavaScript Financial services or data-intensive industry background SRE culture: Familiarity with Google's SRE book principles — error budgets, toil tracking, blameless post-mortems What We Offer: Competitive and attractive compensation package with clear career road-map – where you feel challenged everyday We offer a strong culture of learning and development: training courses, library, speakers, share and learn events Learn from who sits next to you! Working in WQ you are surrounded by smart and talented people Premium Health Insurance and Employee Assistance Program Generous time-off policy, re-creation sabbatical leave (based on tenure), Trade Union benefits for staff and family Team building activities every month: Local engagement events, Employee clubs: football, ping-pong, badminton, yoga, running, PS5, movies, etc. Annual company trip and occasional global conferences – opportunity to travel and connect with our global teams Happy-hour with tea break, snacks and meals every day in the office! #LI-QM1 By submitting this application, you acknowledge and consent to terms of the WorldQuant Privacy Policy. The privacy policy offers an explanation of how and why your data will be collected, how it will be used and disclosed, how it will be retained and secured, and what legal rights are associated with that data (including the rights of access, correction, and deletion). The policy also describes legal and contractual limitations on these rights. The specific rights and obligations of individuals living and working in different areas may vary by jurisdiction. Copyright © 2025 WorldQuant, LLC. All Rights Reserved.WorldQuant is an equal opportunity employer and does not discriminate in hiring on the basis of race, color, creed, religion, sex, sexual orientation or preference, age, marital status, citizenship, national origin, disability, military status, genetic predisposition or carrier status, or any other protected characteristic as established by applicable law.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com. Job Summary: We are seeking a highly motivated and detail-oriented Analog Mixed-Signal CAD Engineer to join our design automation team. In this role, you will develop, maintain, and support CAD tools and design flows for analog and mixed-signal IC design. You will work closely with circuit designers, layout engineers, and EDA vendors to ensure efficient and robust design environments. Key Responsibilities: Develop and maintain analog/mixed-signal design flows using industry-standard EDA tools (Cadence Virtuoso, Spectre, etc.). Automate design tasks using scripting languages (e.g., Python, SKILL, Tcl, Perl). Support schematic, layout, simulation, and verification environments. Collaborate with design teams to understand requirements and improve design productivity. Integrate and validate PDKs (Process Design Kits) and technology files. Provide documentation, training, and support for CAD tools and flows. Interface with EDA vendors to evaluate and deploy new tools and features. Monitor and resolve CAD tool issues, ensuring high availability and performance. Required Qualifications: Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field. 3+ years of experience in analog/mixed-signal CAD or EDA tool development. Strong knowledge of analog/mixed-signal IC design methodologies. Proficiency in scripting languages such as SKILL, Python, Tcl, or Perl. Experience with Cadence Virtuoso, Spectre, and AMS simulation environments. Familiarity with PDK integration and technology file management. Excellent problem-solving, communication, and teamwork skills. Preferred Qualifications: Experience with digital-on-top (DoT) or mixed-signal verification flows. Knowledge of version control systems (e.g., Git, Perforce). Familiarity with Unix/Linux environments and shell scripting. Exposure to advanced process nodes (e.g., 7nm, 5nm). We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com. Job Summary: We are seeking a talented Senior Design Verification Engineer to join our team. The ideal candidate will play a key role in verifying the functionality and performance of our digital and mixed-signal designs. You will work closely with the design and development teams to create and execute comprehensive verification plans, ensuring the robustness and reliability of our products. Key Responsibilities: Develop and implement test plans and testbenches for verification of sub-blocks in high-speed Ethernet, UALink, PCIE PHY (64b/66b Encoder/Decoder, FEC encoder/decoder, DSP, FFE, DFE, MLSD). Identify, document, and debug functional issues found during verification, collaborating with design engineers for resolution. Develop and apply coverage models to ensure thorough validation of the design. Work closely with architects, designers, and software teams to comprehend the design architecture and contribute to high-level verification strategy. Stay up-to-date with industry best practices and emerging tools for design verification. Qualifications: Bachelor’s in Electrical Engineering, Computer Engineering, or a related field. 2+ year of experience in DV. Strong proficiency in verification languages such as System Verilog, UVM (Universal Verification Methodology). Experience with simulation tools (e.g., Cadence Xcelium, Synopsys VCS, or Mentor Graphics QuestaSim). Familiarity with scripting languages such as Python, Perl, or Shell scripting for automation purposes. In-depth understanding of digital design principles, verification methodologies, and industry-standard protocols. Excellent analytical, debugging, and problem-solving skills. Strong teamwork and communication abilities. Pay and Benefits Competitive salary. Performance bonus each year. Flexible working time. Health check each year. Insurance for engineer and family. Lunch Allowance. Company trips. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.The company seeks a highly motivated and team-oriented individual to work with both layout and design engineers across multiple time zones As an Integrated Circuit Designer - Layout, you will be part of a key team designing and developing sophisticated advanced node CMOS products. Key Job Duties: The design and development of the layout for integrated circuits according to electronics engineering principles, using software to create design schematics and diagrams. This will include [floor planning, creating layouts of building blocks and integrating layouts for circuits such as PLL, DLL, ADC, regulators, amplifiers, TX, RX, and CDRs in advanced CMOS nodes. Your focus will include minimizing parasitic and skew, matching, EMIR, and antenna rules on top of DRC and LVS] The management of manufacturing process of the products, including technology yield and performance of the products. The development of test programmes and procedures to ensure the products meet their performance specifications. The provision of advice on aspects of semiconductor process technology and maintain and repair semiconductor process equipment. Basic Qualifications: At least a bachelor’s degree in electrical engineering Required Experience: 4+ years of experience in the development of layouts for highspeed analog IC designs in fin FET technology. Experience with layout extraction tools and to analyzing layout parasitic to achieve high quality layout for highspeed circuits. EMIR and antenna DRC rules aware layout practices. Experience writing SKILL and TCL scripts is highly recommended Pay and Benefits Competitive salary. 13th month salary. Performance bonus each year. Long Term Incentive (LTI) Health check each year. Insurance for engineer and family. Lunch Allowance. Company trips. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact Marvell Technology, Inc. is a data infrastructure semiconductor solutions provider. The Company is principally engaged in delivering the data infrastructure technology that connects the world. The Company moves, stores, processes and secures data with semiconductor solutions designed for its customer needs. The Company is engaged in providing high-speed analog and mixed signal semiconductor solutions and optical interconnects for communication infrastructure in long-haul, metro, datacenter for cloud markets. We address the bandwidth, capacity and power issues faced by cloud computing, mega data center from 10Gig to multi-hundred-Gig (100G) network environments. By leveraging our core competencies in advanced analog circuit design, advanced DSP (Digital Signal Processing), advanced packaging and process technologies, the company’s products being first to market in many of key areas, including opto-electronics and DSP based transceivers providing most advanced chips and subsystems solutions to address today’s and future’s multi-100Gig interconnect requirements for the ever-increasing demand of higher data rates. We are seeking talented individuals to work on solving technical challenges with the most outstanding group of collaborators in the industry. Join our team of experts and make a difference in an exciting career opportunity. What You Can Expect Create, define and develop validation and test plans for Chip level silicon validation/characterization on Marvell’s internal IPs used for High-Speed SerDes, key IPs such as PLL, Equalizer and high performance ADC, Serializer, DAC and Driver, BandGap/RefGen, Temperature sensor and others. Responsibility to implement the bench automation in Python to execute automatic data collection both using standard bench equipment and customized toolsets. Responsibility for the test setup and debug of failures. Requires understanding of system areas and interfaces with Architecture, Design, and Pre-silicon Validation High level overview and ability to understand end-to-end system scenarios. Detailed responsibilities include: Working with IP design team to define test specification arm to fully cover all items needed for IP validation and characterization.Responsible for device controlling SW (knowledge of Python, C++, Matlab, Excel VBA is a plus).Data analysis and silicon test report.Provide IP debugging support to SoC teamsProvide IP usual training to Marvell’s internal FAE.Work with IP design team on new chip features, definitions, and bring-upDevelop technical collateral such as application notes, user guides, data sheet What We're Looking For Bachelor’s/Master’s degree in Electrical engineering, Electronics and Communication engineering, Computer Science, Math, Physics, or related fields, 3-5 years of industry experience.Good fundamental knowledge in analog/digital circuit and data communication system.Working experience or knowledge in semiconductor chip lab testing and measurement, test script development, familiar with electronic test equipment.Working experience or knowledge in any of the following SerDes technologies is preferred. PCI Express, Ethernet, USB, SATA, SAS, CPRI, JESD, etc.Good communication skills in English and capable of independent work with less guidance.Thoughtful and perceptive analytical skills, logical thinking.Dedicated and committed to creative problem solving and getting things done.Prior experience in in HW validation, HW-SW integration, develop test plans for networking system features (Nice to have)Knowledge of high frequency lab instruments like DSO, SSA, VNA… (Nice to have) Additional Compensation and Benefit Elements Competitive salary, plus 13th-month salary and performance-based bonusRSUs (Restricted Stock Units) for new joiners and on-going annuallyPremium health accident insurance for you and your family (spouse and children)Annual medical check-up at a designated hospital arranged by MarvellGenerous paid leave policies: 15 annual leave days, 3 Recharge periods per year (company-wide off-work from Friday to Monday), 5 paid sick leave days, 3 days of volunteer time-off and 11 public holidaysExciting Employee Events: Participate in fun activities throughout the year such as team birthdays, sports tournaments, company trips, mid-autumn, appreciation week, charity, health seminars, year-end party, and more. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. Interview Integrity To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews. These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process. This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.We are seeking an experienced Analog/Mixed-Signal (AMS) Circuit Design Engineer to join our high-performance design team working on next-generation transceiver IPs targeting the TSMC 5/3nm technology node. In this role, you will design high-speed analog and mixed-signal circuits used in multi-gigabit transceivers, collaborating with layout, verification, and system teams to ensure robust performance, power efficiency, and successful silicon validation at advanced process nodes. Key Responsibilities Design critical AMS blocks such as PLLs, CDRs, LDOs, bias generators, and ADC/DAC components for wireline transceivers. Perform transistor-level design, simulation, and optimization for performance, power, and area across process, voltage, and temperature (PVT) corners. Work closely with layout engineers to guide floorplanning, matching-sensitive layout, and parasitic-aware design. • Perform design verification using pre- and post-layout simulations (transient, AC, noise, Monte Carlo, corner sweep). Ensure robust operation under variation, jitter, power supply noise, and crosstalk conditions. Create and maintain design documentation, design reviews, and specifications Collaborate with system architects, digital design, and firmware teams to define and optimize mixed-signal interface behavior. Support silicon bring-up, lab measurement correlation, and debug of design issues. Use industry-standard tools (e.g., Virtuoso, Spectre, HSPICE, ADE, MATLAB, Python) for design and analysis. Required Qualifications Bachelor’s or Master’s degree in Electrical Engineering, Microelectronics, or related field. 5+ years of experience in analog/mixed-signal circuit design in deep-submicron or FinFET technologies. Strong experience with: Transistor-level design and simulation in advanced nodes (≤ 5nm). Designing analog blocks for high-speed transceivers (e.g., clocking, bias, analog front ends). SPICE simulation tools and AMS verification environments. Deep understanding of noise, jitter, linearity, bandwidth, gain, impedance matching, and power trade-offs. Familiarity with layout interaction and parasitic-aware circuit optimization. Solid debugging, problem-solving, and documentation skills. Benefits Competitive salary 13th month salary Performance bonus each year Flexible working time Health check each year Insurance for engineer and family Lunch Allowance Company trips. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Lead technical strategy and implementation across the trucking ecosystem including Petrol station, Maintenance Workshop/ Garage, EV vehicles, charging infrastructure, telematics, and fleet systemsProvide technical expertise on vehicle systems, maintenance requirements, safety standards, and operational risks.Work closely with engineering, operations, procurement, and external vendors to ensure technical feasibility and performance.Troubleshoot complex technical issues related to vehicle performance, maintenance, charging, and fleet operations.Define and standardize preventive maintenance SOPs, frameworks, ensuring optimal vehicle lifecycle management and minimizing downtime across the fleet.Monitor and improve key technical metrics such as maintenance cost per km, vehicle reliability, fuel or energy efficiency, and asset performance.Evaluate new technologies (battery systems, telematics, vehicle hardware/software) to improve operational efficiency.Support business teams with technical input for new projects and partnerships.Act as internal expert on Vietnam transport regulations, maintaining forward-looking visibility on policy changes impacting fleet operations and planning.Translate regulatory changes into actionable fleet strategies, including asset mix adjustments, route redesign, and compliance risk mitigation plans.Continuously explore and pilot innovative vehicle types, including specialized delivery vehicles and emerging formats suited for urban and middle-mile logistics.

We seek an experienced Analytics Engineer who will be in charge of (1) building automation solutions for analytics processes; and (2) optimization and maintenance of local data pipelines to ensure analytics efficiency and governance.  The Analytics Engineer will work closely with Functional BI teams and business users to understand the data logic and workflow, then architect and build solutions to automate the data flow and manual tasks.  AutomationPartner closely with stakeholders across business units and Functional BI teams to understand their challenges and translate requirements into technical solutionsDrive process automation by developing intelligent tools for eKYC processing, tax validation, and other critical business operationsData EngineeringBuild robust data foundations by designing and implementing scalable ETL processes that seamlessly extract, transform, and load data from our internal platformsArchitect data pipelines that integrate smoothly with existing systems and power automated workflows across the businessOptimize data infrastructure including local tables, data models, and data mart architecture for peak performance and reliabilityAnalytics Modelling Implementation and MaintenanceImplement and maintain predictive analytics and automated data processing solutionsWrite SQL queries and Python code that support features engineering and EDA in complex datasetsData Quality and GovernanceMaintain code quality through disciplined source control practices, branch management, and collaborative code reviewsEnsure system reliability by monitoring, troubleshooting, and optimizing data pipeline performance