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What this role owns: Hands-on security for mobile apps and web services. You run penetration tests, review source code, build threat models, and produce actionable fixes that engineers can implement. You also create standards, automate tests in CI, and run training for engineering teams. Mô tả công việcKey ResponsibilitiesPerform penetration tests for mobile and web applications.Review code to identify security vulnerabilities and recommend fixes.Develop threat models for new features and workflows.Analyze application flows and identify attack vectors (tampering, hooking, jailbreak/root bypass, emulator detection, etc.).Research emerging vulnerabilities, exploit techniques, and tools.Document findings and deliver clear remediation guidance to engineering teams.Support post-incident analysis and root-cause reviews.Build internal security guidelines and secure coding standards.Train engineering teams on security best practices and secure SDLC.Yêu cầu công việcRequirementsBachelor's degree in Information Security, Computer Science, or related field.Proven experience in application penetration testing (mobile + web).Practical source code review experience and secure coding knowledge.Hands-on experience with testing frameworks such as the PTES and OWASPIn-depth knowledge of application development processes and at least one programming or scripting language (e.g., Java, Scala, C#, Ruby, Perl, Python, PowerShell)Passion to learn and explore.PreferredExperience with exploit development, vulnerability research or fuzzing.Fintech or payment industry security experience.

Google welcomes people with disabilities.Note: By applying to this position you will have an opportunity to share your preferred working location from the following: New Taipei, Banqiao District, New Taipei City, Taiwan; Zhubei, Zhubei City, Hsinchu County, Taiwan.Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 8 years of experience in functional verification, performance validation, developing test plans and diagnostic codes of modern processors. Experience with processor microarchitecture. Preferred qualifications: Master degree in Electrical Engineering, Computer Science or related fields. Experience with UVM, SystemVerilog, or other scripting languages such as Python, Perl, Shell, Bash, etc. Experience with ARM Instruction Set Architecture. Knowledge of general purpose operating systems such as Linux and Android. About the jobBe part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.Responsibilities Design verification for future CPU developments. Build functional verification infrastructure, the infrastructure will include unit, multi-unit, core, and subsystem level verification environments. Produce diagnostic code repositories that sufficiently enable production of quality CPU’s. Verify and validate performance for both pre-silicon and post-silicon. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.About the Role We are seeking a Principal CAD Engineer to architect, build, and maintain an integrated CAD infrastructure that enables seamless collaboration across analog/mixed-signal (AMS), digital RTL, physical design, and verification/validation teams. You will be the technical owner for cross-domain design environments ensuring reliability, scalability, and reproducibility across IP and SoC programs. This role combines EDA flow knowledge, and methodology knowledge. You will partner with design and verification leaders to define best practices, establish flows, and deliver a first-class designer experience from concept to tape-out. Key Responsibilities CAD tools Ownership Flow Development and Methodology Compute infrastructure and Automation Cross-Functional Enablement and Support Tape-out Readiness and Sign-off Required Qualifications Experience 10+ years in CAD/EDA methodology development for IP/SoC programs across AMS and digital domains (advanced nodes preferred: 7 nm → 3 nm or equivalent). Deep hands-on expertise with major EDA ecosystems (Cadence, Synopsys, Siemens). Strong scripting/automation: Python, Perl, shell scripting, Cadence Skill, Tcl HPC experience: LSF/SLURM, license servers monitoring/logging. Version control and data management: Git/Perforce Understanding of timing verification, SI, EM/IR, physical verification, library/PDK fundamentals, and foundry deliverables. Core Competencies Skills End-to-end flow integration across AMS, digital, PD, and verification disciplines. Performance tuning: distributed resource management, memory/CPU/GPU utilization, and license efficiency. Ability to abstract complex flows into modular components and standard interfaces. Influence across organizations; mentor junior CAD engineers and power users. Clear documentation, and effective training for current and new team members. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com. Basic qualifications: Strong academic and technical background in electrical engineering. A Bachelor’s degree in EE / Computer is required, and a Master’s degree is preferred. ≥10 years’ experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications. Professional attitude with the ability to prioritize a dynamic list of multiple tasks, plan and prepare for customer meetings in advance, and work with minimal guidance and supervision. Entrepreneurial, open-mind behavior and can-do attitude. Think and act fast with the customer in mind! Required experience: Hands-on and thorough knowledge of synthesis, place and route, CTS, extraction timing analysis/STA, Physical Verification and other backend tools and methodologies for technologies 16nm or less, preferably 7nm or less. Proven expertise in synthesis, timing closure and formal verification (equivalence) at the block and full-chip level. Full chip or block level ownership from architecture to GDSII, driving multiple complex designs to production. Experience with Cadence and/or Synopsys physical design tools/flows. Familiarity and working knowledge of System Verilog/Verilog. Experience with DFT tools and techniques. Experience in working with IP vendors for both RTL and hard-mac blocks. Good scripting skills in python or Perl Preferred : Good knowledge of design for test (DFT), stuck-at and transition scan test insertion. Familiarity with DFT test coverage and debug. Familiarity with ECO methodologies and tools. Your base salary will be determined based on your experience, and the pay of employees in similar positions. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. 4 years of experience with digital logic design principles, RTL design concepts, and languages, such as Verilog or SystemVerilog. Experience with logic synthesis techniques to optimize RTL code, performance and power, as well as low-power design techniques. Preferred qualifications: Master's or PhD degree in Electrical Engineering, Computer Engineering, or Computer Science. Experience with a scripting language like Perl or Python. Experience with ASIC or FPGA design verification, synthesis, timing/power analysis, and DFT. Knowledge of high-performance and low-power design techniques, assertion-based formal verification, FPGA and emulation platforms, and SOC architecture. Knowledge of memory compression, fabric, coherence, cache, or DRAM. About the jobBe part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. The Platforms and Devices team encompasses Google's various computing software platforms across environments (desktop, mobile, applications), as well as our first party devices and services that combine the best of Google AI, software, and hardware. Teams across this area research, design, and develop new technologies to make our user's interaction with computing faster and more seamless, building innovative experiences for our users around the world.Responsibilities Define the block-level design document (e.g., interface protocol, block diagram, transaction flow, pipeline, etc.). Perform RTL coding, function/performance simulation debug, and Lint/Clock Domain Crossing (CDC)/Formal Verification (FV)/Unified Power Format (UPF) checks. Participate in synthesis, timing/power closure, and FPGA/silicon bring-up. Participate in test plan and coverage analysis of the block and ASIC-level verification. Communicate and work with multi-disciplined and multi-site teams. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.

Minimum qualifications: Bachelor's degree in Computer Science, Electronics or Electrical Engineering, or equivalent practical experience. 8 years of experience in DFT/DFD flows and methodologies. Experience with DFT EDA Tool Tessent/Genus/FC/Simvision, etc. Experience with scan insertion, ATPG, gate level simulations and silicon debug, low power designs, BIST, JTAG, IJTAG tools and flow. Preferred qualifications: Experience with industry DFT, MBIST, and ATPG tools. Knowledge of high performance design DFT techniques like SSN, HighBandwidth IJTAG. Understanding of the end to end flows (e.g., design, verification, DFT and PD phases in a SOC cycle). Proficiency with IJTAG ICL, PDL terminology, ICL extraction, ICL modeling with Siemens Tessent Tool. Proficiency with a scripting language such as Perl or Python. About the jobBe part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.Responsibilities Collaborate with a team of DFT engineers, working closely with RTL, Physical Design, SoC DFT, and Product Engineering teams. Architect SoC and Subsystem Memory Built-In Self-Test (MBIST) structures across multiple voltage and power domains. Drive cross-functional design efforts regarding memory repair methodology and system-level integration. Own Gate-Level Simulation (GLS) verification and debug sign-off, ensuring total functional and timing coverage. Develop MBIST TbGen, pattern generation, and DFT simulation flows, including scripting to automate and optimize the DFT environment. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.

Google welcomes people with disabilities.Minimum qualifications: Bachelor’s degree in Electrical or Electronics Engineering, or equivalent practical experience. 2 years of experience in SoC Software, Architecture, or hardware validation, with mobile, Internet of Things (IoT), or consumer electronics. Experience with coding languages such as Python, Bash, or Perl for automating data collection, analysis, and report generation. Preferred qualifications: 4 years of experience in SoC Software, Architecture, or hardware validation, with mobile, Internet of Things (IoT), or consumer electronics. Experience in using lab test equipment like oscilloscopes, electronic loads, and network analyzers for mixed-signal validation. Experience with hardware, including working with pre-production silicon and evaluation platforms in a lab setting. Knowledge in working of operating systems (e.g., Android/IoS/Linux), including how OS interacts with the SoC's hardware for memory management, power management, and scheduling. About the jobBe part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. The Google Pixel team focuses on designing and delivering the world's most helpful mobile experience. The team works on shaping the future of Pixel devices and services through some of the most advanced designs, techniques, products, and experiences in consumer electronics. This includes bringing together the best of Google’s artificial intelligence, software, and hardware to build global smartphones and create transformative experiences for users across the world.Responsibilities Conduct technical and market-based analysis of System on a Chip (SoCs), covering areas such as architecture, performance, features, and cost. Lead technical tear-downs and benchmark activities to gather detailed intelligence on participants products. Develop and maintain engaging intelligence reports, including market landscapes, product roadmaps, and feature comparisons. Collaborate with cross-functional teams, including engineering, marketing, and business to support product planning and Go-to-Market (GTM) strategies. Monitor industry trends, emerging technologies, and participants moves to provide analysis. Use data analysis tools and techniques to reconcile datasets and deliver insights. Maintain and update internal engaging databases and repositories of technical information. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.

Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 8 years of experience with digital logic design principles, RTL design concepts, and languages, such as Verilog or SystemVerilog. Experience with logic synthesis techniques to optimize RTL code, performance and power, as well as low-power design techniques. Preferred qualifications: Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science. Experience with a scripting language like Perl or Python. Knowledge in one or more of these areas: Process Cores, Interconnects, Debug and Trace, Security, Interrupts, Clocks/Reset, Power/Voltage Domains, Pin-muxing. About the jobBe part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. The Platforms and Devices team encompasses Google's various computing software platforms across environments (desktop, mobile, applications), as well as our first party devices and services that combine the best of Google AI, software, and hardware. Teams across this area research, design, and develop new technologies to make our user's interaction with computing faster and more seamless, building innovative experiences for our users around the world.Responsibilities Define the microarchitecture for Intellectual Property (IP) blocks, subsystems, and Systems-on-Chip (SoCs), collaborating with cross-functional teams to deliver high-quality designs that meet strict schedules and optimized Power, Performance, and Area (PPA). Work closely with the cross-functional team of Verification, Design for Test, Physical Design and Software teams to make design decisions and represent project status throughout the development process.  Define the block level design document such as interface protocol, block diagram, transaction flow, pipeline, etc.  Perform RTL coding for Subsystem (SS) and System-on-Chip (SoC) integration, function/performance simulation debug, Lint, Clock Domain Crossing (CDC), Formal Verification (FV), and Unified Power Format (UPF) checks. Ability to utilize key design collaterals, specifically Synopsys Design Constraints (SDC) and Unified Power Format (UPF), while collaborating with stakeholders to disscuss quality standards and develop technical workarounds for integration issues. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.Staff Physical Design Engineer About the Role We are seeking a Staff Physical Design Engineer to join our high-performance design team working on next-generation transceiver IPs targeting the TSMC 5nm, 3nm technology node. In this role, you will take ownership of physical implementation from RTL to GDSII, ensure timing and power closure for ultra-high-speed designs, and collaborate closely with cross-functional teams to resolve challenges unique to advanced nodes and multi-gigabit transceiver architectures. Key Responsibilities Perform full-chip and block-level physical implementation including floor planning, placement, clock tree synthesis (CTS), routing, and physical verification for high-speed designs in TSMC 3nm. Collaborate with RTL and STA teams to ensure clean handoffs and convergent timing, area, and power. Work on advanced physical design techniques to support multiple voltage/frequency domains, hierarchical design, and physical-aware synthesis. Handle advanced physical design topics: EM/IR analysis and power grid optimization Congestion analysis and mitigation Clock domain crossing and skew optimization RC extraction-aware placement and routing Integrate IPs and top-level blocks with attention to physical interfaces, constraints, and timing alignment. Participate in defining floorplan strategy and chip partitioning for multi-gigabit transceivers. Perform ECO implementation and support tapeout signoff activities. Ensure DRC/LVS/ANT/CELL/ERC clean database using industry-standard physical verification tools. Use industry-standard tools (e.g., ICC2, Innovus, Voltus, RedHawk, Calibre) for implementation and signoff. Develop and maintain automation scripts (Tcl, Python, Perl) for physical design flows and regressions. Required Qualifications Bachelor’s or Master’s degree in Electrical Engineering, Electronics Engineering, or related field. 4+ years of experience in physical design with advanced technology nodes (preferably ≤ 5nm). Strong experience with: Floor planning, placement, CTS, routing, and IR drop mitigation Signoff checks (DRC/LVS/ANT/ERC) and debugging Timing closure collaboration with STA team Hands-on experience with tools such as Synopsys ICC2, Cadence Innovus, Calibre, Voltus. Experience in integrating high-speed IPs (e.g., SerDes, PHYs) into SoC or chiplet environments. Experience in high frequence data path, DSP designs. Solid scripting skills for automation and productivity enhancement. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. 4 years of experience with digital logic design principles, RTL design concepts, and languages, such as Verilog or SystemVerilog. Experience with logic synthesis techniques to optimize RTL code, performance and power, as well as low-power design techniques. Preferred qualifications: Master's or PhD degree in Electrical Engineering, Computer Engineering, or Computer Science. Experience with a scripting language like Perl or Python. Experience with ASIC or FPGA design verification, synthesis, timing/power analysis, and DFT. Knowledge of high-performance and low-power design techniques, assertion-based formal verification, FPGA and emulation platforms, and SOC architecture. Knowledge of memory compression, fabric, coherence, cache, or DRAM. About the jobBe part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. In this role, you will be a part of the team which designs the SoC and Subsystem. You will be working through all phases of design and implementation. You will be working with architects to come up with microarchitecture specifications. You will use your logic design skills to convert the micro-arch into System Verilog code. You will be involved in Power, Performance and Area (PPA) experiments/prototyping experiments early on to optimize PPA. You will also work closely with the verification team to verify the features implemented in design. You will also work with the Physical Design (PD) team to take the design through the PD cycle and eventual tape-out.The Platforms and Devices team encompasses Google's various computing software platforms across environments (desktop, mobile, applications), as well as our first party devices and services that combine the best of Google AI, software, and hardware. Teams across this area research, design, and develop new technologies to make our user's interaction with computing faster and more seamless, building innovative experiences for our users around the world.Responsibilities Define the block-level design document (e.g., interface protocol, block diagram, transaction flow, pipeline, etc.). Perform RTL coding, function/performance simulation debug, and Lint/CDC/FV/UPF checks. Participate in test plan and coverage analysis of the block and ASIC-level verification. Communicate and work with multi-disciplined and multi-site teams. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.