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Company Overview This opportunity is with a top-tier RD division backed by a globally recognized technology group, focusing on next-generation AI and robotics innovation. The team works on cutting-edge domains such as Autonomous Systems, Embodied AI, and Cyber-Physical Systems. Operating with the agility of a startup and the resources of a large enterprise, the organization brings together world-class engineers and researchers in a fully English-speaking, international environment. As the company accelerates its “AI-first” strategy, this role sits at the center of a major shift toward physical AI and intelligent systems — offering a rare chance to work on impactful, real-world AI applications at scale. What You’ll Do Lead a team developing autonomous systems and robotics software platforms Stay hands-on in system architecture, key module development, and technical decision-making Establish engineering best practices (code quality, testing, CI/CD, documentation) Collaborate cross-functionally with hardware engineers, AI researchers, and product teams Own project planning, resource allocation, and technical roadmaps Build and scale a high-performing engineering team and culture Tech Stack Programming: Python, C++, Go, JavaScript / TypeScript Systems: Distributed Systems, Microservices Architecture Domains: Autonomous Systems / Robotics / Embedded / Real-time Systems Infrastructure: Cloud Platforms, DevOps, CI/CD

公司介紹 我們的客戶是一家專注於 Physical AI 與數位孿生（Digital Twin）技術 的 AI 新創團隊，致力於打造能夠讓 AI 在虛擬環境中訓練、學習並優化決策的下一代平台，並將最佳策略部署回真實世界場域。 團隊核心技術結合 AI、3D 模擬、運籌優化與大型場域建模，應用於智慧製造、自動化物流與高精密產業等場景，協助企業在虛擬工廠中完成策略模擬與 AI 訓練，大幅提升建置效率與營運決策能力。 公司獲得 國際 GPU 生態系與多家產業資本支持，並與大型科技與製造企業合作，是少數專注於 Sim-to-Real / Real-to-Sim AI 應用落地 的技術團隊。 如果你對 AI + Simulation + Robotics / Automation 的跨領域技術有興趣，這將是一個能直接參與核心產品與演算法設計的機會。 工作內容 你將加入核心演算法研發團隊，負責設計並優化應用於 大型數位孿生場域的演算法模型，協助解決複雜環境中的路徑規劃、排程與資源配置問題。 主要職責包含： 建立與設計演算法模型（如圖論、網格建模、路徑規劃或優化模型） 從 3D 環境與場域資料中建構抽象模型並設計解法 設計並實作高效能演算法模組（Python 為主） 使用 GPU 加速工具優化大型資料處理或模擬效能 與產品與工程團隊合作，將演算法整合至平台系統 測試與評估不同策略表現並持續優化 使用技術 Python CUDA / GPU Parallel Computing PyTorch Algorithm Design / Data Structures Graph Theory / Path Planning 3D Simulation / Digital Twin Optimization / Scheduling

公司介紹 這是一家高速成長的 AI 新創團隊，專注於 Physical AI 與 Industrial AI 的落地應用。團隊致力於打造能將真實世界工業環境快速轉換為高擬真模擬場景的 AI 平台，讓 AI 能在虛擬環境中進行訓練與策略優化，最終部署至真實工業系統。 公司產品結合 3D Simulation、Digital Twin 與 Reinforcement Learning 技術，讓企業可以在虛擬世界完成複雜系統的訓練與測試，大幅降低現實環境的成本與風險，並加速智慧製造與自動化的導入。 團隊由多位具創業與深度技術背景的成員組成，目前已獲得 國際級 AI 科技公司與知名投資機構支持，並與高端製造及半導體產業合作。工程師將有機會參與 AI + Simulation + Robotics 的前沿技術應用，直接將研究級技術落地至真實世界場景。 工作內容 作為 Senior Reinforcement Learning Engineer，你將負責透過強化學習技術優化自動化系統與工業場景中的 AI 決策能力，並在模擬環境中訓練可部署於真實世界的 AI 模型。 你將有機會參與 AI 在 工業自動化、機器人與智慧製造場景中的實際應用。 主要職責包含： 在 NVIDIA Isaac Sim 等模擬平台上建立與訓練強化學習模型 設計並實作 state space、action space 與 reward function 開發與優化 RL policy（如 Q-learning / Policy-based methods） 與 AI / Simulation / 3D 團隊合作進行系統模擬與模型訓練 持續調整模型與參數，提升策略效率與系統穩定度 將模擬環境中的最佳策略導入實際工業系統 使用技術 Python PyTorch / TensorFlow Reinforcement Learning Algorithms NVIDIA Isaac Sim Simulation / Digital Twin Robotics / Automation Systems

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.Role Overview Astera Labs is establishing a strategic RD center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a visionaryPhysical Design Engineer to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, defining the backend execution and methodologies for chips that power the world's largest AI clusters. As aPhysical Design Engineer, you will be a key architect of our silicon's physical reality. You won't just execute a flow—you will help establish our local execution culture and technical standards, owning the transformation of complex logic into high-performance silicon. You will drive the physical implementation journey from synthesis through signoff, ensuring our connectivity solutions meet the extreme performance, power, and area targets required for next-generation AI infrastructure. If you thrive on solving complex challenges in deep-submicron processes and want to shape the backend methodology for AI infrastructure connectivity, this is your opportunity. Key Responsibilities Physical Implementation Execution Be part of the founding Backend team in Israel, playing a critical role in establishing local execution culture and technical standards Take full responsibility for physical implementation journey including Synthesis, Floorplanning, Place Route, and Clock-Tree Synthesis (CTS) Own macro-level implementation with deep hands-on experience in floorplanning and complex routing Signoff Design Integrity Drive final stages of design integrity, owning Timing signoff (STA), Physical Verification (DRC/LVS), and Reliability analysis (EMIR) Ensure first-pass silicon success through rigorous signoff flows and analysis Apply Logic Equivalence Checking (LEC) and other verification techniques to guarantee design correctness Methodology Development Cross-Functional Collaboration Participate in defining and refining Backend methodologies with autonomy to improve workflows and tool automation Work closely with Architecture, Design, and DFT teams to navigate challenges of advanced process nodes and high-speed connectivity Leverage scripting and automation to make engineering environment faster and more robust Basic Qualifications Bachelor's degree in Electrical Engineering or related technical field 3+ years of hands-on experience in Physical Design at semiconductor companies Proven expertise in the full RTL2GDS flow with deep hands-on experience in macro-level implementation, floorplanning, and complex routing Experience working with advanced process technologies (7nm and below) Solid experience with signoff tools and flows including STA, Logic Equivalence Checking (LEC), DRC, and EMIR analysis Proficiency in TCL or Python scripting to drive EDA tool flows and automate repetitive tasks Preferred Qualifications Experience with full-chip level implementation and integration Knowledge of Power and Noise analysis (SI/PI) to optimize high-performance silicon Familiarity with Design-for-Test (DFT) requirements and their impact on physical layout Experience with industry-standard EDA tools (Synopsys Fusion Compiler/ICC2, Cadence Innovus) Background in high-speed interface designs or connectivity protocols We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.As an Astera Labs Physical Design/CAD Engineer you will play a crucial role in driving the planning, coordination, and execution supporting the design of Astera Labs' portfolio of connectivity ASICs used in the world's leading cloud service providers, server and network OEMs. This role requires RTL to GDS ownership across design stages (Synthesis/PnR/STA/Signoff), deep technical expertise, and close collaboration with RTL and verification teams to ensure robust full-chip signoff.This role is fully on-site and in-person. Key Responsibilities As Physical Design CAD Engineer you will support and build flows for world class EDA tools. Drive various Physical Design flow related activities, ensuring robust signoff across complex SoCs or sub-systems. Architect and recommend flow improvements and enhance existing methodology for high performance design. Good understanding of flow development related to backend tools like Synthesis/PnR/Extraction/DRC/LVS etc. Work with cross function teams to define requirements and specifications to achieve best PPA Opportunity to own a small block partition and closure (PnR, STA, DRC and LVS etc) based on interest and capacity Partner closely with design, implementation, and verification teams to drive block/top convergence, providing sign-off level expertise and guidance. Basic Qualifications Bachelor’s in Electrical Engineering or Computer Science required; Master’s preferred. 2-10 years of experience in PnR and sign-off for complex SoCs in Server, Storage, or Networking applications. Expertise in PnR, Extraction, Timing closure, EM-IR, Formality and DRC/LVS at both block and full-chip level. Strong knowledge of synthesis, place-and-route, extraction, and equivalence checking flows in advanced nodes (7nm or below). Proficiency with Cadence and/or Synopsys physical design/STA toolchains. Strong scripting ability (Tcl, Python, Perl). Ability to work independently with strong prioritization and a professional, customer-focused mindset. Preferred Experience Knowledge of agentic AI solutions is a plus. Experience working with EDA/IP vendors for both RTL and hard-macro integration. Familiarity with high-speed SERDES and Ethernet PHY timing challenges. Knowledge of ECO methodologies, DFT tools, and test coverage analysis. Your base salary will be determined based on your experience and the pay of employees in similar positions. The base salary range is $135,000 USD - $165,000 USD for Senior Level, and $160,000 USD - $195,000 USD for Staff Level. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Logitech is the Sweet Spot for people who want their actions to have a positive global impact while having the flexibility to do it in their own way.The role and team: Logitech is the established market leader in video communication solutions for consumers and enterprise users alike. Building on its strong marketing and engineering heritage, Logitech continues to push the boundaries of technology by investing in advanced video processing and AI/ML capabilities. The Video AI/ML Technology Development Team spearheads the creation of cutting-edge AI/ML algorithms and video pipelines for edge peripherals and host devices. Delivering unique human and machine vision solutions to Logitech’s webcam business, the team is at the forefront of technology and product innovation. Based at the EPFL Innovation Park, Lausanne (Switzerland), this team works closely with Software and Hardware development teams in North America and Asia. We are looking for a talented Senior Artificial Intelligence (AI)/Machine Learning (ML) Engineer to join a growing team of Data Engineers, Artificial Intelligence (AI)/Machine Learning(ML) Engineers and Software Developers, responsible for product and technology development in consumer webcams and applications. Following best practices in AI/ML and SW development, you will work in cross-functional teams across software and hardware engineering, program management, product management and design, to efficiently deliver on a product strategy. You will also work closely with Logitech’s Technology Office in developing the technology portfolio for disruptive innovation.  Your Contribution:Be Yourself. Be Open. Stay Hungry and Humble. Collaborate. Challenge. Decide and just Do. Share our passion for Equality and the Environment. These are the behaviors and values you’ll need for success at Logitech. In this role you will:Develop AI/ML algorithms and video pipelines across the entire model lifecycle: from design to training at scale, optimization, porting and deploying them to (embedded and hosted) target platforms. Working with a multidisciplinary team, you will champion best practices to turn cutting-edge research into robust and innovative solutions that define the future of human-machine interaction.Key Qualifications:For consideration, you must bring the following minimum skills and experiences to our team:Min. 5–6 years of relevant professional experience in algorithm development (signal processing and AI/ML) with a focus on live video.Significant industry experience in deploying deep learning models to real-world consumer products.Hands-on experience with latest AI/ML (Deep Learning) techniques and toolchains from architecture to training, evaluation, optimization, and porting to embedded systems (Linux/Android) and clients (MacOS/Windows).Experience training and scaling models on distributed computing clusters (e.g., AWS, GCP, or HPC clusters).Familiarity with data engineering: collection, generation, augmentation, and governance.Experience with Software Development Life Cycle (SDLC) best practices in embedded systems or host clients.Pragmatic, innovative, curious, and autonomous with a strong ability to communicate technical concepts to cross-functional partners.Skills:Design, training, evaluation, and optimization of deep neural networks (CNNs, RNNs, GANs, etc.). Knowledge of Transformers and LLMs is a plus.Proficiency in deep learning frameworks such as PyTorch, TensorFlow, or TinyML, as well as ONNX representations.Knowledge of supervised, unsupervised, and self-supervised learning.General-purpose programming languages, including Python, C/C, and C#.Software development experience on embedded platforms (e.g., ARM) and embedded AI.Education:MSc in Computer Science, Machine Learning, Data Science, or a related field.PhD in a related field is a plus.#LI-SL1 Across Logitech we empower collaboration and foster play. We help teams collaborate/learn from anywhere, without compromising on productivity or continuity so it should be no surprise that most of our jobs are open to work from home from most locations. Our hybrid work model allows some employees to work remotely while others work on-premises. Within this structure, you may have teams or departments split between working remotely and working in-house.Logitech is an amazing place to work because it is full of authentic people who are inclusive by nature as well as by design. Being a global company, we value our diversity and celebrate all our differences. Don’t meet every single requirement? Not a problem. If you feel you are the right candidate for the opportunity, we strongly recommend that you apply. We want to meet you!We offer comprehensive and competitive benefits packages and working environments that are designed to be flexible and help you to care for yourself and your loved ones, now and in the future. We believe that good health means more than getting medical care when you need it. Logitech supports a culture that encourages individuals to achieve good physical, financial, emotional, intellectual and social wellbeing so we all can create, achieve and enjoy more and support our families. We can’t wait to tell you more about them being that there are too many to list here and they vary based on location.All qualified applicants will receive consideration for employment without regard to race, sex, age, color, religion, sexual orientation, gender identity, national origin, protected veteran status, or on the basis of disability.If you require an accommodation to complete any part of the application process, are limited in the ability, are unable to access or use this online application process and need an alternative method for applying, you may contact us toll free at 1-510-713-4866 for assistance and we will get back to you as soon as possible.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.Role Overview Astera Labs is seeking a Physical Design Engineering Manager to lead a team of physical design engineers at our Toronto site, driving the implementation of connectivity ASICs within our Signal Connectivity Group. This group is responsible for products that enable high-speed serial connectivity including PCIe retimers, Ethernet retimers, and signal conditioning solutions deployed across the world's largest AI clusters and hyperscale data centers. As an Physical Design Manager Engineering Manager, you will combine hands-on technical leadership with people management, owning physical design execution from RTL to GDSII while building and mentoring a high-performing team. You will drive floorplanning, place-and-route, timing closure, and sign-off for complex designs requiring deep understanding of high-speed physical layer interfaces and SerDes integration at TSMC advanced nodes.This role is fully on-site at our Toronto location. Basic Qualifications Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field; Master's preferred. 12+ years of experience in physical design implementation of complex SoCs at advanced nodes (7nm and below). 2+ years of experience leading teams or projects with demonstrated ability to mentor and develop engineers. Hands-on expertise across the physical design flow: synthesis, place-and-route, CTS, extraction, timing closure, EM-IR, DRC/LVS, and equivalence checking. Proficiency with Cadence Innovus and/or Synopsys Fusion Compiler/ICC2 and supporting toolchains. Strong scripting ability in Tcl, Python, and/or Perl. Professional attitude with the ability to prioritize a dynamic list of tasks, plan and prepare for customer meetings in advance, and work with minimal guidance. Entrepreneurial, open-minded behavior and can-do attitude. Think and act fast with the customer in mind! Required Experience Build, lead, and mentor a physical design team, owning Physical Design execution and team development for Signal Connectivity Group products. Drive block and top-level physical design implementation from floorplan through tapeout for retimer and signal conditioning ASICs. Own floorplanning, macro placement, power grid design, clock tree synthesis, and place-and-route for complex blocks and full-chip designs. Drive timing closure at both block and full-chip levels, developing and maintaining timing constraints and signoff methodology. Ensure DRC/LVS/EM-IR closure and physical verification sign-off to foundry requirements. Integrate hard macros, high-speed SerDes, analog IP, and third-party IP blocks, ensuring seamless physical integration at block boundaries. Collaborate with RTL, DFT, STA, EMIR, and verification teams to drive design convergence from synthesis through sign-off. Work with IP vendors for both RTL and hard-macro integration, ensuring placement constraints and routing guidelines are met. Drive team execution, hiring, career development, and sprint planning for the Toronto PD team. Establish physical design best practices, flow improvements, and quality checks to scale execution across multiple concurrent programs. Coordinate with global PD teams (San Jose, Irvine, Bangalore) to ensure consistent methodology and design quality. Experience with Cadence and/or Synopsys physical design tools/flows. Familiarity and working knowledge of SystemVerilog/Verilog. Preferred Experience Deep understanding of high-speed SerDes physical layer, including equalization, CDR, and signal integrity considerations impacting physical design. Experience with PCIe, Ethernet, or retimer/signal conditioning ASIC implementation. Knowledge of physical layer timing challenges specific to high-speed serial interfaces. Hands-on experience with UPF-based multi-voltage/multi-power-domain implementations. Familiarity with advanced packaging or multi-die integration and its impact on physical design. Experience with ECO methodologies and DFT-aware physical design. Knowledge of EMIR-aware implementation techniques and early-stage IR drop mitigation. Track record of building and scaling physical design teams through multiple tapeouts. Knowledge of agentic AI solutions for EDA automation. Base salary range is CAD 180,000 to CAD 220,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives, and benefits.We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.About the Role We are seeking a Senior Physical Design Engineer to join our high-performance design team working on next-generation transceiver IPs targeting the TSMC 5nm, 3nm technology node. In this role, you will take ownership of physical implementation from RTL to GDSII, ensure timing and power closure for ultra-high-speed designs, and collaborate closely with cross-functional teams to resolve challenges unique to advanced nodes and multi-gigabit transceiver architectures. Key Responsibilities Perform full-chip and block-level physical implementation including floor planning, placement, clock tree synthesis (CTS), routing, and physical verification for high-speed designs in TSMC 3nm. Collaborate with RTL and STA teams to ensure clean handoffs and convergent timing, area, and power. Work on advanced physical design techniques to support multiple voltage/frequency domains, hierarchical design, and physical-aware synthesis. Handle advanced physical design topics: EM/IR analysis and power grid optimization Congestion analysis and mitigation Clock domain crossing and skew optimization RC extraction-aware placement and routing Integrate IPs and top-level blocks with attention to physical interfaces, constraints, and timing alignment. Participate in defining floorplan strategy and chip partitioning for multi-gigabit transceivers. Perform ECO implementation and support tapeout signoff activities. Ensure DRC/LVS/ANT/CELL/ERC clean database using industry-standard physical verification tools. Use industry-standard tools (e.g., ICC2, Innovus, Voltus, RedHawk, Calibre) for implementation and signoff. Develop and maintain automation scripts (Tcl, Python, Perl) for physical design flows and regressions. Required Qualifications Bachelor’s or Master’s degree in Electrical Engineering, Electronics Engineering, or related field. 4+ years of experience in physical design with advanced technology nodes (preferably ≤ 5nm). Strong experience with: Floor planning, placement, CTS, routing, and IR drop mitigation Signoff checks (DRC/LVS/ANT/ERC) and debugging Timing closure collaboration with STA team Hands-on experience with tools such as Synopsys ICC2, Cadence Innovus, Calibre, Voltus. Experience in integrating high-speed IPs (e.g., SerDes, PHYs) into SoC or chiplet environments. Experience in high frequence data path, DSP designs. Solid scripting skills for automation and productivity enhancement. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.As an Astera Labs Senior/Staff Physical Design Engineer you will play a crucial role in overseeing the planning, coordination, and execution supporting the design of Astera Labs' portfolio of connectivity ASICs used in the world's leading cloud service providers, server and network OEMs. To accomplish that, you will work closely with designers, verification engineering, and engineering operations. This role is fully on-site and in-person. Basic Qualifications: Strong academic and technical background in electrical engineering. A Bachelor’s degree in EE / Computer is required, and a Master’s degree is preferred. ≥3 years’ experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications. Professional attitude with the ability to prioritize a dynamic list of multiple tasks, plan and prepare for customer meetings in advance, and work with minimal guidance and supervision. Entrepreneurial, open-mind behavior and can-do attitude. Think and act fast with the customer in mind! Required Experience: Hands-on and thorough knowledge of synthesis, place and route, timing, extraction, EM-IR, formal verification (equivalence) and other backend tools and methodologies for technologies 7nm or less. Block level ownership from architecture to GDSII, driving multiple complex designs to production. Experience with Cadence and/or Synopsys physical design tools/flows. Familiarity and working knowledge of System Verilog/Verilog. Proven expertise in developing/maintaining timing constraints, timing signoff methodology, timing closure at the block or full-chip level. Experience in working with IP vendors for both RTL and hard-macro blocks. Good scripting skills in tcl, python or Perl. Preferred Experience: Knowledge of design for test (DFT) Familiarity with ECO methodologies and tools. Knowledge of LVS/DRC closures. Your base salary will be determined based on your experience and the pay of employees in similar positions. The base salary range is $135,000 USD - $165,000 USD for Senior Level, and $160,000 USD - $195,000 USD for Staff Level. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Logitech is the Sweet Spot for people who want their actions to have a positive global impact while having the flexibility to do it in their own way.Summer internship period: July 1, 2026 (Wed) ~ August 31, 2026 (Mon)The Team and Role:An AI and Firmware Engineer is responsible for create, training and testing the AI agent for coding process automation for embedded systemYour Contribution:Be Yourself. Be Open. Stay Hungry and Humble. Collaborate. Challenge. Decide and just Do. These are the behaviors you’ll need for success at Logitech. In this role you will:Study the AI framework that can help on platform porting from Datasheet study, SDK integration, function test and code commit.Work with system architect, embedded FW developer and test team to understand the product development process and define the role of AI agent to create the AI assisted automation process.Prototype and show your ideasValidate your work, write user guide , and introduce your contribution to automate the design process.Engage with colleagues in a multi-sites multicultural environment (US, Switzerland, Taiwan)Key Qualifications:For consideration, you must bring the following minimum skills and behaviors to our team:Fluent in C/C programming including test and debugSoftware system level design experience (modularized design, state machine, system diagram, flow chart tools) Practically minded with strong problem solving skillsStrong technical documentation skillsFluent spoken written EnglishEducation:BS/MS in Computer Science or equivalent#LI-AL2/104Across Logitech we empower collaboration and foster play. We help teams collaborate/learn from anywhere, without compromising on productivity or continuity so it should be no surprise that most of our jobs are open to work from home from most locations. Our hybrid work model allows some employees to work remotely while others work on-premises. Within this structure, you may have teams or departments split between working remotely and working in-house.Logitech is an amazing place to work because it is full of authentic people who are inclusive by nature as well as by design. Being a global company, we value our diversity and celebrate all our differences. Don’t meet every single requirement? Not a problem. If you feel you are the right candidate for the opportunity, we strongly recommend that you apply. We want to meet you!We offer comprehensive and competitive benefits packages and working environments that are designed to be flexible and help you to care for yourself and your loved ones, now and in the future. We believe that good health means more than getting medical care when you need it. Logitech supports a culture that encourages individuals to achieve good physical, financial, emotional, intellectual and social wellbeing so we all can create, achieve and enjoy more and support our families. We can’t wait to tell you more about them being that there are too many to list here and they vary based on location.All qualified applicants will receive consideration for employment without regard to race, sex, age, color, religion, sexual orientation, gender identity, national origin, protected veteran status, or on the basis of disability.If you require an accommodation to complete any part of the application process, are limited in the ability, are unable to access or use this online application process and need an alternative method for applying, you may contact us toll free at 1-510-713-4866 for assistance and we will get back to you as soon as possible.