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Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.Role Overview Astera Labs is establishing a strategic RD center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a highly skilled Physical Design Engineer specializing in EMIR CAD to join our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful technical ownership in a new site, executing the backend power methodologies for chips that power the world's largest AI clusters. As a Physical Design Engineer, you will be a core technical contributor ensuring the power robustness and long-term reliability of our high-performance connectivity silicon. You will continuously develop the Electro-Migration and IR Drop (EMIR) flow, working closely at the intersection of Physical Design, Analog/Mixed-Signal design, and Package Engineering. Key Responsibilities Take responsibility on IR drop analysis and signal/power electromigration (EM) flow Implement and maintain robust EMIR flows and methodologies using industry-standard tools (Ansys RedHawk-SC, Cadence Voltus, or equivalent) Collaborate closely with Analog/SerDes designers to integrate current profiles and ensure robust power delivery to sensitive high-speed IP blocks Partner with Package Design engineers to perform Chip-Package-System (CPS) co-analysis flow Understand root-cause analysis for voltage drop violations and EM risks Support silicon bring-up by correlating simulation results with actual silicon measurements and yield data Basic Qualifications Bachelor's or Master's degree in Electrical Engineering or a related technical field 5+ years of hands-on experience in EMIR/Power Integrity analysis for high-performance SoCs or high-speed connectivity products Strong proficiency in industry-standard EMIR tools flow development (Ansys RedHawk/RedHawk-SC, or Cadence Voltus) Deep understanding of EM/IR challenges in advanced FinFET nodes (7nm, 5nm, 3nm) Basic understanding of Place Route flows, power grid synthesis, extraction (RC), and standard cell architecture Proven Proficiency in Python in required, Tcl or Perl preferable for flow automation and data parsing Deep understanding of the RedHawk tool, including efficient use of MapReduce and other Ansys proprietary capabilities (including potential use of ad-hoc SDC for context and LSO – Logic State Override) Strong understanding of required inputs for creating Scenarios and Analysis Views Deep understanding of standard cell and IP abstractions (APL, LIB, AVM), including IP waveform construction from PWL (sim2iprof) Preferred Experience Experience performing Chip-Package-System (CPS) thermal and power co-simulation Familiarity with thermal analysis tools and their interaction with electrical performance Experience working with sign-off criteria and margins for high-volume production chips Basic understanding of timing and PR Good understanding of EM, including deterministic EM (DC, peak, RMS) Basic understanding of statistical EM and reliability concepts (SEB, Black’s Equation, FIT, MTTF) Basic understanding of packaging, top metal layers, MIM capacitor usage, and power distribution We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.Role Overview Astera Labs is establishing a strategic RD center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a visionaryPhysical Design Engineer to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, defining the backend execution and methodologies for chips that power the world's largest AI clusters. As aPhysical Design Engineer, you will be a key architect of our silicon's physical reality. You won't just execute a flow—you will help establish our local execution culture and technical standards, owning the transformation of complex logic into high-performance silicon. You will drive the physical implementation journey from synthesis through signoff, ensuring our connectivity solutions meet the extreme performance, power, and area targets required for next-generation AI infrastructure. If you thrive on solving complex challenges in deep-submicron processes and want to shape the backend methodology for AI infrastructure connectivity, this is your opportunity. Key Responsibilities Physical Implementation Execution Be part of the founding Backend team in Israel, playing a critical role in establishing local execution culture and technical standards Take full responsibility for physical implementation journey including Synthesis, Floorplanning, Place Route, and Clock-Tree Synthesis (CTS) Own macro-level implementation with deep hands-on experience in floorplanning and complex routing Signoff Design Integrity Drive final stages of design integrity, owning Timing signoff (STA), Physical Verification (DRC/LVS), and Reliability analysis (EMIR) Ensure first-pass silicon success through rigorous signoff flows and analysis Apply Logic Equivalence Checking (LEC) and other verification techniques to guarantee design correctness Methodology Development Cross-Functional Collaboration Participate in defining and refining Backend methodologies with autonomy to improve workflows and tool automation Work closely with Architecture, Design, and DFT teams to navigate challenges of advanced process nodes and high-speed connectivity Leverage scripting and automation to make engineering environment faster and more robust Basic Qualifications Bachelor's degree in Electrical Engineering or related technical field 3+ years of hands-on experience in Physical Design at semiconductor companies Proven expertise in the full RTL2GDS flow with deep hands-on experience in macro-level implementation, floorplanning, and complex routing Experience working with advanced process technologies (7nm and below) Solid experience with signoff tools and flows including STA, Logic Equivalence Checking (LEC), DRC, and EMIR analysis Proficiency in TCL or Python scripting to drive EDA tool flows and automate repetitive tasks Preferred Qualifications Experience with full-chip level implementation and integration Knowledge of Power and Noise analysis (SI/PI) to optimize high-performance silicon Familiarity with Design-for-Test (DFT) requirements and their impact on physical layout Experience with industry-standard EDA tools (Synopsys Fusion Compiler/ICC2, Cadence Innovus) Background in high-speed interface designs or connectivity protocols We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.Role Overview Astera Labs is establishing a strategic RD center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we are seeking a motivatedPhysical Design Studentto join our founding local engineering team. This is a unique opportunity to kickstart your career in the semiconductor industry. Working alongside senior industry veterans, you will gain hands-on experience in backend execution and advanced methodologies for cutting-edge chips that power the world's largest AI clusters. If you are passionate about silicon hardware, eager to learn, and thrive on solving complex engineering challenges, this role offers the perfect bridge between your academic studies and a high-impact career. Key Responsibilities Guided Implementation Learning Partner with and learn from senior engineers to support the physical implementation journey, including synthesis, floorplanning, Place Route (PR), and Clock-Tree Synthesis (CTS) Assist in macro-level implementation and develop hands-on skills in complex layout routing Participate in deep-submicron process challenges under close professional mentorship Signoff Design Integrity Support Assist in running engineering checks for design integrity, including Static Timing Analysis (STA), Physical Verification (DRC/LVS), and Reliability analysis (EMIR) Learn to apply Logic Equivalence Checking (LEC) to help guarantee design correctness Gain exposure to the rigorous flows required to ensure first-pass silicon success Scripting Cross-Functional Collaboration Leverage and develop scripting tools to automate repetitive tasks and optimize the engineering environment Collaborate with Architecture, Design, and DFT teams to understand how different chip design disciplines intersect Actively participate in team reviews and technical discussions to ramp up backend methodologies Basic Qualifications Pursuing a Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related technical field Strong academic foundation in digital systems, VLSI design, or semiconductor devices. Familiarity with Python, TCL, Bash, or Perl. Ability to work at least 2 days per week at our Haifa/Tel Aviv Center A "can-do" attitude with a passion for solving complex technical challenges Fluent in Hebrew and English with the ability to work effectively in a team environment Preferred Qualifications Prior experience from a previous VLSI/Hardware student position or a significant academic project in physical design/VLSI Hands-on university lab experience with industry-standard EDA tools (e.g., Synopsys Fusion Compiler/ICC2, Cadence Innovus) Understanding of basic verification concepts (STA, DRC, LVS) Fast learner with a proactive attitude and a passion for deep-tech hardware infrastructure We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.Role Overview Astera Labs is establishing a strategic RD center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a visionary Junior Physical Design Engineer to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, defining the backend execution and methodologies for chips that power the world's largest AI clusters. As a Junior Physical Design Engineer, you will be a key architect of our silicon's physical reality. You won't just execute a flow—you will help establish our local execution culture and technical standards, owning the transformation of complex logic into high-performance silicon. You will drive the physical implementation journey from synthesis through signoff, ensuring our connectivity solutions meet the extreme performance, power, and area targets required for next-generation AI infrastructure. If you thrive on solving complex challenges in deep-submicron processes and want to shape the backend methodology for AI infrastructure connectivity, this is your opportunity. Key Responsibilities Physical Implementation Execution Be part of the founding Backend team in Israel, playing a critical role in establishing local execution culture and technical standards Take full responsibility for physical implementation journey including Synthesis, Floorplanning, Place Route, and Clock-Tree Synthesis (CTS) Own macro-level implementation with deep hands-on experience in floorplanning and complex routing Signoff Design Integrity Drive final stages of design integrity, owning Timing signoff (STA), Physical Verification (DRC/LVS), and Reliability analysis (EMIR) Ensure first-pass silicon success through rigorous signoff flows and analysis Apply Logic Equivalence Checking (LEC) and other verification techniques to guarantee design correctness Methodology Development Cross-Functional Collaboration Participate in defining and refining Backend methodologies with autonomy to improve workflows and tool automation Work closely with Architecture, Design, and DFT teams to navigate challenges of advanced process nodes and high-speed connectivity Leverage scripting and automation to make engineering environment faster and more robust Basic Qualifications Bachelor’s degree in Electrical Engineering or a related technical field Foundational understanding of the RTL-to-GDS flow, with academic or internship exposure to areas such as floorplanning, placement, and routing Familiarity with advanced process technologies (e.g., 7nm and below) through coursework or hands-on projects Basic experience with signoff methodologies and tools, including STA, Logic Equivalence Checking (LEC), DRC, and EMIR analysis Working knowledge of TCL or Python scripting for simple automation and support of EDA tool flows Preferred Qualifications Experience with full-chip level implementation and integration Knowledge of Power and Noise analysis (SI/PI) to optimize high-performance silicon Familiarity with Design-for-Test (DFT) requirements and their impact on physical layout Experience with industry-standard EDA tools (Synopsys Fusion Compiler/ICC2, Cadence Innovus) Background in high-speed interface designs or connectivity protocols We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.Role Overview Astera Labs is establishing a strategic RD center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, We are looking for aPhysical Design CAD Engineerwith at least3 years of hands-on experiencein digital implementation flows. The ideal candidate is highly technical, curious, and eager to drive innovation by combining strong physical design knowledge with modern automation andGenAI-based methodologies. This is a unique opportunity to take on meaningful technical ownership in a new site, implementing the parasitic extraction (PEX) methodologies and flows for chips that power the world's largest AI clusters. As a foundational member of the team, you will be responsible for the accuracy and efficiency of our extraction environment, ensuring that our high-speed designs are modeled with the highest precision from RTL to GDSII. Key Responsibilities The Engineer will develop, maintain, and improve CAD flows and methodologies for physical design teams, supporting advanced implementation stages from synthesis through place and route, timing closure, power optimization, and signoff readiness. Key responsibilities include: Develop and support physical design CAD flows using industry-standard EDA tools Build automation infrastructure for implementation, analysis, reporting, and debug Support design teams in areas such as synthesis, floorplanning, placement, CTS, routing, timing, power, and physical verification Create scripts and utilities to improve productivity, quality of results, and flow robustness Support and enhance flows based onSynopsys Fusion Compiler Explore and integrateGenAI solutions to accelerate debug, automate repetitive tasks, improve reporting, and enhance engineering productivity Analyze tool results, logs, QoR metrics, timing reports, congestion, utilization, power, and design-rule issues Basic Qualifications At least3 years of experience in Physical Design, CAD, or implementation methodology Strong understanding of digital physical design concepts, including synthesis, placement, CTS, routing, timing closure, and physical verification Hands-on experience withSynopsys Fusion Compiler Experience with scripting languages such asTcl, Python Ability to develop automation around EDA tools and large-scale design flows Good understanding of timing, power, congestion, floorplanning, and QoR analysis Strong debugging and problem-solving skills Ability to work closely with multiple engineering teams and support complex design environments High motivation to learn and applyGenAI technologiesin semiconductor design flows. Preferred Experience Experience with additional tools such as PrimeTime, StarRC, ICC2, Innovus, Voltus, RedHawk, Calibre, or similar Knowledge of STA, low-power design, UPF, EM/IR, extraction, or signoff flows Experience building dashboards, regression systems, flow checkers, or automated report analyzers Familiarity with LLMs, prompt engineering, AI agents, or GenAI-based coding/debug tools Experience with Git, CI/CD, databases, or cloud-based compute environments We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.Role Overview Astera Labs is establishing a strategic RD center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a highly skilled Static Timing Analysis (STA) Engineer to join our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful technical ownership in a new site, executing the sign-off methodology for chips that power the world's most advanced AI clusters. As an STA Engineer, you will be deeply involved in the STA activities from chip partition and time budgeting through to final sign-off. You will bridge the gap between Architecture, Design, DFT, and Physical Design to ensure our high-performance silicon meets the aggressive timing targets required for next-generation connectivity. Key Responsibilities Execute the STA flow and sign-off methodologies, ensuring our products meet rigorous timing criteria for the most demanding data center environments Collaborate closely with Architecture, Design, DFT, and Backend teams, participating in timing reviews and working with block owners to navigate the path to sign-off convergence Develop, optimize, and manage complex SDC constraints, ensuring they are accurate and robust across multi-scenario environments Analyze and resolve challenges related to cross-chip clock distribution networks and apply sophisticated margining techniques to ensure robust silicon across all process corners Participate in design methodology improvements and tool automation, utilizing both industry-standard EDA tools and custom scripts to make our sign-off process faster and more efficient Basic Qualifications B.Sc. in Electrical Engineering or Computer Engineering 5+ years of hands-on experience in Static Timing Analysis (STA) at semiconductor companies, specifically working on advanced process technologies. (Note: Adjust years of experience based on the exact level you are targeting) Deep expertise in multi-scenario STA, as well as timing and SDC constraint development and verification at the block and subsystem levels Solid understanding of advanced margining methodologies, including OCV, AOCV, and POCV, from synthesis through to final sign-off Solid knowledge of physical design flows (Synthesis, PR, Physical Verification) and how they intersect with timing closure Preferred Experience Experience developing and validating constraints using industry-standard tools like Timing Constraints Manager (Synopsys) or TimeVision (Ausdia) Proven track record of executing STA on complex Macro-level designs and supporting Full-Chip timing integration Strong background in scripting (Tcl, Python, Perl) and automation to enhance timing closure efficiency We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.Role Overview Astera Labs is establishing a strategic RD center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a highly skilled Chip Top Physical Design Engineer focusing on implementation to join our local engineering powerhouse from the ground up.If you thrive on solving complex, unnamed challenges in deep-submicron processes, your place is with us. As a Physical Design Engineer, you will be a key hands-on member of our PD Team in the Israel RD center. You will execute the physical design of the SoC Top level for chips that drive the world’s largest AI clusters. You will be deeply involved in all PD disciplines of the chip, driving the tape-out (T.O.) GDS to meet strict signoff criteria (Timing, LVS, EMIR, DRC, PV, etc.), ensuring our silicon meets the extreme performance, power, and area (PPA) targets required for AI scale. Key Responsibilities Execute SoC Top-level physical design and actively drive full-chip convergence Perform Top-Level physical implementation, including floor-planning, Place Route (PR), Clock Tree Synthesis (CTS), Power/Clock distribution, Power Integrity, and Timing/Physical signoff Work closely with the Architecture, Design, DFT, and Product teams to achieve optimal Power, Performance, and Area (PPA). This involves participating in feasibility studies for new architectures and optimizing runs to ensure the best Quality of Results (QoR) Resolve complex signal integrity, thermal, and power challenges inherent in high-speed connectivity silicon Collaborate closely with the Package team on Bump-map-to-Ballout design, taking all signal integrity aspects into consideration Basic Qualifications B.Sc. or M.Sc. in Electrical Engineering 5+ years of hands-on experience in Chip Top Physical Design/Backend at leading semiconductor companies, working on advanced process technologies (5nm, 3nm, and below) Proven experience executing complex block or chip-level projects with a proactive, "can-do" approach and excellent communication skills Deep hands-on expertise in RTL2GDS flows, including PR, STA, Physical Verification (DRC/LVS), Formal Verification, low-power implementation (UPF/CPF), and EMIR Mastery of industry-standard EDA tools (Synopsys Fusion Compiler/ICC2 or Cadence Innovus) Practical experience handling both complex macro/subsystem-level designs and Full-Chip integration Preferred Qualifications Deep understanding of Power Noise analysis (EM/IR) Experience with DFT (Design for Test) integration into the physical design flow Background in high-speed interfaces or data center protocols We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.Role Overview Astera Labs is establishing a strategic RD center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a highly skilled Physical Design Engineer specializing in SoC EMIR to join our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful technical ownership in a new site, executing the backend power methodologies for chips that power the world's largest AI clusters. As an EMIR Engineer, you will be a core technical contributor ensuring the power robustness and long-term reliability of our high-performance connectivity silicon. You will be responsible for SoC EMIR Analysis to ensure our products meet aggressive voltage drop and reliability targets in advanced FinFET process nodes, directly impacting the performance and yield of chips operating in the world’s most demanding AI and cloud environments. Key Responsibilities Take responsibility on IR drop analysis and signal/power electromigration (EM) of very complex chip Collaborate closely with Physical Design team to insure a full power integrity Partner with Package Design engineers to perform Chip-Package co-analysis (CPM) Understand root-cause analysis for voltage drop violations and EM risks Basic Qualifications Bachelor's or Master's degree in Electrical Engineering or a related technical field 7+ years of hands-on experience in EMIR/Power Integrity analysis for high-performance SoCs or high-speed connectivity products Strong proficiency in industry-standard EMIR tools (Ansys RedHawk/RedHawk-SC, or Cadence Voltus) Deep understanding of EM/IR challenges in advanced FinFET nodes (7nm, 5nm, 3nm) Deep understanding of Place Route flows, power grid synthesis, extraction (RC), and standard cell architecture Deep understanding of EM and trade-offs between signal EM and power grid (PG) EM Preferred Experience Familiarity with thermal analysis tools and their interaction with electrical performance Experience working with sign-off criteria and margins for high-volume production chips Good understanding of timing and PR Basic understanding of packaging, top metal layers, MIM capacitor usage, and power distribution Ability to write TCL scripts for STA and Fusion Compiler (FC) We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.Role Overview Astera Labs is establishing a strategic RD center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a highly skilled Physical Design CAD Engineer specializing in CAD Extraction to join our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful technical ownership in a new site, implementing the parasitic extraction (PEX) methodologies and flows for chips that power the world's largest AI clusters. As a foundational member of the team, you will be responsible for the accuracy and efficiency of our extraction environment, ensuring that our high-speed designs are modeled with the highest precision from RTL to GDSII. Key Responsibilities Develop, qualify, and maintain automated RC extraction flows for high-performance AI SoCs Own the setup and validation of foundry technology files (e.g., StarRC/Quantus techfiles, TLU+, ITF) across various process corners Perform correlation studies between different extraction tools and 3D field solvers (e.g., Raphael, QuickCap) to ensure modeling accuracy Collaborate closely with the Signal Integrity (SI) and Power Integrity (PI) teams to provide accurate parasitic data for critical high-speed nets and power grids Implement automated scripts (Tcl/Python) to streamline extraction regressions, data parsing, and PEX-to-STA (Static Timing Analysis) handoffs Analyze the impact of layout effects (LDE) and parasitics on timing and power, providing feedback to the implementation team to optimize PPA Interface with EDA vendors and foundries to resolve extraction tool bugs and methodology gaps related to advanced nodes (5nm/3nm) Basic Qualifications Bachelor’s degree in Electrical Engineering or a related technical field 5+ years of hands-on experience in Physical Design CAD or Physical Verification with a heavy focus on parasitic extraction Expert proficiency with industry-standard extraction tools such as Synopsys StarRC, Cadence Quantus (QRC), or Siemens Calibre xACT Strong scripting skills in Tcl and Python for flow automation and database manipulation Deep understanding of semiconductor physics, interconnect modeling, and the impact of parasitics on timing, EM (Electromigration), and IR drop Proven experience in validating tech files and running extraction for complex, multi-million gate designs Preferred Experience Hands-on experience with 5nm, 3nm, or more advanced process nodes, including FinFET-specific extraction challenges Familiarity with 3D field solvers and their use in benchmarking standard extraction engines Knowledge of Netlist formats (SPEF, DSPF) and their integration into STA and Spice simulation flows Experience with compute farm management (LSF/Slurm) and version control (Git) We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.Role Overview Astera Labs is establishing a strategic RD center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a highly skilled Physical Design CAD Engineer specializing in CAD Automation and Signoff to join our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful technical ownership in a new site, implementing the backend execution environment and methodologies for chips that power the world's largest AI clusters. As a foundational member of the team, you will be responsible for the physical implementation environment. Your primary mission is to develop, optimize, and support automated flows from RTL to manufacturable GDSII tape-out, ensuring a methodical and efficient work environment for the entire PD team. Key Responsibilities Develop and maintain automated flows for Synthesis, Place Route (PR), and Floor-planning to ensure seamless design transitions Implement and manage robust environments for Static Timing Analysis (STA), Power Analysis, and Physical Verification (DRC/LVS/ERC) Write and maintain custom plug-ins and scripts (Tcl/Python) to extend vendor tool capabilities, tailoring them to specific process node constraints Build automated "dashboards" and feedback loops to track and improve Power, Performance, and Area (PPA) metrics across design iterations Own the design database structure and version control to ensure team alignment and data integrity Collaborate directly with EDA vendors (Synopsys, Cadence, Siemens/Mentor) to troubleshoot flow issues and analyze tool results Provide technical support to the broader PD team, helping them optimize individual blocks for power, performance, and timing Basic Qualifications Bachelor’s degree in Electrical Engineering or a related technical field 5+ years of hands-on professional experience with back-end industrial tool suites (e.g., Synopsys Fusion Compiler or Cadence Genus/Innovus) Expert-level proficiency in Tcl and Python for high-level flow automation, data parsing, and tool customization Deep technical understanding of Physical Design concepts, including clock tree synthesis (CTS), routing congestion, timing closure, and signal integrity Proven experience executing sign-off flows for complex, high-performance designs Strong communication skills and a collaborative approach to solving complex engineering bottlenecks Preferred Experience Hands-on experience with 5nm, 3nm, or more advanced process nodes Practical knowledge of compute farm management (LSF/Slurm) and revision control (Git) for managing massive design databases Experience in developing proprietary automation wrappers for industry-standard EDA tools We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.