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Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.Role Overview Astera Labs is seeking a Physical Design Engineering Manager to lead a team of physical design engineers at our Toronto site, driving the implementation of connectivity ASICs within our Signal Connectivity Group. This group is responsible for products that enable high-speed serial connectivity including PCIe retimers, Ethernet retimers, and signal conditioning solutions deployed across the world's largest AI clusters and hyperscale data centers. As an Physical Design Manager Engineering Manager, you will combine hands-on technical leadership with people management, owning physical design execution from RTL to GDSII while building and mentoring a high-performing team. You will drive floorplanning, place-and-route, timing closure, and sign-off for complex designs requiring deep understanding of high-speed physical layer interfaces and SerDes integration at TSMC advanced nodes.This role is fully on-site at our Toronto location. Basic Qualifications Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field; Master's preferred. 10+ years of experience in physical design implementation of complex SoCs at advanced nodes (7nm and below). 2+ years of experience leading teams or projects with demonstrated ability to mentor and develop engineers. Hands-on expertise across the physical design flow: synthesis, place-and-route, CTS, extraction, timing closure, EM-IR, DRC/LVS, and equivalence checking. Proficiency with Cadence Innovus and/or Synopsys Fusion Compiler/ICC2 and supporting toolchains. Strong scripting ability in Tcl, Python, and/or Perl. Professional attitude with the ability to prioritize a dynamic list of tasks, plan and prepare for customer meetings in advance, and work with minimal guidance. Entrepreneurial, open-minded behavior and can-do attitude. Think and act fast with the customer in mind! Required Experience Build, lead, and mentor a physical design team, owning Physical Design execution and team development for Signal Connectivity Group products. Drive block and top-level physical design implementation from floorplan through tapeout for retimer and signal conditioning ASICs. Collaborate with RTL, DFT, STA, EMIR, and verification teams to drive design convergence from synthesis through sign-off. Work with IP vendors for both RTL and hard-macro integration, ensuring placement constraints and routing guidelines are met. Drive team execution, hiring, career development, and sprint planning for the Toronto PD team. Establish physical design best practices, flow improvements, and quality checks to scale execution across multiple concurrent programs. Coordinate with global PD teams (San Jose, Irvine, Bangalore) to ensure consistent methodology and design quality. Experience with Cadence and/or Synopsys physical design tools/flows. Preferred Experience/Nice to Have Deep understanding of high-speed SerDes physical layer, including equalization, CDR, and signal integrity considerations impacting physical design. Knowledge of physical layer timing challenges specific to high-speed serial interfaces. Track record of building and scaling physical design teams through multiple tapeouts. Knowledge of agentic AI solutions for EDA automation. Base salary range is CAD 180,000 to CAD 220,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives, and benefits.We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.As an Astera Labs Technical Lead Physical Design Engineer you will play a crucial role in driving the planning, coordination, and execution supporting the design of Astera Labs' portfolio of connectivity ASICs used in the world's leading cloud service providers, server and network OEMs. This role requires end-to-end STA ownership across design stages, deep technical expertise, and close collaboration with RTL, physical design, and verification teams to ensure robust full-chip timing convergence. This role is fully on-site and in-person. Key Responsibilities Drive timing closure from RTL through sign-off, ensuring robust timing across complex SoCs. Develop and validate SDC constraints, including MMMC setup, to enable accurate and efficient STA analysis. Define and manage I/O timing budgets across hierarchical designs. Apply advanced sign-off methodologies at TSMC 7nm and below, including OCV/AOCV and PVT effects. Leverage ETM libraries for hierarchical timing analysis and correlation, balancing runtime and accuracy. Provide actionable timing feedback at both block and full-chip levels, including root cause analysis and ECO guidance. Manage large-scale multi-corner/multi-mode STA runs with automation, partitioning, and efficient resource usage. Generate and validate timing ECOs, partnering with physical design and RTL teams for quick closure. Partner closely with design, implementation, and verification teams to drive timing convergence, providing sign-off level expertise and guidance. Basic Qualifications Bachelor’s in Electrical Engineering or Computer Science required; Master’s preferred. ≥5 years of experience in timing analysis and sign-off for complex SoCs in Server, Storage, or Networking applications. Expertise in timing constraints, STA methodology, and timing closure at both block and full-chip level. Strong knowledge of synthesis, place-and-route, extraction, and equivalence checking flows in advanced nodes (7nm or below). Proficiency with Cadence and/or Synopsys physical design/STA toolchains. Strong scripting ability (Tcl, Python, Perl). Ability to work independently with strong prioritization and a professional, customer-focused mindset. Preferred Experience Familiarity with high-speed SERDES and Ethernet PHY timing challenges. Knowledge of ECO methodologies, DFT tools, and test coverage analysis. Experience working with IP vendors for both RTL and hard-macro integration. SystemVerilog/Verilog familiarity. The base salary range is $140,000 CAD – $180,000.00 CAD. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.Role Overview As a Sr. Principal Program Manager, ASIC Designat Astera Labs, you will own the cross-functional execution framework for advanced ASIC programs from early planning through tapeout. You will drive milestones, dependencies, execution reviews, decision-making forums, risk management, and tapeout readiness across multiple engineering teams. You will partner closely with architecture, RTL design, functional verification, emulation, DFT, synthesis, physical design, CAD, IP, product management, engineering leadership, and external partners. This is a high-impact role for a technical program leader who can operate in a fast-moving environment, manage ambiguity, drive accountability, and establish scalable execution practices across complex silicon development programs. Key Responsibilities Program Execution Planning Lead pre-silicon execution of complex ASIC and subsystem programs from concept through tapeout. Own program plans, schedules, milestones, dependencies, risk registers, dashboards, and executive-level status reporting. Drive pre-silicon and NPD phase-gate execution from kickoff through final GDS handoff, ensuring cross-functional readiness across architecture, RTL, verification, DFT, physical design, signoff, and tapeout. Cross-Functional Alignment Coordination Drive cross-functional alignment across architecture, RTL design, verification, emulation, DFT, synthesis, physical design, CAD, IP integration, product management, and external partners. Track IP delivery, PDK updates, CAD/EDA flow readiness, tool dependencies, and foundry requirements. Partner with Post-Silicon PM and Validation teams to absorb feedback from post silicon bring up, including bug reports and Si issues. Risk Management Decision-Making Identify execution risks, lead risk mitigation plans, and drive trade-off decisions across scope, schedule, resources, and quality. Communicate program health, risks, dependencies, and decisions clearly to engineering teams, senior leaders, executives, and external partners. Process Operational Excellence Establish scalable program management practices, operating rhythms, decision forums, documentation standards, and communication mechanisms, lead constant improvement. Basic Qualifications Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related technical field. 10+ years of experience in ASIC/SoC development or silicon program execution, including 3+ years in technical program management, engineering program management, or technical leadership. Experience managing pre-silicon ASIC development flows, including architecture planning, RTL design, functional verification, synthesis, DFT, physical design, timing closure, signoff, and tapeout. Experience with advanced process nodes and high-performance ASIC/SoC development. Strong understanding of ASIC development milestones from product requirements through final GDS handoff. Familiarity with EDA flows, CAD infrastructure, IP integration, PDK readiness, foundry requirements, and vendor dependency management. Experience with pre-silicon validation platforms such as simulation, emulation, FPGA prototyping, or hardware/software co-validation. Experience driving complex cross-functional programs with multiple engineering teams, technical dependencies, external vendors, and aggressive schedules. Preferred Qualifications Strong technical judgment with the ability to manage trade-offs across performance, power, area, cost, schedule, quality, and risk. Excellent communication, organizational, leadership, and stakeholder-management skills. Ability to influence without authority across global, cross-functional, and cross-cultural teams. Ability to operate independently in a fast-paced, ambiguous, high-growth environment. Experience with high-speed connectivity, SerDes, PHY, PCIe, CXL, Ethernet, networking, switching, or AI infrastructure silicon. Salary range is CAD 195,000 to CAD 240,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.Job Description  We are looking foraSeniorDesign Verification Engineer with proven experience in all aspects of verification in UVM and C/C++. The candidate must have experience using high level programming languages such as C/C++ to communicate with System Verilog and/or UVM based environments to aid RTL simulation,CoSimulationand Emulation.  Basic Qalifications:  Strong academic and technical background in electrical engineering. At minimum, a Bachelor’s in EE is required, and a Maser’s is preferred.  ≥2years’ experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications.  Professional attitude with the ability to prioritize a dynamic list of multiple tasks, to plan and prepare for customer meetings in advance, and to work with minimal guidance and supervision.  Entrepreneurial, open-mind behavior and can-do attitude. Think and act fast with the customer in mind!  Authorized to work in Canada and start immediately.  Required Experience: Experience with integrating C/C++ in System Verilog environments using DPI/PLI  Ability to use scripting tools (Perl/Python) to automate verification infrastructure.  Experience in developing infrastructure and tests in a hybrid directed and constrained random environments  Must be able to work independently to develop test-plans, and related test-sequences in UVM to generate stimuli and work collaboratively with RTL designers to debug failures.  Develop user-controlled random constraints in transaction-based verification methodology. Experience writing assertions,coverproperties and analyzing coverage data  Must have prior experience using Verification IPs from 3rd party vendors for communication protocols such as PCI-Express (Gen-3 and above), Ethernet, Infiniband, DDR, NVMe, USB, etc.  Develop VIP abstraction layers to simplify and scale verification deployments  Preferred Experience: S/W debugging for SoC based designs in the area of kernel/device-drivers/u-boot  Physical Layer, Link Layer and Transaction Layer verification expertise in PCIe protocol.  Experience in memory technologies like DDR4/DDR5/HBM.  Experience with FPGA-based verification/emulation.  Base salary range is $125,000 CAD -$180,000 CAD, and will be determined based on the candidate's capabilities and employees in similar positions.We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.Job Description  We are looking for a Principal Design Verification Engineer with proven experience in all aspects of verification in UVM and C/C++. The candidate must have experience using high level programming languages such as C/C++ to communicate with System Verilog and/or UVM based environments to aid RTL simulation, CoSimulation and Emulation.  Basic Qualifications:  Strong academic and technical background in electrical engineering. At minimum, a Bachelor’s in EE is required, and a Maser’s is preferred.  ≥8years’ experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications.  Professional attitude with the ability to prioritize a dynamic list of multiple tasks, to plan and prepare for customer meetings in advance, and to work with minimal guidance and supervision.  Entrepreneurial, open-mind behavior and can-do attitude. Think and act fast with the customer in mind!  Authorized to work in Canada and start immediately.  Required Experience: Experience with integrating C/C++ in System Verilog environments using DPI/PLI  Ability to use scripting tools (Perl/Python) to automate verification infrastructure.  Experience in developing infrastructure and tests in a hybrid directed and constrained random environments  Must be able to work independently to develop test-plans, and related test-sequences in UVM to generate stimuli and work collaboratively with RTL designers to debug failures.  Develop user-controlled random constraints in transaction-based verification methodology. Experience writing assertions, cover properties and analyzing coverage data  Must have prior experience using Verification IPs from 3rd party vendors for communication protocols such as PCI-Express (Gen-3 and above), Ethernet, Infiniband, DDR, NVMe, USB, etc.  Develop VIP abstraction layers to simplify and scale verification deployments  Preferred Experience: S/W debugging for SoC based designs in the area of kernel/device-drivers/u-boot  Physical Layer, Link Layer and Transaction Layer verification expertise in PCIe protocol.  Experience in memory technologies like DDR4/DDR5/HBM.  Experience with FPGA-based verification/emulation.  Base salary range is $165,000 CAD -$210,000 CAD, and will be determined based on the candidate's capabilities and employees in similar positions.We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.