Cake 找工作

Company Overview This opportunity is with a top-tier RD division backed by a globally recognized technology group, focusing on next-generation AI and robotics innovation. The team works on cutting-edge domains such as Autonomous Systems, Embodied AI, and Cyber-Physical Systems. Operating with the agility of a startup and the resources of a large enterprise, the organization brings together world-class engineers and researchers in a fully English-speaking, international environment. As the company accelerates its “AI-first” strategy, this role sits at the center of a major shift toward physical AI and intelligent systems — offering a rare chance to work on impactful, real-world AI applications at scale. What You’ll Do Lead a team developing autonomous systems and robotics software platforms Stay hands-on in system architecture, key module development, and technical decision-making Establish engineering best practices (code quality, testing, CI/CD, documentation) Collaborate cross-functionally with hardware engineers, AI researchers, and product teams Own project planning, resource allocation, and technical roadmaps Build and scale a high-performing engineering team and culture Tech Stack Programming: Python, C++, Go, JavaScript / TypeScript Systems: Distributed Systems, Microservices Architecture Domains: Autonomous Systems / Robotics / Embedded / Real-time Systems Infrastructure: Cloud Platforms, DevOps, CI/CD

公司介紹 我們的客戶是一家專注於 Physical AI 與數位孿生（Digital Twin）技術 的 AI 新創團隊，致力於打造能夠讓 AI 在虛擬環境中訓練、學習並優化決策的下一代平台，並將最佳策略部署回真實世界場域。 團隊核心技術結合 AI、3D 模擬、運籌優化與大型場域建模，應用於智慧製造、自動化物流與高精密產業等場景，協助企業在虛擬工廠中完成策略模擬與 AI 訓練，大幅提升建置效率與營運決策能力。 公司獲得 國際 GPU 生態系與多家產業資本支持，並與大型科技與製造企業合作，是少數專注於 Sim-to-Real / Real-to-Sim AI 應用落地 的技術團隊。 如果你對 AI + Simulation + Robotics / Automation 的跨領域技術有興趣，這將是一個能直接參與核心產品與演算法設計的機會。 工作內容 你將加入核心演算法研發團隊，負責設計並優化應用於 大型數位孿生場域的演算法模型，協助解決複雜環境中的路徑規劃、排程與資源配置問題。 主要職責包含： 建立與設計演算法模型（如圖論、網格建模、路徑規劃或優化模型） 從 3D 環境與場域資料中建構抽象模型並設計解法 設計並實作高效能演算法模組（Python 為主） 使用 GPU 加速工具優化大型資料處理或模擬效能 與產品與工程團隊合作，將演算法整合至平台系統 測試與評估不同策略表現並持續優化 使用技術 Python CUDA / GPU Parallel Computing PyTorch Algorithm Design / Data Structures Graph Theory / Path Planning 3D Simulation / Digital Twin Optimization / Scheduling

公司介紹 這是一家高速成長的 AI 新創團隊，專注於 Physical AI 與 Industrial AI 的落地應用。團隊致力於打造能將真實世界工業環境快速轉換為高擬真模擬場景的 AI 平台，讓 AI 能在虛擬環境中進行訓練與策略優化，最終部署至真實工業系統。 公司產品結合 3D Simulation、Digital Twin 與 Reinforcement Learning 技術，讓企業可以在虛擬世界完成複雜系統的訓練與測試，大幅降低現實環境的成本與風險，並加速智慧製造與自動化的導入。 團隊由多位具創業與深度技術背景的成員組成，目前已獲得 國際級 AI 科技公司與知名投資機構支持，並與高端製造及半導體產業合作。工程師將有機會參與 AI + Simulation + Robotics 的前沿技術應用，直接將研究級技術落地至真實世界場景。 工作內容 作為 Senior Reinforcement Learning Engineer，你將負責透過強化學習技術優化自動化系統與工業場景中的 AI 決策能力，並在模擬環境中訓練可部署於真實世界的 AI 模型。 你將有機會參與 AI 在 工業自動化、機器人與智慧製造場景中的實際應用。 主要職責包含： 在 NVIDIA Isaac Sim 等模擬平台上建立與訓練強化學習模型 設計並實作 state space、action space 與 reward function 開發與優化 RL policy（如 Q-learning / Policy-based methods） 與 AI / Simulation / 3D 團隊合作進行系統模擬與模型訓練 持續調整模型與參數，提升策略效率與系統穩定度 將模擬環境中的最佳策略導入實際工業系統 使用技術 Python PyTorch / TensorFlow Reinforcement Learning Algorithms NVIDIA Isaac Sim Simulation / Digital Twin Robotics / Automation Systems

🚀 公司介紹 我們是一間專注於實體 AI（Physical AI）與工業 AI 落地應用的前瞻性科技新創。作為全台灣第一間獲得全球晶片巨頭 NVIDIA 直接投資的指標性新創，我們更在 2025 年榮獲國際知名科技媒體《The Information》評選為「全球最具潛力的 50 家新創公司」之一（也是唯一入選的台灣企業）。 我們獨創的 AI 原生生成平台，專注於將虛實整合（Real-to-Sim 與 Sim-to-Real）帶入精密製造、半導體與自動化倉儲等核心產業。透過自研的 3D 與 AI 整合模型，將複雜的 2D 藍圖秒級轉化為具備物理運動邏輯的 3D 高擬真環境，讓 AI 可以在虛擬世界中進行萬次訓練與策略迭代，最終完美部署回真實世界。 【為什麼你該加入我們？】 與頂尖技術並肩： 創始團隊擁有多次成功創業經驗，團隊成員皆為業界頂尖高手，在這裡你可以「與聰明的人一起工作」，挑戰最前沿的 AI 落地場景。高度自由與信任： 我們提倡開放、傾聽與透明的文化，採用 Hybrid Work（混合辦公，一週一天遠端），給予夥伴高度的時間與空間主導權。頂級工學配備： 進辦公室提供全套升降桌椅、27 吋大螢幕，讓你高效工作不傷身。 📋 工作內容 我們正在尋找一位熟悉 LLM / VLM 與 Agentic Workflow 開發的 AI Copilot Engineer，您將負責將內部各類專家工作流程（如 3D pipeline、simulation stack 等）轉化為可落地的 AI Copilot / Agent 系統。 設計、實作與優化面向專家工作流程的 Agentic Workflow 與 AI Copilot 架構。整合 LLM、VLM 與工具調用機制，設計規劃 Skill / Tool / MCP 架構以提升任務執行力。評估與串接 Claude Code、Codex、OpenClaw 或其他主流 Agent Framework。設計精準的 Prompt、Planning、Execution 與 Error Handling 機制。與產品及工程團隊緊密合作，定義高價值的 AI 應用 Use Case 並推動落地。撰寫結構化的技術與系統設計文件。 🛠 使用的技術 (Tech Stack) LLM / VLM / Multi-agent FrameworksAgentic Coding / Orchestration Tools (Claude Code, OpenClaw, MCP)Python / C++PyTorch / TensorFlowNVIDIA Isaac Sim (強化學習應用) 🎁 福利制度 高競爭力薪酬： 具市場競爭力的優渥底薪，並提供員工分紅與實質的績效獎金。優於勞基法假勤： 彈性安排假期，並擁有高度自由的彈性遠距工作日（Remote Day）。豐富團隊活動： 舒適的混合辦公環境、生日與三節禮金、不定期舉辦高質感聚餐與團隊凝聚活動。人才推薦獎勵： 設有優秀人才推薦獎金制度，邀請志同道合的夥伴一同高速成長。

WorldQuant develops and deploys systematic financial strategies across a broad range of asset classes and global markets. We seek to produce high-quality predictive signals (alphas) through our proprietary research platform to employ financial strategies focused on market inefficiencies. Our teams work collaboratively to drive the production of alphas and financial strategies – the foundation of a balanced, global investment platform. WorldQuant is built on a culture that pairs academic sensibility with accountability for results. Employees are encouraged to think openly about problems, balancing intellectualism and practicality. Excellent ideas come from anyone, anywhere. Employees are encouraged to challenge conventional thinking and possess an attitude of continuous improvement. Our goal is to hire the best and the brightest. We value intellectual horsepower first and foremost, and people who demonstrate an outstanding talent. There is no roadmap to future success, so we need people who can help us build it.Location: West Palm Beach, FL or New York, NY The Role: We are seeking an exceptionally talented AI Scientist to join the Artificial Intelligence team at WorldQuant. The successful candidate will: Conduct research in the Machine Learning field to improve multiple aspects of the investment pipeline Produce trading or predictive signals using innovative Machine Learning algorithms Apply the latest in LLM based agentic technology to develop and test innovative trading signals and algorithms Implement signal compression and combination techniques using Machine Learning tools Implement state of the art machine learning algorithms Design deep learning architectures. Develop model frameworks for investment professionals Collaborate with portfolio managers and researchers to optimize machine learning algorithms Communicate optimally with team members, researchers, and portfolio managers What You’ll Bring: PhD degree in a quantitative or highly analytical field (e.g., Computer Science, Physics, Mathematics, Statistics, or a related field) 2+ years of research or work experience applying Machine Learning in innovative ways to complex problems Graduated at the top of your respective educational program, with excellent problem-solving abilities, insight, and judgment with a strong attention to detail Demonstrated ability to program. Strong development skills and proficiency in C++, Python, and PyTorch. Demonstrated science aptitude via record of creativity and inventions. Ability to run experiments and perform statistical inference. Experience with software development tools and practices, such as version control (e.g., Git), continuous integration, and testing frameworks Advanced practitioner-level knowledge of statistical inference, machine learning, software solvers, and/or mathematical optimization Strong communication skills; ability to express complex concepts in simple terms Our Benefits: Core Benefits: Fully paid medical and dental insurance for employees and dependents, flexible spending account, 401k, fully paid parental leave, generous PTO (paid time off) that consists of: twenty vacation days that are pro-rated based on the employee’s start date, at an accrual of 1.67 days per month, three personal days, and ten sick days. Perks: Employee discounts for gym memberships, wellness activities, healthy snacks, casual dress code Training: learning and development courses, speakers, team-building off-site Employee resource groups Pay Transparency: WorldQuant is a total compensation organization where you will be eligible for a base salary, discretionary performance bonus, and benefits. To provide greater transparency to candidates, we share base pay ranges for all US-based job postings regardless of state. We set standard base pay ranges for all roles based on job function and level, benchmarked against similar stage organizations. When finalizing an offer, we will take into consideration an individual’s experience level and the qualifications they bring to the role to formulate a competitive total compensation package. The Base Pay Range For This Position Is $150,000 - $200,000 USD. At WorldQuant, we are committed to providing candidates with all necessary information in compliance with pay transparency laws. If you believe any required details are missing from this job posting, please notify us at [email protected], and we will address your concerns promptly.By submitting this application, you acknowledge and consent to terms of the WorldQuant Privacy Policy. The privacy policy offers an explanation of how and why your data will be collected, how it will be used and disclosed, how it will be retained and secured, and what legal rights are associated with that data (including the rights of access, correction, and deletion). The policy also describes legal and contractual limitations on these rights. The specific rights and obligations of individuals living and working in different areas may vary by jurisdiction. Copyright © 2025 WorldQuant, LLC. All Rights Reserved.WorldQuant is an equal opportunity employer and does not discriminate in hiring on the basis of race, color, creed, religion, sex, sexual orientation or preference, age, marital status, citizenship, national origin, disability, military status, genetic predisposition or carrier status, or any other protected characteristic as established by applicable law.

Req ID: 135134Remote Position: YesRegion: AsiaCountry: IndiaState/Province: ChennaiCity: Guindy, ChennaiSummaryThe AI Data Analyst will design, develop, document, and maintain data pipelines and architectures, working closely with IT, Data Engineering, and Data Science teams to deliver artificial intelligence and machine learning solutions. Provide technical support on selected AI systems (for example, Generative AI applications, agentic workflows, and internal data integration tools) and participate in enterprise IT and AI projects.Detailed DescriptionPerforms tasks such as, but not limited to, the following:•Collaborate with IT and Data Science teams to gather technical requirements, ensuring data availability and system readiness for AI integration.•Design, build, and optimize data pipelines (ETL/ELT) to prepare, clean, and structure datasets for machine learning models and large language models (LLMs).•Work within Google Cloud environments to manage datasets, orchestrate data flows, and support model deployment.•Respond to system, API, and data pipeline problems by troubleshooting data anomalies, analyzing logs, and determining the technical course of action.•Develop and maintain technical documentation for data architectures, API integrations, and AI workflows.•Participate in the configuration, testing, and deployment of agentic AI development and workflow orchestration platforms.Knowledge/Skills/Competencies•Strong technical collaboration and teamwork skills within an IT environment.•Good analytical, technical, troubleshooting, and problem-solving skills.•Good technical documentation skills, including mapping technical architectures, data pipelines, and system integrations.•Good understanding of data engineering concepts, database management, and the IT software development life cycle.•Proficient coding skills in Python (including data libraries like Pandas and NumPy) and robust SQL skills for complex database querying and data manipulation.•Understanding of core machine learning concepts and familiarity with Generative AI tools, agentic development, and AI orchestration platforms (e.g., Flowise AI, Zapier, n8n).•Familiarity with Google Cloud data and AI technologies, specifically Gemini, BigQuery, and Vertex AI.•Understanding of interrelations between IT infrastructure components (cloud environments, APIs, databases, data pipelines, servers, etc.).• Physical Demands• Duties of this position are performed in a normal office environment.• Duties may require extended periods of sitting and sustained visual concentration on a computer monitor or on numbers and other detailed data. Repetitive manual movements (e.g., data entry, using a computer mouse, using a calculator, etc.) are frequently required.Typical Experience•Minimum 3+ years of professional experience required .•1 to 3 years of relevant experience in similar rolesTypical Education•Bachelors Degreeor consideration of an equivalent combination of education and experience.•Educational Requirements may vary by GeographyNotesThis job description is not intended to be an exhaustive list of all duties and responsibilities of the position. Employees are held accountable for all duties of the job. Job duties and the % of time identified for any function are subject to change at any time.Celestica is an equal opportunity employer. All qualified applicants will receive consideration for employment and will not be discriminated against on any protected status (including race, religion, national origin, gender, sexual orientation, age, marital status, veteran or disability status or other characteristics protected by law).At Celestica we are committed to fostering an inclusive, accessible environment, where all employees and customers feel valued, respected and supported. Special arrangements can be made for candidates who need it throughout the hiring process. Please indicate your needs and we will work with you to meet them.COMPANY OVERVIEW:Celestica (NYSE, TSX: CLS) enables the world’s best brands. Through our recognized customer-centric approach, we partner with leading companies in Aerospace and Defense, Communications, Enterprise, HealthTech, Industrial, Capital Equipment and Energy to deliver solutions for their most complex challenges. As a leader in design, manufacturing, hardware platform and supply chain solutions, Celestica brings global expertise and insight at every stage of product development – from drawing board to full-scale production and after-market services for products from advanced medical devices, to highly engineered aviation systems, to next-generation hardware platform solutions for the Cloud.Headquartered in Toronto, with talented teams spanning 40+ locations in 13 countries across the Americas, Europe and Asia, we imagine, develop and deliver a better future with our customers.Celestica would like to thank all applicants, however, only qualified applicants will be contacted.Celestica does not accept unsolicited resumes from recruitment agencies or fee based recruitment services.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.Role Overview Astera Labs is establishing a strategic RD center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a highly skilled Physical Design Engineer specializing in EMIR CAD to join our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful technical ownership in a new site, executing the backend power methodologies for chips that power the world's largest AI clusters. As a Physical Design Engineer, you will be a core technical contributor ensuring the power robustness and long-term reliability of our high-performance connectivity silicon. You will continuously develop the Electro-Migration and IR Drop (EMIR) flow, working closely at the intersection of Physical Design, Analog/Mixed-Signal design, and Package Engineering. Key Responsibilities Take responsibility on IR drop analysis and signal/power electromigration (EM) flow Implement and maintain robust EMIR flows and methodologies using industry-standard tools (Ansys RedHawk-SC, Cadence Voltus, or equivalent) Collaborate closely with Analog/SerDes designers to integrate current profiles and ensure robust power delivery to sensitive high-speed IP blocks Partner with Package Design engineers to perform Chip-Package-System (CPS) co-analysis flow Understand root-cause analysis for voltage drop violations and EM risks Support silicon bring-up by correlating simulation results with actual silicon measurements and yield data Basic Qualifications Bachelor's or Master's degree in Electrical Engineering or a related technical field 5+ years of hands-on experience in EMIR/Power Integrity analysis for high-performance SoCs or high-speed connectivity products Strong proficiency in industry-standard EMIR tools flow development (Ansys RedHawk/RedHawk-SC, or Cadence Voltus) Deep understanding of EM/IR challenges in advanced FinFET nodes (7nm, 5nm, 3nm) Basic understanding of Place Route flows, power grid synthesis, extraction (RC), and standard cell architecture Proven Proficiency in Python in required, Tcl or Perl preferable for flow automation and data parsing Deep understanding of the RedHawk tool, including efficient use of MapReduce and other Ansys proprietary capabilities (including potential use of ad-hoc SDC for context and LSO – Logic State Override) Strong understanding of required inputs for creating Scenarios and Analysis Views Deep understanding of standard cell and IP abstractions (APL, LIB, AVM), including IP waveform construction from PWL (sim2iprof) Preferred Experience Experience performing Chip-Package-System (CPS) thermal and power co-simulation Familiarity with thermal analysis tools and their interaction with electrical performance Experience working with sign-off criteria and margins for high-volume production chips Basic understanding of timing and PR Good understanding of EM, including deterministic EM (DC, peak, RMS) Basic understanding of statistical EM and reliability concepts (SEB, Black’s Equation, FIT, MTTF) Basic understanding of packaging, top metal layers, MIM capacitor usage, and power distribution We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.Role Overview Astera Labs is establishing a strategic RD center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a visionaryPhysical Design Engineer to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, defining the backend execution and methodologies for chips that power the world's largest AI clusters. As aPhysical Design Engineer, you will be a key architect of our silicon's physical reality. You won't just execute a flow—you will help establish our local execution culture and technical standards, owning the transformation of complex logic into high-performance silicon. You will drive the physical implementation journey from synthesis through signoff, ensuring our connectivity solutions meet the extreme performance, power, and area targets required for next-generation AI infrastructure. If you thrive on solving complex challenges in deep-submicron processes and want to shape the backend methodology for AI infrastructure connectivity, this is your opportunity. Key Responsibilities Physical Implementation Execution Be part of the founding Backend team in Israel, playing a critical role in establishing local execution culture and technical standards Take full responsibility for physical implementation journey including Synthesis, Floorplanning, Place Route, and Clock-Tree Synthesis (CTS) Own macro-level implementation with deep hands-on experience in floorplanning and complex routing Signoff Design Integrity Drive final stages of design integrity, owning Timing signoff (STA), Physical Verification (DRC/LVS), and Reliability analysis (EMIR) Ensure first-pass silicon success through rigorous signoff flows and analysis Apply Logic Equivalence Checking (LEC) and other verification techniques to guarantee design correctness Methodology Development Cross-Functional Collaboration Participate in defining and refining Backend methodologies with autonomy to improve workflows and tool automation Work closely with Architecture, Design, and DFT teams to navigate challenges of advanced process nodes and high-speed connectivity Leverage scripting and automation to make engineering environment faster and more robust Basic Qualifications Bachelor's degree in Electrical Engineering or related technical field 3+ years of hands-on experience in Physical Design at semiconductor companies Proven expertise in the full RTL2GDS flow with deep hands-on experience in macro-level implementation, floorplanning, and complex routing Experience working with advanced process technologies (7nm and below) Solid experience with signoff tools and flows including STA, Logic Equivalence Checking (LEC), DRC, and EMIR analysis Proficiency in TCL or Python scripting to drive EDA tool flows and automate repetitive tasks Preferred Qualifications Experience with full-chip level implementation and integration Knowledge of Power and Noise analysis (SI/PI) to optimize high-performance silicon Familiarity with Design-for-Test (DFT) requirements and their impact on physical layout Experience with industry-standard EDA tools (Synopsys Fusion Compiler/ICC2, Cadence Innovus) Background in high-speed interface designs or connectivity protocols We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.Role Overview Astera Labs is establishing a strategic RD center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we are seeking a motivatedPhysical Design Studentto join our founding local engineering team. This is a unique opportunity to kickstart your career in the semiconductor industry. Working alongside senior industry veterans, you will gain hands-on experience in backend execution and advanced methodologies for cutting-edge chips that power the world's largest AI clusters. If you are passionate about silicon hardware, eager to learn, and thrive on solving complex engineering challenges, this role offers the perfect bridge between your academic studies and a high-impact career. Key Responsibilities Guided Implementation Learning Partner with and learn from senior engineers to support the physical implementation journey, including synthesis, floorplanning, Place Route (PR), and Clock-Tree Synthesis (CTS) Assist in macro-level implementation and develop hands-on skills in complex layout routing Participate in deep-submicron process challenges under close professional mentorship Signoff Design Integrity Support Assist in running engineering checks for design integrity, including Static Timing Analysis (STA), Physical Verification (DRC/LVS), and Reliability analysis (EMIR) Learn to apply Logic Equivalence Checking (LEC) to help guarantee design correctness Gain exposure to the rigorous flows required to ensure first-pass silicon success Scripting Cross-Functional Collaboration Leverage and develop scripting tools to automate repetitive tasks and optimize the engineering environment Collaborate with Architecture, Design, and DFT teams to understand how different chip design disciplines intersect Actively participate in team reviews and technical discussions to ramp up backend methodologies Basic Qualifications Pursuing a Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related technical field Strong academic foundation in digital systems, VLSI design, or semiconductor devices. Familiarity with Python, TCL, Bash, or Perl. Ability to work at least 2 days per week at our Haifa/Tel Aviv Center A "can-do" attitude with a passion for solving complex technical challenges Fluent in Hebrew and English with the ability to work effectively in a team environment Preferred Qualifications Prior experience from a previous VLSI/Hardware student position or a significant academic project in physical design/VLSI Hands-on university lab experience with industry-standard EDA tools (e.g., Synopsys Fusion Compiler/ICC2, Cadence Innovus) Understanding of basic verification concepts (STA, DRC, LVS) Fast learner with a proactive attitude and a passion for deep-tech hardware infrastructure We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.As an Astera Labs Physical Design/CAD Engineer you will play a crucial role in driving the planning, coordination, and execution supporting the design of Astera Labs' portfolio of connectivity ASICs used in the world's leading cloud service providers, server and network OEMs. This role requires RTL to GDS ownership across design stages (Synthesis/PnR/STA/Signoff), deep technical expertise, and close collaboration with RTL and verification teams to ensure robust full-chip signoff.This role is fully on-site and in-person. Key Responsibilities As Physical Design CAD Engineer you will support and build flows for world class EDA tools. Drive various Physical Design flow related activities, ensuring robust signoff across complex SoCs or sub-systems. Architect and recommend flow improvements and enhance existing methodology for high performance design. Good understanding of flow development related to backend tools like Synthesis/PnR/Extraction/DRC/LVS etc. Work with cross function teams to define requirements and specifications to achieve best PPA Opportunity to own a small block partition and closure (PnR, STA, DRC and LVS etc) based on interest and capacity Partner closely with design, implementation, and verification teams to drive block/top convergence, providing sign-off level expertise and guidance. Basic Qualifications Bachelor’s in Electrical Engineering or Computer Science required; Master’s preferred. 2-10 years of experience in PnR and sign-off for complex SoCs in Server, Storage, or Networking applications. Expertise in PnR, Extraction, Timing closure, EM-IR, Formality and DRC/LVS at both block and full-chip level. Strong knowledge of synthesis, place-and-route, extraction, and equivalence checking flows in advanced nodes (7nm or below). Proficiency with Cadence and/or Synopsys physical design/STA toolchains. Strong scripting ability (Tcl, Python, Perl). Ability to work independently with strong prioritization and a professional, customer-focused mindset. Preferred Experience Knowledge of agentic AI solutions is a plus. Experience working with EDA/IP vendors for both RTL and hard-macro integration. Familiarity with high-speed SERDES and Ethernet PHY timing challenges. Knowledge of ECO methodologies, DFT tools, and test coverage analysis. Your base salary will be determined based on your experience and the pay of employees in similar positions. The base salary range is $135,000 USD - $165,000 USD for Senior Level, and $160,000 USD - $195,000 USD for Staff Level. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.