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Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. 8 years of experience in ASIC development with Verilog/SystemVerilog, VHDL. Experience with ASIC design verification, synthesis, timing/power analysis, and Design for Testing (DFT). Experience in micro-architecture and design of IPs and subsystems in Networking domain such as packet processing, bandwidth management, congestion control,

Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. 8 years of experience in ASIC development with Verilog/SystemVerilog, VHDL, or Chisel. 4 years of experience in people management, developing employees. Experience in micro-architecture and design of Machine Learning IPs or Graphics IPs, handling Low Precision/Mixed Precision Numerics. Experience in ASIC/SoC design verification, synthes

Minimum qualifications: 5 years of experience in designing RTL digital logic using System Verilog for FPGA/Application-Specific Integrated Circuit (ASIC). Experience in scripting language such as Perl or Python. Experience in area, power and performance optimization. Preferred qualifications: Master's degree or PhD in Electrical Engineering, Computer Science, or equivalent practical experience. Experience in design and development of security blocks or crypto blocks. About the job Be part of a d

Minimum qualifications: Bachelor’s degree in Electrical Engineering or Computer Engineering, or equivalent practical experience. 15 years of experience in ASIC RTL design. Experience with RTL design using Verilog/System Verilog and microarchitecture. Experience with ARM-based SoCs, interconnects and ASIC methodology. Preferred qualifications: Master’s degree in Electrical Engineering or Computer Engineering. Experience driving multi-generational roadmap for IP development. Experience leading int

Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Science, or equivalent practical experience. 3 years of experience in RTL coding using Verilog or Systemverilog language. Experience in STA closure, DV test-plan review, and coverage analysis of the sub-system and chip level verification. Preferred qualifications: Master's degree in Electrical Engineering, Computer Science, or a related field. Knowledge in one or more of these areas: Process Cores, Interconnects, Debug

Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. 15 years of experience in ASIC/SoC development with Verilog/SystemVerilog. Experience in micro-architecture and design of IPs and Subsystems. Experience in ASIC/SoC design verification, synthesis, timing/power analysis, and Design for Testing (DFT). Preferred qualifications: Experience with programming languages (e.g., Python, C/C++ or

Minimum qualifications: Bachelor's degree in Computer Science, Electrical Engineering, Computer Engineering, a related technical field, or equivalent practical experience. 3 years of experience in ASIC/SoC development with Verilog/SystemVerilog. Experience in design of Machine Learning IPs, or graphics IPs, managing low precision/mixed precision numerics. Experience in ASIC design verification, synthesis, timing/power analysis, and Design for Testing (DFT). Preferred qualifications: Experience w

We are looking for digital engineer to join us together to become world-class IC design house to help people all over the world.

We are looking for digital engineer to join us together to become world-class IC design house to help people all over the world.

1.Creating verification plans of complex digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios. 2.Create verification environments using SystemVerilog, SystemC or UVM. 3.Identify and write all types of coverage measures for stimulus and corner-cases. 4.Debug tests with design engineers to deliver functionally correct design blocks. 5. Close coverage measures to identify verification holes and to sh