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Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.Role SummaryWe are seeking a technically strong Chief of Staff to the Head of Engineering who will also lead Engineering Program Management across Silicon Engineering. This role is a force-multiplier for Engineering leadership — driving org scale, decision velocity, and execution rigor. The ideal candidate brings deep technical fluency, structured problem-solving, and the ability to drive outcomes through influence rather than hierarchy. The role is fully in person in San Jose. Responsibilities — What You Will Own 1) Chief of Staff to Head of Engineering • Drive operational cadence: engineering all hands, staff meetings, agenda/material prep, tech talks, university engagements, action follow-through, and leadership syncs.• Frame and resolve high-leverage decisions — proactively surface blockers (technical, operational, organizational) before they escalate.• Manage escalations and organizational friction — diagnose root causes, coordinate resolution paths, and ensure durable fixes.• Partner cross-functionally with Hardware, Product, and Quality teams to ensure clarity of communication, alignment on priorities, and disciplined follow-through on decisions.• Support org design, headcount planning, and hiring prioritization for engineering teams.• Maintain alignment across functions through clear messaging and communication, validate exitance and validation of processes• Navigate org dynamics, build trust, and constructively challenge assumptions; maintain psychological safety.• Support the head of engineering with administrative and org related activities 2) Lead ASIC Tape out Management (Silicon Programs) • Status management — collect and track status across functions contributing to ASIC tapeouts.• Milestone tracking — maintain methodology checklists and boundary agreements to ensure schedule adherence.• IP and vendor tracking — own visibility into IP deliveries, version inventory, vendor issues, and escalation loops.• Quality documentation — monitor quality KPIs, ensure engineering documentation completeness.• Requirements tracking — ensure PRDs/features are captured, tracked, baselined.• Resource monitoring — track compute, hardware, storage consumption and thresholds.• Internal reporting — generate status reporting for Silicon Engineering leadership. 3) Influence Without Authority • Drive cross-engineering outcomes through credibility, clarity, and follow-through — not hierarchy.• Create order in ambiguous spaces; shape scope where it is undefined. Qualifications • 10+ years in semiconductor/SoC/ASIC or adjacent high-complexity engineering environment (e.g., CPU/IP/System companies).• Proven success in Chief of Staff, Staff Program Manager, TPM Director, or similar technical leadership-enablement role. • Strong technical acumen — able to understand engineering trade-offs and make decisions with limited information, challenge assumptions, and earn credibility with senior ICs.• Demonstrated experience running program cadence for complex silicon programs (tapeout, IP integration, etc.).• Proven ability to organize complex workflows and drive consistent follow-through.• High EQ and organizational awareness; can navigate tension and align diverse viewpoints.• Exceptional written/verbal communication, structured thinking, and execution discipline.• Prior experience in leading RTL2GDSII chip design is a huge plus. What Success Looks Like • Engineering leadership spends more time on strategic and technical decisions, less on coordination.• Milestones hit with fewer escalations and clearer accountability.• Status, risks, and decisions are crisp — never ad hoc or late.• Teams feel supported, not policed — trust increases, friction decreases without compromising on accountability .• Ambiguity decreases over time as clarity and execution rhythm scale with the org. Salary range is $216,000 to $300,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.Astera Labs is seeking an exceptional Senior Director System Validation to lead our AI Fabric Validation organization. Connectivity is a critical component of every AI accelerator deployment and hyperscale data center architecture. As part of the AI Fabric Engineering group, you will play a key role in ensuring that Astera Labs’ fabric solutions perform at scale and deliver system-level performance across the most demanding AI and ML workloads. This role offers a unique opportunity to shape validation strategy for cutting-edge connectivity silicon and gain deep insight into next-generation AI infrastructure platforms. Your primary responsibility will be to build and lead a world-class validation organization tasked with validating all silicon, firmware, and system-level solutions at scale, ensuring performance, reliability, and production readiness across customer deployments. Job Description Seeking a strong technical leader who has delivered multiple SoC products. Lead and scale the system validation organization for Astera Labs' AI fabric portfolio, building a high-performing team across multiple concurrent product programs. Understand the performance and functionality requirements of our AI fabric switches to enable customers to develop Data Center systems using Astera Labs' connectivity products for AI and ML applications. Own comprehensive validation strategies for AI fabric switch products. Drive execution through scalable automation platforms and data-centric testing with automated reporting and specification compliance verification. Collaborate cross-functionally with Architecture, Hardware, Firmware, and Software teams to influence product requirements and ensure validation excellence. Ensure timely bring‑up of new silicon and platforms, driving root‑cause analysis and cross‑functional debug of hardware, firmware, and system issues. Deliver high‑confidence validation results that support product qualification, customer sampling, and mass production readiness. Engage directly with key customers to understand their requirements and highlight the unique capabilities of Astera Labs' solutions. The ideal candidate brings deep expertise in silicon/system validation, a strong architectural mindset, and a proven ability to scale organizations in fast‑moving, high‑performance computing environments. Work closely with silicon design, architecture, Firmware, software engineering teams to ensure cohesive validation strategies. Drive a culture of technical excellence, accountability, and continuous improvement. Manage resource planning, and vendor/partner relationships. Basic Qualifications Strong academic background in Electrical or Computer Engineering. Bachelor's required, Master's preferred. ≥15 years' experience supporting or developing complex SoC/silicon products for Server, Storage, Networking applications and high‑performance hardware companies. ≥5 years hands-on experience with Silicon/System bring-up, validation, and debug, including in customer systems. ≥5 years building high performance Engineering teams and validation methodologies. Deep understanding of CPU, GPU, SoC, or AI/ML accelerator architectures, including memory subsystems, I/O, power management, and firmware interactions. Expertise in validation methodologies: pre‑silicon simulation/emulation, post‑silicon bring‑up, system validation, stress testing, and performance characterization. Strong background in debug methodologies, lab infrastructure, and automation frameworks. Excellent communication skills and ability to influence executives and cross‑functional partners. Entrepreneurial, open-minded behavior and can-do attitude. Think and act with the customer in mind! Preferred Experience ≥8 years leading validation teams planning, execution and maintaining project visibility. ≥10 years hands-on experience with Silicon/System bring-up, validation, and debug, including in customer systems. Thorough knowledge of high-speed protocols like PCIe, CXL, NVMe, or Ethernet. Deep understanding of High-Speed Signaling Principles and x86/ARM architecture, UEFI/Linux boot sequence. The base salary range is $240,000 USD - $300,000 USD. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.As aSenior Software Diagnostics Engineer onthe Astera Labs Hardware Engineering team you will be responsible for building diagnostics and manufacturing software to allow design, test, and manufacture of cutting-edge high-speed datacenter products. You will be working on a project from conception to the final production stage at contract manufacturer. The role requires a strong and broad software background and a good understanding of hardware design and manufacturing practices. At the same time, we welcome candidates with deep experience in smaller areas and desire to learn. Depending on your experience, you may be focusing on design/validation or automation/manufacturing. Key Responsibilities: Design, implement test production-grade diagnostics for high-speed digital boards and ASICS to help with hardware validation. Design, implement test manufacturing tests to validate mass production of digital boards used in data center networking product Bring-up newly manufactured boards and port the first level of software. Isolate and perform root-cause analysis of reported failures Support new platform software and hardware features Coordinate with the hardware engineering team on bring-up schedules and feature delivery Participate proactively in design discussions, design review and project management Basic Qualifications Bachelors in Computer Science/Computer Engineering or equivalent experience. Knowledge of modern software development Proficiency in Python, C or similar Ability to work cross-functionally in a fast-paced, highly technical environment. Required Experience 2+ years of Experience in subset of diagnostics, hardware bring-up, test or manufacturing automation Strong debugging skills across hardware, firmware, and system layers Preferred Experience/Nice to Have Experience working with datacenter-level complex electronic equipment bring-up/diagnostic/manufacturing Ability to read schematic/layout System debug experience Embedded programming and good knowledge of OS internals (Linux/Unix) Has knowledge of common interconnecting buses and interfaces such as PCIe, I2C, XAUI, 10G Ethernet drivers, FPGA, Switch chips, SSL offload, TCAM programming. Experience with DDR5 The base salary range is $120,000 - $195,000. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.Role OverviewAstera Labs is looking for a Principal Design Verification Engineer with a passion for breaking complex designs and developing innovative verification strategies for next-generation AI connectivity ASICs. You'll leverage your deep expertise in SystemVerilog, UVM, and hybrid verification methodologies to ensure the highest quality silicon supporting PCIe Gen 6/7, CXL, UALink, UCI, Ethernet, and DDR4/DDR5 protocols. In this role, you'll own the full verification lifecycle—from test planning through coverage closure—while collaborating with RTL designers, software teams, and system validation engineers. You'll drive verification of excellence, mentor team members, and contribute to methodology improvements that scale across multiple product lines in a fast-paced, high-impact environment. Key Responsibilities Verification Strategy Execution Define and execute comprehensive verification strategies using hybrid directed and constrained-random methodologies with an exceptional power, performance and area trade-off using silicon technologies better than 7nm. Own the full verification lifecycle from test plan development through coverage closure and tape-out sign-off Develop and deploy advanced coverage models to identify verification holes and ensure high-quality silicon Technical Problem Solving Debug complex design issues collaboratively with RTL designers, driving root cause analysis to resolution Implement formal verification techniques to complement simulation-based approaches Develop test sequences and stimulus generation for corner-case coverage Collaboration Leadership Partner with software and system validation teams to develop and execute test plans on emulation platforms Mentor junior verification engineers and drive best practices across the team Contribute to verification infrastructure improvements and automation initiatives Basic Qualifications Bachelor's degree in Electrical Engineering; Master's preferred 10+ years of experience verifying and validating complex SoCs for Server, Storage, and/or Networking applications Expert-level proficiency with SystemVerilog/UVM-based verification methodologies Proven ability to develop and execute test plans, stimulus generation, and coverage closure strategies Experience with industry-standard simulators, revision control systems, and regression infrastructure Strong debugging skills with ability to work independently and collaboratively with design teams Preferred Qualifications Master's degree in Electrical Engineering or related field Experience with Verification IPs for protocols such as PCIe (Gen 5+), CXL, Ethernet, DDR4/5, or similar Proficiency with formal verification methods and tools Working experience with scripting tools (Python/Perl) to automate verification infrastructure Experience with emulation platforms and hardware-software co-verification Background in cache verification or directed test methodologies Salary range is $185,000 to $230,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.About Astera Labs Astera Labs (NASDAQ: ALAB) is a pioneering fabless semiconductor company headquartered in Silicon Valley, driving the evolution of AI and cloud infrastructure through purpose-built connectivity solutions. As a leader in rack-scale architecture, Astera Labs is enabling the shift to AI Infrastructure 2.0, where compute is optimized at the rack level to support the demands of next-generation workloads. Our portfolio includes high-performance silicon, software, and system-level solutions that address critical bottlenecks in data movement across compute, memory, and networking domains. Leveraging technologies such as PCIe®, CXL®, Ethernet, and UALink™, we deliver scalable, interoperable platforms that empower hyperscale data centers to deploy AI and cloud services with greater efficiency and flexibility. We are committed to open standards, software-defined architectures, and continuous innovation as we work to expand our product offerings and customer engagements. We foster a collaborative environment for professionals passionate about solving complex challenges and shaping the future of intelligent infrastructure. Role Overview Astera Labs is seeking a strategic and proactive Senior Principal Category Sourcing Manager to lead sourcing initiatives across Corporate Services Operations, a category that spans a broad and dynamic range of enterprise needs. This includes sourcing for professional services (legal, finance, marketing, recruiting, and engineering consulting), IT infrastructure and equipment, corporate software tools, facilities and real estate services, and workplace operations. This role is foundational to enabling enterprise-wide operations and supporting business continuity, compliance, and employee productivity. You will be responsible for developing and executing category strategies, managing supplier relationships, and driving high-impact negotiations across a diverse set of internal stakeholders and external partners. You’ll also play a key role in vendor consolidation, spend governance, and process optimization to support Astera Labs’ rapid growth and evolving business needs. A Day in the Life In this role, you’ll be at the center of enabling Astera Labs’ enterprise operations. Your day is shaped by dynamic interactions across legal, finance, IT, and facilities teams, as you help translate business needs into sourcing strategies that drive efficiency, scalability, and value. You’ll navigate a diverse landscape of suppliers—from strategic consulting firms and software providers to facilities and real estate partners—building relationships and shaping agreements that support both immediate needs and long-term growth. Whether you're refining a framework for professional services sourcing, evaluating new IT platforms, or exploring ways to streamline corporate spend, your work will influence how the company operates and scales. This role offers a unique blend of strategic ownership and cross-functional engagement, where your decisions directly impact business continuity, employee experience, and operational excellence. Key Responsibilities Develop and execute sourcing strategies for corporate categories including professional services, IT infrastructure, facilities, real estate, and enterprise software. Lead supplier selection, negotiation, and contract execution including NDAs, MSAs, SOWs, and licensing agreements. Partner with internal stakeholders to align sourcing initiatives with business needs and operational goals. Drive vendor consolidation and strategic partnerships to improve service levels and reduce cost. Streamline procurement processes for high-volume, low-value purchases and support spend governance improvements. Monitor supplier performance, compliance, and service-level agreements (SLAs). Analyze market trends, cost structures, and supplier capabilities to inform sourcing decisions. Collaborate with logistics and procurement operations teams to support freight rate negotiations and global sourcing initiatives. Basic Qualifications Bachelor’s degree in Business, Supply Chain, Finance, or related field. 7+ years of experience in indirect sourcing, procurement, or supplier management across corporate categories. Proven experience negotiating contracts for professional services, IT infrastructure, facilities, and enterprise tools. Strong understanding of procurement operations, vendor management, and spend governance. Demonstrated ability to lead complex negotiations and manage supplier relationships across global teams. Preferred Qualifications Master’s degree in Business, Supply Chain Management, or related discipline. Experience with sourcing frameworks for legal, consulting, and engineering services. Familiarity with corporate IT tools, SaaS licensing models, and facilities management. Strong analytical, financial modeling, and contract management skills. Excellent communication and stakeholder engagement across technical and business functions. Why Join Us? Be part of a high-growth, innovation-driven company at the forefront of AI and cloud infrastructure. Work with diverse teams and strategic partners across the enterprise. Enjoy a collaborative culture that values ownership, agility, and continuous improvement. Competitive compensation, equity, and benefits package. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.Role OverviewAstera Labs is seeking a Senior Principal Digital Design Engineer to drive the architecture and implementation of next-generation digital designs powering AI infrastructure connectivity. This is a high-impact technical leadership role where you'll define micro-architecture strategies for better power, performance and area tradeoff, own complex chip-level design decisions, and guide multiple blocks from concept through silicon bring-up for industry-leading products supporting PCIe Gen 6/7, CXL, UALink, UCI, Ethernet, and DDR4/DDR5 protocols. As a senior technical leader, you'll shape design methodologies, mentor engineering teams, and collaborate cross-functionally with verification, physical design, DFT, and post-silicon teams to deliver high-performance, production-quality silicon. You'll also influence roadmap decisions and drive design excellence across the organization, ensuring Astera Labs continues to set the standard for AI connectivity solutions. Key Responsibilities Architecture Technical Leadership Define and drive micro-architecture for complex digital blocks and subsystems across multiple product lines Establish architectural standards and best practices that scale across the design organization Provide technical guidance and decision-making on critical design trade-offs impacting performance, power, and area Design Execution Ownership Lead RTL implementation of complex designs from architecture definition through GDS and silicon bring-up Drive timing constraints and closure strategies and implement robust Design-for-Test (DFT) methodologies Own accountability for design quality, schedule, and successful production delivery Cross-Functional Collaboration Partner with verification teams to develop comprehensive test plans, achieve coverage closure, and debug complex issues Collaborate with physical design, DFT, and post-silicon teams to ensure seamless integration and bring-up Work with firmware and software teams to optimize hardware-software interfaces Mentorship Process Excellence Mentor and develop junior and senior engineers, elevating team technical capabilities Drive continuous improvement of silicon development processes, CAD automation, and design infrastructure Contribute to organizational knowledge sharing and technical reviews Basic Qualifications Bachelor's degree in Electrical Engineering or equivalent 12+ years of hands-on experience developing complex SoC/silicon products in Server, Storage, and/or Networking markets Demonstrated expertise in architecture definition, micro-architecture development, RTL coding, synthesis, and timing closure Deep knowledge of at least one high-speed protocol: PCIe, CXL, Ethernet, DDR, or similar Production experience with advanced CMOS nodes (≤7nm) Proficiency with Cadence and/or Synopsys digital design flows Track record of delivering multiple high-performance designs to production Preferred Qualifications Master's degree in Electrical Engineering or related field Experience with multiple high-speed protocols (PCIe Gen 5/6, CXL, UALink, Ethernet, DDR4/DDR5) Hands-on collaboration with embedded firmware teams and familiarity with RISC-V or Arm subsystems Proven contributions to design methodology, CAD automation, or infrastructure improvements Experience leading technical teams or driving cross-functional initiatives in data center environments Salary range is $205,000 to $255,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.Are you passionate about creating differentiated products and working with hyperscale and AI platform providers to deploy the next generation of data center infrastructure?  We are seeking a highly technical and experienced product manager to join our team at Astera Labs. As a key member of our product management team, you will work closely with customers, product marketing, engineering and other internal cross-functional teams to define and deliver competitive silicon, hardware and software solutions. This is a unique opportunity to play a pivotal role in the success of our Taurus Ethernet Retimer portfolio. We are scaling our Taurus product management team to support our worldwide customers, offering ample opportunities for growth and advancement within the product team. Based in San Jose, this position requires an in-person presence with travel to customers.  Key Responsibilities  Own product definition: Define detailed product requirements and prioritize features, enhancements, and bug fixes based on business goals and customer feedback.  Lead product planning:Work closely with product marketing to translate product strategy into executable product plans and collaborate with Astera Labs cross-functional teams to drive products from ideation to launch.  Lead customer technical engagement:Work closely with lighthouse customers to translate their needs to competitive product requirements and secure new design wins throughout the product lifecycle.  Support go-to-market:Leverage technical and product expertise to support product marketing and corporate marketing teams on go-to-market planning and execution, sales enablement, competitive analysis, and product positioning.  Qualifications  Deep understanding of high-speed protocols (Ethernet is required; UAL, PCIe, CXL, and other protocols are a plus) and system architectures used in cloud and AI infrastructure  10+ years of experience in product management, applications engineering or other technical product roles within the semiconductor industry Proven track record of defining and launching successful semiconductor products Strong strategic thinking and analytical skills, with the ability to translate customer pain points into competitive products  Excellent communication skills with the ability to articulate complex technical concepts in a clear and compelling manner  Proven ability to collaborate effectively with cross-functional teams and drive consensus in a fast-paced, dynamic environment  Experience working with customers and partners to understand their needs and drive product definition  Willingness to travel as needed for customer meetings, industry events, and trade shows  We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.Overview Astera Labs is seeking Firmware Engineers across multiple seniority levels to architect, develop, and deliver core firmware for our next-generation connectivity, chiplet, and system products. This is a catch-all requisition designed to hire exceptional firmware talent aligned to one or more critical technical domains across PCIe/CXL, Ethernet, UALink, UCIe/Chiplet, and Device Driver development. Firmware is a core differentiator for Astera Labs’ products and is treated as a first-class engineering discipline, on par with hardware and silicon design. Engineers in this role will work closely with Architecture, RTL, Physical Design, Validation, and Systems teams, and may be customer-facing to support integration, debug, and deployment in hyperscale and data-center environments. We are hiring Individual Contributors (Senior up to Senior Principal). This role is required onsite in San Jose, CA. Key Responsibilities (scope scales by level) Architect, develop, and maintain bare-metal and low-level firmware running on embedded microcontrollers within Astera Labs SoCs and systems. Design and implement device drivers, core firmware services, and hardware abstraction layers for high-speed connectivity products. Define and implement HW-SW interfaces in close collaboration with RTL, PD, and Architecture teams. Lead bring-up, debug, and validation of firmware on silicon and system platforms. Develop and maintain C/C++ firmware codebases, SDKs, and supporting infrastructure. Build automation, tooling, and diagnostics using Python and scripting frameworks. Participate in system-level debug involving PCIe, Ethernet, memory subsystems, and interconnect fabrics. Support customer enablement, integration, and escalations as needed. Basic Qualifications Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related field (Master’s preferred). Strong fundamentals in embedded systems, computer architecture, and low-level software. Proven experience developing firmware for complex SoC or silicon-based products in Server, Storage, Networking, or Accelerator environments. Proficiency in C (required); C++ experience is a plus. Ability to work cross-functionally in a fast-paced, highly technical environment. Required Experience Bare-metal or RTOS-based firmware development (e.g., ThreadX, MQX, or equivalent). Firmware development for on-chip microcontrollers and supporting SDKs. Strong debugging skills across hardware, firmware, and system layers. Familiarity with firmware build systems and tooling (gcc, Make, Git, Doxygen). Python scripting for automation, validation, or tooling. Hands-on experience with server, storage, or networking systems. Preferred Experience / Nice to Have Firmware development for PCIe or Ethernet switch products. Exposure to BMCs, OpenBMC, or system management firmware. Experience with high-speed interfaces such as: PCIe (Gen3+) Ethernet (100G / 400G+) DDR, NVMe, USB, Infiniband Participation in industry forums or ecosystems (e.g., OCP, OpenBMC). Customer-facing or field-enablement experience. The base salary range is $135,000–$255,000 USD for Senior through Senior Principal roles. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.Role Overview Astera Labs is seeking a Staff Design Verification Engineer with a talent for breaking code and developing creative verification approaches for complex AI connectivity ASICs. Using your expertise in SystemVerilog, UVM, and problem-solving skills, you'll contribute to the functional verification of cutting-edge designs supporting PCIe Gen 6/7, CXL, UALink, UCI, Ethernet, and DDR4/DDR5 protocols. You'll be responsible for the full verification lifecycle—from planning to test development to debugging and coverage closure—while collaborating with RTL designers and system validation teams. This is an exciting opportunity to grow your career at a hypergrowth company defining the future of AI infrastructure connectivity. Key Responsibilities Verification Execution Execute full verification lifecycle using SystemVerilog/UVM methodologies, from test planning through coverage closure Develop test sequences and constrained-random stimulus to exercise design functionality and corner cases Identify and implement coverage measures to ensure comprehensive verification and high-quality tape-out Debug Collaboration Debug failures collaboratively with RTL designers, driving issues to root cause resolution Deploy hybrid verification techniques combining directed and constrained-random approaches Work with software and system validation teams to develop and execute test plans on emulation platforms Infrastructure Process Contribute to verification infrastructure improvements and automation using scripting tools Support regression infrastructure and coverage analysis workflows Document test plans, coverage strategies, and verification results Basic Qualifications Bachelor's degree in Electrical Engineering; Master's preferred 5+ years of experience verifying and validating complex SoCs for Server, Storage, and/or Networking applications Strong proficiency with SystemVerilog/UVM-based verification methodologies Experience developing test plans, test sequences, and coverage closure strategies Knowledge of industry-standard simulators, revision control systems, and regression systems Ability to work independently and collaboratively with cross-functional teams Preferred Qualifications Master's degree in Electrical Engineering or related field Experience with Verification IPs for protocols such as PCIe, CXL, Ethernet, DDR4/5, or similar Exposure to formal verification methods Working experience with scripting tools (Python/Perl) to automate verification infrastructure Experience with directed test methodologies or cache verification Base salary range is $160,000 to $195,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.As an Astera Labs Senior/Staff Physical Design Engineer you will play a crucial role in overseeing the planning, coordination, and execution supporting the design of Astera Labs' portfolio of connectivity ASICs used in the world's leading cloud service providers, server and network OEMs. To accomplish that, you will work closely with designers, verification engineering, and engineering operations. This role is fully on-site and in-person. Basic Qualifications: Strong academic and technical background in electrical engineering. A Bachelor’s degree in EE / Computer is required, and a Master’s degree is preferred. ≥3 years’ experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications. Professional attitude with the ability to prioritize a dynamic list of multiple tasks, plan and prepare for customer meetings in advance, and work with minimal guidance and supervision. Entrepreneurial, open-mind behavior and can-do attitude. Think and act fast with the customer in mind! Required Experience: Hands-on and thorough knowledge of synthesis, place and route, timing, extraction, EM-IR, formal verification (equivalence) and other backend tools and methodologies for technologies 7nm or less. Block level ownership from architecture to GDSII, driving multiple complex designs to production. Experience with Cadence and/or Synopsys physical design tools/flows. Familiarity and working knowledge of System Verilog/Verilog. Proven expertise in developing/maintaining timing constraints, timing signoff methodology, timing closure at the block or full-chip level. Experience in working with IP vendors for both RTL and hard-macro blocks. Good scripting skills in tcl, python or Perl. Preferred Experience: Knowledge of design for test (DFT) Familiarity with ECO methodologies and tools. Knowledge of LVS/DRC closures. Your base salary will be determined based on your experience and the pay of employees in similar positions. The base salary range is $135,000 USD - $165,000 USD for Senior Level, and $160,000 USD - $195,000 USD for Staff Level. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.