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Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.Job Overview As a Firmware Engineering Director/ Manager, you will lead and scale firmware development efforts for Astera Labs’ SoC and systems products used in data-center and AI infrastructure. You will be responsible for technical direction, people leadership, and execution across core firmware, bare-metal software, and device driver development. Firmware is a first-class differentiator at Astera Labs. In this role, you will build, mentor, and guide high-performing firmware teams while partnering closely with hardware, silicon architecture, validation, product, and customers to ensure successful delivery of complex firmware programs. This role supports two leadership levels: Firmware Engineering Manager Firmware Engineering Director Key Responsibilities Own the firmware execution strategy across one or more SoC or systems programs, ensuring alignment with product and silicon roadmaps. Lead and manage firmware teams responsible for bare-metal firmware, RTOS-based firmware, and device drivers. Provide technical oversight and architectural guidance without being the primary implementer. Partner closely with hardware architecture, RTL design, validation, and systems teams to define HW/SW interfaces, development milestones, and integration plans. Drive SoC bring-up readiness, firmware validation strategy, and risk mitigation across pre-silicon and post-silicon phases. Establish development processes, coding standards, and quality metrics to ensure predictable and scalable execution. Support customer engagements as needed, including escalation handling, technical reviews, and roadmap alignment. Communicate status, risks, and tradeoffs clearly to executive leadership and cross-functional stakeholders. Director scope: own multi-team delivery, long-term roadmap planning, hiring strategy, and cross-org alignment across multiple product lines. Firmware Domains Under Management Teams under this role may span one or more of the following areas: PCIe Firmware: PCIe switch and controller firmware (Gen3+), including link training, enumeration, error handling, and performance optimization. Ethernet Firmware: Embedded firmware for high-speed Ethernet systems (100G–400G+), including PHY/MAC interaction and link bring-up. UCIe / Chiplet Firmware: Firmware for chiplet-based SoC architectures, including die-to-die interconnect initialization and advanced packaging enablement. Required Experience Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or Computer Science. 10+ years of experience developing or supporting firmware for SoC, silicon, or systems products in compute, networking, or storage domains. 5+ years of experience in a people-management role, leading firmware or low-level software teams. Strong understanding of bare-metal firmware, RTOS environments, and firmware development lifecycles. Experience managing teams working on complex SoCs and high-speed interfaces such as PCIe, Ethernet, DDR, NVMe, or similar. Proven ability to lead execution across ambiguous, fast-moving environments with multiple stakeholders. Strong communication skills, executive presence, and customer-facing professionalism. Authorization to work in the U.S. Preferred Experience Prior experience managing firmware teams delivering PCIe or Ethernet switch products. Experience with UCIe, chiplet architectures, or advanced packaging ecosystems. Track record of scaling teams through hiring, onboarding, and mentorship. Experience working with or supporting customers during bring-up, deployment, or escalations. Participation in industry ecosystems such as OCP or OpenBMC. Director level: experience owning multi-program delivery, long-term technical roadmaps, and cross-functional organizational planning. This position can be hired as aSenior Manager Level or Director Level.The base salary range is $230,000 USD – $265,000 USD. Your base salary will be determined based on location, experience, and employees' pay in similar positions. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com. Role Overview Astera Labs is seeking a Director of Product Engineering to lead our product engineering organization in San Jose, CA. This is a critical leadership role responsible for driving next-generation high-speed, high-performance, and low-power semiconductor products from silicon bring-up through high-volume manufacturing in advanced process nodes. As the AI infrastructure market accelerates at an unprecedented pace, Astera Labs needs a seasoned leader who can build and scale a world-class product engineering team while maintaining the technical depth to solve the hardest problems in high-speed connectivity. You will own the complete post-silicon product development lifecycle — from characterization and qualification through production ramp and sustaining — across our portfolio of purpose-built connectivity solutions enabling rack-scale AI. This role demands a unique combination of hands-on technical expertise in high-speed signaling and ATE test fundamentals, coupled with the organizational leadership to build teams, establish best-known methods, and deliver products to production with uncompromising quality. You'll partner closely with design, validation, operations, and customers to ensure Astera Labs' products set the industry standard for performance and reliability. Key Responsibilities Team Leadership Organization Building Build, mentor, and lead a high-performing team of product engineers owning a diverse portfolio of connectivity products purpose-built for AI infrastructure Define team strategy, priorities, and execution roadmaps aligned with Astera Labs' aggressive product delivery timelines Establish scalable processes, best-known methods (BKMs), and operational excellence frameworks as the organization grows Make sound technical and organizational decisions in a fast-paced, dynamic environment with competing priorities ATE Test Development Production Excellence Drive ATE test program development and optimization for wafer sort and final test solutions on the Advantest 93K platform Own device ATE test yields, test time reduction, and quality metrics with a detailed, data-driven mindset Establish consistent BKMs for rolling out new ATE test programs across product families Lead data analysis efforts using tools such as JMP or Spotfire to calculate limits, identify outliers, and drive continuous improvement Product Qualification Manufacturing Define and execute standards-based qualification programs at both product and package level Partner with OSATs to support high-volume manufacturing through the complete product lifecycle Ensure seamless production ramp and sustaining operations, delivering quality parts to Astera Labs' hyperscaler and enterprise customers Drive system-level debug involving test hardware, test programs, and DUT interactions across digital and analog domains Cross-Functional Technical Leadership Provide technical leadership in high-speed signaling including NRZ/PAM4 SerDes protocols (PCIe Gen 3+, Ethernet 25G+), and memory interfaces such as (LP)DDR5/4 Partner with silicon design teams to feed back production learnings and drive DFT/DFM improvements Collaborate with silicon validation teams to ensure device performance meets production requirements Engage with customers and field teams on quality, reliability, and production-related technical matters Basic Qualifications Bachelor's degree in Electrical Engineering or Computer Engineering 8+ years of experience in post-silicon product development dealing with high-speed signals (product, test, or validation) 5+ years of managerial experience building and leading product engineering teams Hands-on experience with the Advantest 93K ATE platform including test program development for wafer sort and final test Strong technical foundation in high-speed SerDes protocols (PCIe, Ethernet, CXL) and/or memory interfaces (DDR5/LPDDR5) Experience defining and executing standards-based qualification at product and package level Demonstrated track record delivering semiconductor products to high-volume production with quality Strong data analysis skills and experience with statistical tools (JMP, Spotfire, or equivalent) Digital and analog circuit-level understanding for DUT characterization and debug Preferred Qualifications Master's degree in Electrical Engineering or Computer Engineering Experience working with silicon validation teams to correlate device performance with production requirements Firmware development experience in C/C++, scripting in Python, or equivalent programming skills Experience with advanced process nodes (5nm and below) Proven success partnering with OSATs in a fabless semiconductor operating model Prior experience in a high-growth company shipping products to hyperscaler customers The salary range for this position is $187,200 to $260,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.Role Overview Astera Labs is seeking a Manager, Package Design Engineering to lead and scale our Package Design team in San Jose. In this high-impact role, you'll own the end-to-end delivery of advanced IC packaging solutions—from early architecture definition through production ramp—enabling the next generation of AI infrastructure and connectivity products. As the semiconductor industry races toward chiplet-based architectures, 2.5D/3D integration, and ever-increasing bandwidth demands, packaging has become a critical differentiator. You'll build and mentor a high-performing team while driving cross-functional execution with silicon architecture, SIPI, PCB, validation, manufacturing, and external partners including substrate vendors and OSATs. Your work will directly impact Astera Labs' ability to deliver industry-leading PCIe, CXL, and Ethernet connectivity solutions to the world's most demanding hyperscale and AI customers. This role offers the opportunity to shape design methodology, establish scalable standards, and enable chip-package-board co-design frameworks across multiple product lines in a fast-moving, innovation-driven environment. Key Responsibilities Team Leadership Execution Build, mentor, and scale a high-performing package design engineering team with clear ownership, accountability, and execution flows Establish design templates, standards, and best-known methods (BKMs) across multiple concurrent programs Lead design reviews, audits, and issue resolution through bring-up and production ramp Package Design Delivery Own end-to-end package design execution including FCBGA/FCCSP, monolithic, multi-die, and chiplet-based designs from concept feasibility through tape-out and production Define and review substrate stack-ups, pad stacks, routing strategies, and design constraints to meet electrical, thermal, mechanical, and manufacturability requirements Drive technical tradeoffs across performance, cost, yield, and schedule, ensuring high-quality design closure and on-time delivery Cross-Functional Collaboration Partner with SIPI, silicon architecture, system/board design, and product teams to drive chip-package-board co-design and resolve system-level challenges Collaborate with OSATs and substrate vendors to ensure design feasibility, manufacturability, and alignment with evolving design rules and technology roadmaps Support adoption of advanced packaging technologies such as 2.5D, chiplet, CPO/CPC, and heterogeneous integration platforms Methodology Automation Develop and scale design methodologies and automation flows to improve efficiency, quality, and repeatability across the organization Basic Qualifications Bachelor's degree in Electrical Engineering, Materials Science, or related field 10+ years of progressive experience in IC package design using tools such as Cadence Allegro APD/SiP 5+ years of leadership experience managing teams or technical organizations in IC packaging environments Strong hands-on expertise in end-to-end package design with proven delivery of HVM-ready FCBGA/FCCSP packages using Cadence APD tool Experience with high-speed SerDes systems (PCIe Gen5/6/7, CXL, Ethernet 100G/200G/400G+) and advanced nodes (7nm, 5nm, 3nm) Deep understanding of substrate technologies, stack-ups, routing constraints, assembly processes, and SI/PI fundamentals Proven experience working with OSATs and substrate vendors through development and production ramp Experience working with OSATs and substrate vendors through development and production ramp Experience with advanced packaging architectures such as 2.5D/3D, chiplet, or heterogeneous integration Preferred Qualifications Master's degree in Electrical Engineering or related field Experience with advanced packaging architectures such as 2.5D/3D, chiplet, or heterogeneous integration Experience implementing automation, scripting (Python, SKILL, Tcl), or workflow optimization Background in early package feasibility, platform evaluation, and technology roadmap development Familiarity with chip floor planning, architecture, and system-level tradeoffs Exposure to SIPI modeling and analysis, thermal, and mechanical performance considerations The base salary range is $230,000 USD – $265,000 USD. This position can be hired as a Manager Level or Director Level. Your base salary will be determined based on location, experience, and employees' pay in similar positions.We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com. Role Overview Astera Labs is looking for a Senior Principal Engineering Program Manager to lead end-to-end execution of advanced-node ASIC products from concept through production. This is a high-visibility role with direct accountability for delivering revenue-critical silicon on time, on spec, and at scale. Key Responsibilities Program Ownership Execution Own full ASIC lifecycle execution: architecture, RTL, verification, physical design, tapeout, validation, customer sampling, qualification, and RTM Serve as the single point of ownership for assigned ASIC programs Drive program planning, schedules, budgets, resources, and risk management Cross-Functional Leadership Issue Resolution Lead cross-functional teams across design, validation, product, test, firmware, software, and operations Resolve complex pre-silicon and post-silicon issues through strong technical judgment Stakeholder Management Alignment Manage scope, schedule, and cost trade-offs and communicate clearly with executives and stakeholders Champion program execution while aligning engineering delivery with business and customer goals Basic Qualifications BS or MS in Electrical, Electronics, or Computer Engineering 10+ years of ASIC product development experience in a semiconductor environment Strong understanding of ASIC development flows, with hands-on experience in RTL, DSP, or Physical Design Experience delivering ASICs in advanced nodes (10nm) Proven ability to lead in a matrixed, high-pressure environment Strong program management skills; familiarity with MS Project, Jira, Atlassian tools, Scrum/WBS Preferred Qualifications 5 or more years of experience as an ASIC Program Manager Experience with PCIe, memory, or high-speed data communication ASICs Salary range is $205,000 to $250,000 depending on experience, level, and business need. This role is eligible for discretionary bonus, incentives and benefits. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.Role Overview Astera Labs is seeking aSenior HR Business Partnerto join our People team in San Jose, CA. In this high-impact role, you will partner directly with engineering organizations—serving as a trusted advisor, coach, and strategic partner to engineering leaders, managers, and employees across our technical teams. You will bring deep HRBP/Generalist experience, strong employee relations expertise, and substantial knowledge of US labor and employment law to ensure our people practices are both effective and compliant as we scale. This role is critical to supporting the talent strategies, people leader development, and organizational health that enable our engineering teams to deliver world-class AI infrastructure connectivity products. Key Responsibilities 1. Engineering Partnership Coaching Serve as a trusted partner to engineeringpeople leaders, providing hands-on coaching on people management, team dynamics, and leadership effectiveness Build strong relationships across all levelsensuring employees and managers have accessible, credible HR support Coach engineering managers on performance conversations, career development discussions, feedback delivery, and navigating difficult team situations Help translate the unique challenges of semiconductor product development into practical people strategies 2. Employee Relations Compliance Serve as the primary point of contact for employee relations matters across supported engineering groups, handling investigations, performance issues, interpersonal conflict, and conduct concerns with professionalism and care Apply strong knowledge ofNorth Americalabor and employment law—including federal, state, and local regulations—to advise leaders and ensure compliant, defensible people decisions Conduct thorough, fair, and well-documented workplace investigations, partnering with Employment Counsel and Legal on complex or high-risk matters Proactivelyidentifycompliance risks and partner with HR Operations to ensure policies, practices, and manager actions align with legal requirements Stay current on evolving employment legislation and regulatory changes, advising leaders on implications and necessary adjustments Provide clear, empathetic, and legally sound guidance to managers navigating terminations, leaves of absence, accommodations, and other sensitive situations 3. Talent Strategy Organizational Effectiveness Partner with engineering leaders on organizational design, role clarity, and team structure to support product roadmap execution Lead talent reviews, retention planning, and succession planning for critical technical roles Support headcount planning and workforce decisions, balancing near-term delivery needs with long-term capability building Identifytalent risks and hotspots early, working proactively with leaders to address retention and engagement challenges 4. Performance Management Guide leaders and managers through performance cycles, calibration sessions, and compensation reviews with fair, consistent, and well-reasoned recommendations Ensure performance management practices are applied consistently and in compliance with company policy and legal standards Partner with Compensation and HR Operations to supportequitablepay decisions and address compensation-related concerns 5. Operational Excellence Scalability Identifygaps in people processes or manager capability and proactively propose solutions Partner with HR Ops and Centers of Excellence to simplify, standardize, and scale HR practices as the engineering organization grows Operate with an owner's mindset—taking accountability for outcomes, not just recommendations Basic Qualifications Bachelor's degree in Human Resources, Business Administration, Organizational Development, or related field 8+ years of HR Business Partnerexperiencesupporting engineering or technical organizations Demonstrated experience insupporting engineering organizations Strong knowledge ofNorth Americaemploymentand labor law, including federal and California state regulations (wage and hour, leaves, accommodations, terminations, harassment/discrimination) Proventrack recordhandling complex employee relations matters, workplace investigations, and sensitive personnel issues Demonstrated ability to coach managers and build trusted relationships with technical employees at all levels Strong judgment and comfortoperatingin fast-paced, ambiguous environments Clear, confident communicator who can influence and advise engineering leaders effectively Preferred Qualifications PHR, SPHR, SHRM-CP, or SHRM-SCP certification Experience supporting organizations through rapid scaling or hypergrowth phases Background partnering with engineering teams Strong analytical skills with experience using people data to inform talent decisions Track recordof developing manager capability and building coaching cultures within engineering organizations Experience in AI, data center, or connectivity-focused technology companies Salary range is $133,200 to $185,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com. Senior Director, Optical Test Engineering Position Overview We are seeking an experienced Senior Director of Optical Test Engineering to lead the development, validation, and manufacturing support of advanced integrated optical interconnect solutions. This role focuses on optical-electrical integration at the module level, bridging transceiver and compute platform interfaces with comprehensive test strategy and execution. Key Responsibilities Strategic Leadership Define and execute the optical test engineering roadmap for next-generation interconnect architectures Establish testing methodologies and standards for tightly integrated optical-electrical assemblies Lead cross-functional teams across optical design, electrical engineering, manufacturing, and quality Develop partnerships with ecosystem partners on test protocols and validation requirements Technical Program Management Oversee test strategy development for optical modules with embedded or adjacently mounted optical components Drive creation of comprehensive test plans covering optical performance, electrical performance, thermal management, and reliability Establish acceptance criteria and performance benchmarks aligned with data center and enterprise requirements Manage test equipment specifications, procurement, and deployment across manufacturing sites Validation Reliability Champion accelerated life testing programs for integrated optical-electrical systems Develop diagnostic and characterization protocols for novel optical assembly approaches Lead root-cause analysis on field failures and manufacturing defects Ensure compliance with industry standards (IEEE, IEC, Telcordia) and customer specifications Engineering Team Development Build and mentor a team of optical test engineers, technicians, and process specialists Foster innovation in test methodology and automation Develop talent pipeline and career advancement opportunities Promote continuous learning in optical testing technologies and practices Manufacturing Support Collaborate with manufacturing operations on yield improvement and test efficiency Establish in-line test protocols and inline measurement strategies Support transition from development to production testing Drive test cost reduction through automation and optimization Required Qualifications Experience: 15+ years in optical engineering, with 5+ years in test engineering leadership Technical Expertise: Deep knowledge of optical transceiver design and testing Experience with optical-electrical integration challenges Proficiency in optical characterization (loss, dispersion, eye diagrams, jitter) Fluency with high-speed electrical measurements and signal integrity Leadership: Demonstrated success managing technical teams and cross-functional programs Industry Knowledge: Understanding of data center interconnect architectures and requirements Problem-Solving: Strong analytical and troubleshooting capabilities Preferred Qualifications Experience with 112G+ or 200G+ optical systems Familiarity with thermal management in high-density optical modules Knowledge of automated test equipment (ATE) programming and optimization Background in manufacturing process capability analysis Understanding of substrate technologies (silicon photonics, planar lightwave circuits) Advanced degree in Physics, Optical Engineering, Electrical Engineering, or related field Strategic vision and execution Technical depth and credibility Cross-functional collaboration Process improvement and lean manufacturing principles Data-driven decision making Communication with technical and executive audiences Change management Budget and resource management We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com. AVP of Hardware Engineering Operations/Manufacturing Role Overview Astera Labs is scaling rapidly as the connectivity backbone of rack-scale AI infrastructure, and our hardware manufacturing footprint is scaling with it. Smart Cable Modules (SCM), Active Electrical Cables (AEC), evaluation boards, AI Chassis-class systems, and ODM-built products are central to how we deliver purpose-built connectivity at hyperscale. We're hiring an AVP of Hardware Engineering Operations/Manufacturing to bring focused, senior leadership to this growing function. This is a wide-ranging role spanning the full breadth of Astera Labs' hardware portfolio — from Smart Cable Modules to rack-scale chassis-based products. You'll own manufacturing strategy and execution across SCM, AEC, evaluation boards (SVB/EVB), AI Chassis-class systems, and ODM-built products such as switch trays and CEM cards. You'll be the primary leader partnering with our contract manufacturers across China and the rest of Asia, driving quality, capacity, cost, and time-to-market as we scale to meet AI infrastructure demand. Key Responsibilities Leadership, Strategy CM/ODM Partnership Lead Astera Labs' hardware engineering operations and manufacturing organization across SCM, AEC, evaluation boards, AI Chassis-class systems, and ODM programs Own day-to-day partnership with contract manufacturers across China and the rest of Asia — driving cadence, accountability, and site ramps from qualification through full production maturity Manage ODM engagements for switch trays, CEM cards, chassis-based systems, and adjacent products, navigating the differences from traditional CM models Partner with Hardware Engineering, Product, Supply Chain, and Quality leaders, and represent hardware operations in executive reviews New Product Introduction (NPI) Advanced Manufacturing Drive Design for Manufacturability (DFM) reviews on early product designs to validate completeness and manufacturability before release to the floor Lead production scaling — estimating costs, production times, and staffing requirements for new designs Prepare and maintain technical documentation for new manufacturing processes and engineering procedures Process Sustaining Engineering Design factory layouts and analyze workflows to achieve maximum production efficiency Troubleshoot operational bottlenecks and investigate material use variances directly on the assembly line Conduct ongoing time and cost analyses to identify waste reduction and lean manufacturing improvements Test Engineering Architect test parameters for finished products to validate they meet exact process requirements Coordinate the design, procurement, build, and debug of automated test equipment Test products to identify anomalies and ensure compliance with functional and safety standards Product Engineering (Manufacturing Focus) Lead failure analysis using statistical methods and recommend changes in designs, tolerances, or processing methods Apply root-cause fixes to prevent reoccurrence of product problems involving existing designs or materials Monitor and analyze operational data to evaluate product performance and drive technical design changes that improve yield Tooling Automation Assess, select, and schedule installation of manufacturing machinery and industrial processing systems Design and implement custom jigs, fixtures, and manufacturing aids for daily assembly Apply automation techniques and robotics programming to improve workflow and reduce manual labor Basic Qualifications Bachelor's degree in Electrical Engineering or related technical discipline 15+ years of hardware manufacturing experience, with significant time leading cable assembly, PCBA, board, module, or system/chassis manufacturing Proven track record managing contract manufacturers in Asia, including site ramps and multi-site operations Deep expertise in NPI, DFM, mass production ramp, yield/test, and quality systems for high-volume hardware products Hands-on experience across process/sustaining engineering, test engineering, and tooling/automation Experience leading and scaling hardware operations organizations through hyper-growth Willingness and ability to travel internationally to CM and ODM sites on a regular cadence Preferred Qualifications Master's degree in Electrical Engineering or related field Direct experience with Active Electrical Cables (AEC), optical transceivers, Smart Cable Modules, or high-speed cable/connector assemblies Experience manufacturing rack-scale or chassis-class systems for hyperscale or AI infrastructure Experience with ODM engagement models for system-level products (switch trays, CEM cards, or similar) Chinese language proficiency (Mandarin) for direct CM partnership in China We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.Role SummaryWe are seeking a technically strong Chief of Staff to the Head of Engineering who will also lead Engineering Program Management across Silicon Engineering. This role is a force-multiplier for Engineering leadership — driving org scale, decision velocity, and execution rigor. The ideal candidate brings deep technical fluency, structured problem-solving, and the ability to drive outcomes through influence rather than hierarchy. The role is fully in person in San Jose. Responsibilities — What You Will Own 1) Chief of Staff to Head of Engineering • Drive operational cadence: engineering all hands, staff meetings, agenda/material prep, tech talks, university engagements, action follow-through, and leadership syncs.• Frame and resolve high-leverage decisions — proactively surface blockers (technical, operational, organizational) before they escalate.• Manage escalations and organizational friction — diagnose root causes, coordinate resolution paths, and ensure durable fixes.• Partner cross-functionally with Hardware, Product, and Quality teams to ensure clarity of communication, alignment on priorities, and disciplined follow-through on decisions.• Support org design, headcount planning, and hiring prioritization for engineering teams.• Maintain alignment across functions through clear messaging and communication, validate exitance and validation of processes• Navigate org dynamics, build trust, and constructively challenge assumptions; maintain psychological safety.• Support the head of engineering with administrative and org related activities 2) Lead ASIC Tape out Management (Silicon Programs) • Status management — collect and track status across functions contributing to ASIC tapeouts.• Milestone tracking — maintain methodology checklists and boundary agreements to ensure schedule adherence.• IP and vendor tracking — own visibility into IP deliveries, version inventory, vendor issues, and escalation loops.• Quality documentation — monitor quality KPIs, ensure engineering documentation completeness.• Requirements tracking — ensure PRDs/features are captured, tracked, baselined.• Resource monitoring — track compute, hardware, storage consumption and thresholds.• Internal reporting — generate status reporting for Silicon Engineering leadership. 3) Influence Without Authority • Drive cross-engineering outcomes through credibility, clarity, and follow-through — not hierarchy.• Create order in ambiguous spaces; shape scope where it is undefined. Qualifications • 10+ years in semiconductor/SoC/ASIC or adjacent high-complexity engineering environment (e.g., CPU/IP/System companies).• Proven success in Chief of Staff, Staff Program Manager, TPM Director, or similar technical leadership-enablement role. • Strong technical acumen — able to understand engineering trade-offs and make decisions with limited information, challenge assumptions, and earn credibility with senior ICs.• Demonstrated experience running program cadence for complex silicon programs (tapeout, IP integration, etc.).• Proven ability to organize complex workflows and drive consistent follow-through.• High EQ and organizational awareness; can navigate tension and align diverse viewpoints.• Exceptional written/verbal communication, structured thinking, and execution discipline.• Prior experience in leading RTL2GDSII chip design is a huge plus. What Success Looks Like • Engineering leadership spends more time on strategic and technical decisions, less on coordination.• Milestones hit with fewer escalations and clearer accountability.• Status, risks, and decisions are crisp — never ad hoc or late.• Teams feel supported, not policed — trust increases, friction decreases without compromising on accountability .• Ambiguity decreases over time as clarity and execution rhythm scale with the org. Salary range is $216,000 to $300,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com. Role Overview Astera Labs' Taurus product line includes Ethernet retimers and gearboxes deployed in active electrical cables and in-system applications at the heart of AI infrastructure. As AI clusters scale to tens of thousands of GPUs connected by high-speed Ethernet fabrics, the firmware running on these connectivity devices is mission-critical — and so is the ability to debug it fast when something breaks. We're looking for a Firmware Engineer who can bridge our system validation team and firmware development organization. When something goes wrong in the lab or in the field, you won't be waiting on others to dig into the firmware. You'll be the person in the room who understands both sides — can pull up the code, identify the problem, and fix it. If you've worked at a networking company, know how Ethernet actually works from the MAC down through the PHY, have debugged real link failures, and have written or modified firmware or low-level drivers, this role was designed for you. Your primary focus will be debug and system integration. You will be an integral part of the firmware team and work on new feature development, but you will be the point person in the lab helping to unblock other teams — triaging failures, understanding what the firmware is doing, and making targeted fixes without requiring a long handoff loop. Beyond that, you'll contribute to feature development and help bring new products from initial bringup into customer deployment. Key Responsibilities Debug System Integration Work directly with the system validation team to debug firmware behavior across different Ethernet configurations, link states, and failure modes Investigate and fix firmware issues in embedded C, leveraging deep understanding of how Layer 1 PHY, SERDES, FEC/PCS, MAC, and retimer components interact Serve as the connective tissue between firmware and system validation teams, triaging issues and driving them to resolution without long handoff loops Customer Bring-Up Field Support Support customer bring-up and integration activities, including triaging field issues and coordinating fixes with internal teams Partner with field applications engineers to diagnose and resolve deployment issues quickly Firmware Feature Development Contribute to firmware feature development for SERDES configuration, link training, equalization, and diagnostics Partner with SoC, field applications, and platform teams across the full product lifecycle Help bring new Taurus products from initial silicon bringup through customer deployment Basic Qualifications Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field 5+ years of experience in firmware development or embedded systems engineering Hands-on experience with Ethernet at the system or device level: Layer 1 PHY, SERDES, retimers, gearboxes, NICs, switches, or related devices Solid embedded C/C++ skills and comfort working in a firmware codebase on real hardware Ability to debug across the hardware/software boundary: register accesses, embedded SDKs, link state machines, PHY telemetry, debug print logs Familiarity with Linux development tools: gcc/clang, make, bash, gdb, git Strong communication skills and comfort working in a fast-moving environment where the problem in front of you may not have a clean solution Preferred Qualifications Experience with switch or NIC management software, SAI, or OpenBMC Knowledge of PMA, FEC, or other PHY-layer subsystems beyond the SERDES Background with retimer or gearbox firmware or SDK/API development Python scripting for debug, test automation, or data analysis Experience with lab equipment: BERT, oscilloscopes, Viavi/Lecroy/Exfo/Keysight/Tektronix or similar Understanding of signal integrity: equalization, jitter, eye diagrams, link margin Prior experience mentoring engineers or leading debug efforts across teams Salary range is $133,200 to $185,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.Astera Labs is seeking an exceptional Senior Director System Validation to lead our AI Fabric Validation organization. Connectivity is a critical component of every AI accelerator deployment and hyperscale data center architecture. As part of the AI Fabric Engineering group, you will play a key role in ensuring that Astera Labs’ fabric solutions perform at scale and deliver system-level performance across the most demanding AI and ML workloads. This role offers a unique opportunity to shape validation strategy for cutting-edge connectivity silicon and gain deep insight into next-generation AI infrastructure platforms. Your primary responsibility will be to build and lead a world-class validation organization tasked with validating all silicon, firmware, and system-level solutions at scale, ensuring performance, reliability, and production readiness across customer deployments. Job Description Seeking a strong technical leader who has delivered multiple SoC products. Lead and scale the system validation organization for Astera Labs' AI fabric portfolio, building a high-performing team across multiple concurrent product programs. Understand the performance and functionality requirements of our AI fabric switches to enable customers to develop Data Center systems using Astera Labs' connectivity products for AI and ML applications. Own comprehensive validation strategies for AI fabric switch products. Drive execution through scalable automation platforms and data-centric testing with automated reporting and specification compliance verification. Collaborate cross-functionally with Architecture, Hardware, Firmware, and Software teams to influence product requirements and ensure validation excellence. Ensure timely bring‑up of new silicon and platforms, driving root‑cause analysis and cross‑functional debug of hardware, firmware, and system issues. Deliver high‑confidence validation results that support product qualification, customer sampling, and mass production readiness. Engage directly with key customers to understand their requirements and highlight the unique capabilities of Astera Labs' solutions. The ideal candidate brings deep expertise in silicon/system validation, a strong architectural mindset, and a proven ability to scale organizations in fast‑moving, high‑performance computing environments. Work closely with silicon design, architecture, Firmware, software engineering teams to ensure cohesive validation strategies. Drive a culture of technical excellence, accountability, and continuous improvement. Manage resource planning, and vendor/partner relationships. Basic Qualifications Strong academic background in Electrical or Computer Engineering. Bachelor's required, Master's preferred. ≥15 years' experience supporting or developing complex SoC/silicon products for Server, Storage, Networking applications and high‑performance hardware companies. ≥5 years hands-on experience with Silicon/System bring-up, validation, and debug, including in customer systems. ≥5 years building high performance Engineering teams and validation methodologies. Deep understanding of CPU, GPU, SoC, or AI/ML accelerator architectures, including memory subsystems, I/O, power management, and firmware interactions. Expertise in validation methodologies: pre‑silicon simulation/emulation, post‑silicon bring‑up, system validation, stress testing, and performance characterization. Strong background in debug methodologies, lab infrastructure, and automation frameworks. Excellent communication skills and ability to influence executives and cross‑functional partners. Entrepreneurial, open-minded behavior and can-do attitude. Think and act with the customer in mind! Preferred Experience ≥8 years leading validation teams planning, execution and maintaining project visibility. ≥10 years hands-on experience with Silicon/System bring-up, validation, and debug, including in customer systems. Thorough knowledge of high-speed protocols like PCIe, CXL, NVMe, or Ethernet. Deep understanding of High-Speed Signaling Principles and x86/ARM architecture, UEFI/Linux boot sequence. The base salary range is $240,000 USD - $300,000 USD. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.