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WorldQuant develops and deploys systematic financial strategies across a broad range of asset classes and global markets. We seek to produce high-quality predictive signals (alphas) through our proprietary research platform to employ financial strategies focused on market inefficiencies. Our teams work collaboratively to drive the production of alphas and financial strategies – the foundation of a balanced, global investment platform. WorldQuant is built on a culture that pairs academic sensibility with accountability for results. Employees are encouraged to think openly about problems, balancing intellectualism and practicality. Excellent ideas come from anyone, anywhere. Employees are encouraged to challenge conventional thinking and possess an attitude of continuous improvement. Our goal is to hire the best and the brightest. We value intellectual horsepower first and foremost, and people who demonstrate an outstanding talent. There is no roadmap to future success, so we need people who can help us build it.Technologists at WorldQuant research, design, code, test and deploy firmwide platforms and tooling while working collaboratively with researchers and portfolio managers. Our environment is relaxed yet intellectually driven. We seek people who think in code and are motivated by being around like-minded people. The Role: We are building a new software engineering team with strong applied AI orientation to amplify WorldQuant's success. The team is focusing on creating company-wide applications to address our colleagues’ every day problems. You will have a chance to work with a broad range of teams at WorldQuant, helping them to be more productive with custom solutions. Collaborate with cross-functional distributed teams. Gather, analyze and spec out requirements, and manage product deliverables. Design and build scalable AI-driven products addressing real-world problems. Stay current with the latest technical advancements, particularly in the field of AI and LLMs. What You’ll Bring: Strong programming skills, preferably in Python. Exceptional analytical skills and a passion for solving complex problems. Thorough understanding of how AI works and familiarity with language models. Understanding of vector databases and other relevant data structures. Working knowledge in various databases and messaging technologies is a strong plus. (SQL, Redis, Kafka etc.) Excellent communication skills in English. Mature, thoughtful attitude with the ability to operate in a collaborative, team-oriented culture. A strong delivery mind-set, drive to get things done. Experience in finance is not required. #LI-MH1 By submitting this application, you acknowledge and consent to terms of the WorldQuant Privacy Policy. The privacy policy offers an explanation of how and why your data will be collected, how it will be used and disclosed, how it will be retained and secured, and what legal rights are associated with that data (including the rights of access, correction, and deletion). The policy also describes legal and contractual limitations on these rights. The specific rights and obligations of individuals living and working in different areas may vary by jurisdiction. Copyright © 2025 WorldQuant, LLC. All Rights Reserved.WorldQuant is an equal opportunity employer and does not discriminate in hiring on the basis of race, color, creed, religion, sex, sexual orientation or preference, age, marital status, citizenship, national origin, disability, military status, genetic predisposition or carrier status, or any other protected characteristic as established by applicable law.

WorldQuant develops and deploys systematic financial strategies across a broad range of asset classes and global markets. We seek to produce high-quality predictive signals (alphas) through our proprietary research platform to employ financial strategies focused on market inefficiencies. Our teams work collaboratively to drive the production of alphas and financial strategies – the foundation of a balanced, global investment platform. WorldQuant is built on a culture that pairs academic sensibility with accountability for results. Employees are encouraged to think openly about problems, balancing intellectualism and practicality. Excellent ideas come from anyone, anywhere. Employees are encouraged to challenge conventional thinking and possess an attitude of continuous improvement. Our goal is to hire the best and the brightest. We value intellectual horsepower first and foremost, and people who demonstrate an outstanding talent. There is no roadmap to future success, so we need people who can help us build it.The Role: We are seeking a senior technology leader to manage a high performing team that handles our electronic execution. In collaboration with the team’s software architect we are looking for someone to: Retain, recruit, and develop a lean team of developers Drive cross team collaboration to ensure prioritization and execution Lead the adaptation of best-in-class engineering practices consistent with our technology organization’s philosophy Escalate and resolve intra- and cross-group misalignment as needed What You'll Bring: Previous experience as a software engineering manager leading experienced teams or technologyorganizations within the financial domain Ability to reduce complex concepts into understandable, actionable tasks Proven experience with delivering best in class technology platforms in C++, Java or Python Familiarity with and inspired by trends in modern computing and new technologies Degree in Computer Science and or related field and 10+ years’ experience leading strategy and delivering solutions for multiple industries and/or solution domains Ability to act as an evangelist who inspires internal audiences through clarity of message and setting of best practices Locations:Chicago, NYC, CT, or Austin Our Benefits: Core Benefits: Fully paid medical and dental insurance for employees and dependents, flexible spending account, 401k, fully paid parental leave, generous PTO (paid time off) that consists of: twenty vacation days that are pro-rated based on the employee’s start date, at an accrual of 1.67 days per month,three personal days, andten sick days. Perks: Employee discounts for gym memberships, wellness activities, healthy snacks, casual dress code Training: learning and development courses, speakers, team-building off-site Employee resource groups Pay Transparency: WorldQuant is a total compensation organization where you will be eligible for a base salary, discretionary performance bonus, and benefits. To provide greater transparency to candidates, we share base pay ranges for all US-based job postings regardless of state. We set standard base pay ranges for all roles based on job function and level, benchmarked against similar stage organizations. When finalizing an offer, we will take into consideration an individual’s experience level and the qualifications they bring to the role to formulate a competitive total compensation package. The Base Pay Range For This Position Is $150,000 – $250,000 USD. At WorldQuant, we are committed to providing candidates with all necessary information in compliance with pay transparency laws. If you believe any required details are missing from this job posting, please notify us at [email protected], and we will address your concerns promptly. By submitting this application, you acknowledge and consent to terms of theWorldQuant Privacy Policy.The privacy policy offers an explanation of how and why your data will be collected, how it will be used and disclosed, how it will be retained and secured, and what legal rights are associated with that data (including the rights of access, correction, and deletion). The policy also describes legal and contractual limitations on these rights. The specific rights and obligations of individuals living and working in different areas may vary by jurisdiction. #LI-RS1 By submitting this application, you acknowledge and consent to terms of the WorldQuant Privacy Policy. The privacy policy offers an explanation of how and why your data will be collected, how it will be used and disclosed, how it will be retained and secured, and what legal rights are associated with that data (including the rights of access, correction, and deletion). The policy also describes legal and contractual limitations on these rights. The specific rights and obligations of individuals living and working in different areas may vary by jurisdiction. Copyright © 2025 WorldQuant, LLC. All Rights Reserved.WorldQuant is an equal opportunity employer and does not discriminate in hiring on the basis of race, color, creed, religion, sex, sexual orientation or preference, age, marital status, citizenship, national origin, disability, military status, genetic predisposition or carrier status, or any other protected characteristic as established by applicable law.

WorldQuant develops and deploys systematic financial strategies across a broad range of asset classes and global markets. We seek to produce high-quality predictive signals (alphas) through our proprietary research platform to employ financial strategies focused on market inefficiencies. Our teams work collaboratively to drive the production of alphas and financial strategies – the foundation of a balanced, global investment platform. WorldQuant is built on a culture that pairs academic sensibility with accountability for results. Employees are encouraged to think openly about problems, balancing intellectualism and practicality. Excellent ideas come from anyone, anywhere. Employees are encouraged to challenge conventional thinking and possess an attitude of continuous improvement. Our goal is to hire the best and the brightest. We value intellectual horsepower first and foremost, and people who demonstrate an outstanding talent. There is no roadmap to future success, so we need people who can help us build it.Technologists at WorldQuant research, design, code, test and deploy projects while working collaboratively with researchers and portfolio managers. Our environment is relaxed yet intellectually driven. We seek people who think in code and are motivated by being around like-minded people. The Role: We are building a new software engineering team with strong applied AI orientation to seek to amplify WorldQuant's success. The team will be focusing on creating company-wide applications to address our colleagues’ every day problems. You will have a chance to work with a broad range of teams at WorldQuant, helping them to be more productive with custom solutions. Collaborate with cross-functional distributed teams. Gather, analyze and spec out requirements, and manage product deliverables. Design and build scalable AI-driven products addressing real-world problems. Stay current with the latest technical advancements, particularly in the field of AI and LLMs. What You’ll bring: Strong programming skills, preferably in Python. Exceptional analytical skills and a passion for solving complex problems. Thorough understanding of how AI works and familiarity with language models. Understanding of vector databases and other relevant data structures. Working knowledge in various databases and messaging technologies is a strong plus. (SQL, Redis, Kafka etc.) Excellent communication skills in English. Mature, thoughtful attitude with the ability to operate in a collaborative, team-oriented culture. A strong delivery mind-set, drive to get things done. Experience in finance is not required. Our Benefits: Core Benefits: Fully paid medical and dental insurance for employees and dependents, flexible spending account, 401k, fully paid parental leave, generous PTO (paid time off) that consists of: twenty vacation days that are pro-rated based on the employee’s start date, at an accrual of 1.67 days per month,three personal days, andten sick days. Perks: Employee discounts for gym memberships, wellness activities, healthy snacks, casual dress code Training: learning and development courses, speakers, team-building off-site Employee resource groups Pay Transparency: WorldQuant is a total compensation organization where you will be eligible for a base salary, discretionary performance bonus, and benefits. To provide greater transparency to candidates, we share base pay ranges for all US-based job postings regardless of state. We set standard base pay ranges for all roles based on job function and level, benchmarked against similar stage organizations. When finalizing an offer, we will take into consideration an individual’s experience level and the qualifications they bring to the role to formulate a competitive total compensation package. The Base Pay Range For This Position Is $125,000 – $200,000 USD. At WorldQuant, we are committed to providing candidates with all necessary information in compliance with pay transparency laws. If you believe any required details are missing from this job posting, please notify us at [email protected], and we will address your concerns promptly. By submitting this application, you acknowledge and consent to terms of theWorldQuant Privacy Policy.The privacy policy offers an explanation of how and why your data will be collected, how it will be used and disclosed, how it will be retained and secured, and what legal rights are associated with that data (including the rights of access, correction, and deletion). The policy also describes legal and contractual limitations on these rights. The specific rights and obligations of individuals living and working in different areas may vary by jurisdiction. #LI-RS1By submitting this application, you acknowledge and consent to terms of the WorldQuant Privacy Policy. The privacy policy offers an explanation of how and why your data will be collected, how it will be used and disclosed, how it will be retained and secured, and what legal rights are associated with that data (including the rights of access, correction, and deletion). The policy also describes legal and contractual limitations on these rights. The specific rights and obligations of individuals living and working in different areas may vary by jurisdiction. Copyright © 2025 WorldQuant, LLC. All Rights Reserved.WorldQuant is an equal opportunity employer and does not discriminate in hiring on the basis of race, color, creed, religion, sex, sexual orientation or preference, age, marital status, citizenship, national origin, disability, military status, genetic predisposition or carrier status, or any other protected characteristic as established by applicable law.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.Job Overview As a Firmware Engineering Director/ Manager, you will lead and scale firmware development efforts for Astera Labs’ SoC and systems products used in data-center and AI infrastructure. You will be responsible for technical direction, people leadership, and execution across core firmware, bare-metal software, and device driver development. Firmware is a first-class differentiator at Astera Labs. In this role, you will build, mentor, and guide high-performing firmware teams while partnering closely with hardware, silicon architecture, validation, product, and customers to ensure successful delivery of complex firmware programs. This role supports two leadership levels: Firmware Engineering Manager Firmware Engineering Director Key Responsibilities Own the firmware execution strategy across one or more SoC or systems programs, ensuring alignment with product and silicon roadmaps. Lead and manage firmware teams responsible for bare-metal firmware, RTOS-based firmware, and device drivers. Provide technical oversight and architectural guidance without being the primary implementer. Partner closely with hardware architecture, RTL design, validation, and systems teams to define HW/SW interfaces, development milestones, and integration plans. Drive SoC bring-up readiness, firmware validation strategy, and risk mitigation across pre-silicon and post-silicon phases. Establish development processes, coding standards, and quality metrics to ensure predictable and scalable execution. Support customer engagements as needed, including escalation handling, technical reviews, and roadmap alignment. Communicate status, risks, and tradeoffs clearly to executive leadership and cross-functional stakeholders. Director scope: own multi-team delivery, long-term roadmap planning, hiring strategy, and cross-org alignment across multiple product lines. Firmware Domains Under Management Teams under this role may span one or more of the following areas: PCIe Firmware: PCIe switch and controller firmware (Gen3+), including link training, enumeration, error handling, and performance optimization. Ethernet Firmware: Embedded firmware for high-speed Ethernet systems (100G–400G+), including PHY/MAC interaction and link bring-up. UCIe / Chiplet Firmware: Firmware for chiplet-based SoC architectures, including die-to-die interconnect initialization and advanced packaging enablement. Required Experience Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or Computer Science. 10+ years of experience developing or supporting firmware for SoC, silicon, or systems products in compute, networking, or storage domains. 5+ years of experience in a people-management role, leading firmware or low-level software teams. Strong understanding of bare-metal firmware, RTOS environments, and firmware development lifecycles. Experience managing teams working on complex SoCs and high-speed interfaces such as PCIe, Ethernet, DDR, NVMe, or similar. Proven ability to lead execution across ambiguous, fast-moving environments with multiple stakeholders. Strong communication skills, executive presence, and customer-facing professionalism. Authorization to work in the U.S. Preferred Experience Prior experience managing firmware teams delivering PCIe or Ethernet switch products. Experience with UCIe, chiplet architectures, or advanced packaging ecosystems. Track record of scaling teams through hiring, onboarding, and mentorship. Experience working with or supporting customers during bring-up, deployment, or escalations. Participation in industry ecosystems such as OCP or OpenBMC. Director level: experience owning multi-program delivery, long-term technical roadmaps, and cross-functional organizational planning. This position can be hired as aSenior Manager Level or Director Level.The base salary range is $230,000 USD – $265,000 USD. Your base salary will be determined based on location, experience, and employees' pay in similar positions. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.Role Overview Astera Labs is seeking a Manager, Package Design Engineering to lead and scale our Package Design team in San Jose. In this high-impact role, you'll own the end-to-end delivery of advanced IC packaging solutions—from early architecture definition through production ramp—enabling the next generation of AI infrastructure and connectivity products. As the semiconductor industry races toward chiplet-based architectures, 2.5D/3D integration, and ever-increasing bandwidth demands, packaging has become a critical differentiator. You'll build and mentor a high-performing team while driving cross-functional execution with silicon architecture, SIPI, PCB, validation, manufacturing, and external partners including substrate vendors and OSATs. Your work will directly impact Astera Labs' ability to deliver industry-leading PCIe, CXL, and Ethernet connectivity solutions to the world's most demanding hyperscale and AI customers. This role offers the opportunity to shape design methodology, establish scalable standards, and enable chip-package-board co-design frameworks across multiple product lines in a fast-moving, innovation-driven environment. Key Responsibilities Team Leadership Execution Build, mentor, and scale a high-performing package design engineering team with clear ownership, accountability, and execution flows Establish design templates, standards, and best-known methods (BKMs) across multiple concurrent programs Lead design reviews, audits, and issue resolution through bring-up and production ramp Package Design Delivery Own end-to-end package design execution including FCBGA/FCCSP, monolithic, multi-die, and chiplet-based designs from concept feasibility through tape-out and production Define and review substrate stack-ups, pad stacks, routing strategies, and design constraints to meet electrical, thermal, mechanical, and manufacturability requirements Drive technical tradeoffs across performance, cost, yield, and schedule, ensuring high-quality design closure and on-time delivery Cross-Functional Collaboration Partner with SIPI, silicon architecture, system/board design, and product teams to drive chip-package-board co-design and resolve system-level challenges Collaborate with OSATs and substrate vendors to ensure design feasibility, manufacturability, and alignment with evolving design rules and technology roadmaps Support adoption of advanced packaging technologies such as 2.5D, chiplet, CPO/CPC, and heterogeneous integration platforms Methodology Automation Develop and scale design methodologies and automation flows to improve efficiency, quality, and repeatability across the organization Basic Qualifications Bachelor's degree in Electrical Engineering, Materials Science, or related field 10+ years of progressive experience in IC package design using tools such as Cadence Allegro APD/SiP 5+ years of leadership experience managing teams or technical organizations in IC packaging environments Strong hands-on expertise in end-to-end package design with proven delivery of HVM-ready FCBGA/FCCSP packages using Cadence APD tool Experience with high-speed SerDes systems (PCIe Gen5/6/7, CXL, Ethernet 100G/200G/400G+) and advanced nodes (7nm, 5nm, 3nm) Deep understanding of substrate technologies, stack-ups, routing constraints, assembly processes, and SI/PI fundamentals Proven experience working with OSATs and substrate vendors through development and production ramp Experience working with OSATs and substrate vendors through development and production ramp Experience with advanced packaging architectures such as 2.5D/3D, chiplet, or heterogeneous integration Preferred Qualifications Master's degree in Electrical Engineering or related field Experience with advanced packaging architectures such as 2.5D/3D, chiplet, or heterogeneous integration Experience implementing automation, scripting (Python, SKILL, Tcl), or workflow optimization Background in early package feasibility, platform evaluation, and technology roadmap development Familiarity with chip floor planning, architecture, and system-level tradeoffs Exposure to SIPI modeling and analysis, thermal, and mechanical performance considerations The base salary range is $230,000 USD – $265,000 USD. This position can be hired as a Manager Level or Director Level. Your base salary will be determined based on location, experience, and employees' pay in similar positions.We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.Role Overview Astera Labs is seeking aSenior HR Business Partnerto join our People team in San Jose, CA. In this high-impact role, you will partner directly with engineering organizations—serving as a trusted advisor, coach, and strategic partner to engineering leaders, managers, and employees across our technical teams. You will bring deep HRBP/Generalist experience, strong employee relations expertise, and substantial knowledge of US labor and employment law to ensure our people practices are both effective and compliant as we scale. This role is critical to supporting the talent strategies, people leader development, and organizational health that enable our engineering teams to deliver world-class AI infrastructure connectivity products. Key Responsibilities 1. Engineering Partnership Coaching Serve as a trusted partner to engineeringpeople leaders, providing hands-on coaching on people management, team dynamics, and leadership effectiveness Build strong relationships across all levelsensuring employees and managers have accessible, credible HR support Coach engineering managers on performance conversations, career development discussions, feedback delivery, and navigating difficult team situations Help translate the unique challenges of semiconductor product development into practical people strategies 2. Employee Relations Compliance Serve as the primary point of contact for employee relations matters across supported engineering groups, handling investigations, performance issues, interpersonal conflict, and conduct concerns with professionalism and care Apply strong knowledge ofNorth Americalabor and employment law—including federal, state, and local regulations—to advise leaders and ensure compliant, defensible people decisions Conduct thorough, fair, and well-documented workplace investigations, partnering with Employment Counsel and Legal on complex or high-risk matters Proactivelyidentifycompliance risks and partner with HR Operations to ensure policies, practices, and manager actions align with legal requirements Stay current on evolving employment legislation and regulatory changes, advising leaders on implications and necessary adjustments Provide clear, empathetic, and legally sound guidance to managers navigating terminations, leaves of absence, accommodations, and other sensitive situations 3. Talent Strategy Organizational Effectiveness Partner with engineering leaders on organizational design, role clarity, and team structure to support product roadmap execution Lead talent reviews, retention planning, and succession planning for critical technical roles Support headcount planning and workforce decisions, balancing near-term delivery needs with long-term capability building Identifytalent risks and hotspots early, working proactively with leaders to address retention and engagement challenges 4. Performance Management Guide leaders and managers through performance cycles, calibration sessions, and compensation reviews with fair, consistent, and well-reasoned recommendations Ensure performance management practices are applied consistently and in compliance with company policy and legal standards Partner with Compensation and HR Operations to supportequitablepay decisions and address compensation-related concerns 5. Operational Excellence Scalability Identifygaps in people processes or manager capability and proactively propose solutions Partner with HR Ops and Centers of Excellence to simplify, standardize, and scale HR practices as the engineering organization grows Operate with an owner's mindset—taking accountability for outcomes, not just recommendations Basic Qualifications Bachelor's degree in Human Resources, Business Administration, Organizational Development, or related field 8+ years of HR Business Partnerexperiencesupporting engineering or technical organizations Demonstrated experience insupporting engineering organizations Strong knowledge ofNorth Americaemploymentand labor law, including federal and California state regulations (wage and hour, leaves, accommodations, terminations, harassment/discrimination) Proventrack recordhandling complex employee relations matters, workplace investigations, and sensitive personnel issues Demonstrated ability to coach managers and build trusted relationships with technical employees at all levels Strong judgment and comfortoperatingin fast-paced, ambiguous environments Clear, confident communicator who can influence and advise engineering leaders effectively Preferred Qualifications PHR, SPHR, SHRM-CP, or SHRM-SCP certification Experience supporting organizations through rapid scaling or hypergrowth phases Background partnering with engineering teams Strong analytical skills with experience using people data to inform talent decisions Track recordof developing manager capability and building coaching cultures within engineering organizations Experience in AI, data center, or connectivity-focused technology companies Salary range is $133,200 to $185,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.As thePrincipal Engineering Program Manager at Astera Labs you will lead all activities required for development, qualification, NPI and RTM (release to manufacturing) of Astera Labs’ ASIC products. This is a high-impact position that is directly responsible for successful execution of critical revenue goals. Key Responsibilities Be the point of contact within Astera for all matters relating to ASIC programs. Own the on-time, on-spec, on-budget and with high-quality delivery of ASIC products from concept through production (architecture, RTL design, verification, physical design, tapeout, validation, customer evaluation, qualification, RTM). Program planning, schedules, budgeting, risk assessment, resource planning and management, and tracking related program activities. Review, disposition and communicate changes in scope / schedule / expense. Conduct regular meetings to ensure cross-functional teams are clear on expectations, and problem-solving actions are in place to address issues in a timely manner. Maintain adequate technical depth and managerial skill to address program and product issues. Be the champion of your programs and maintain management and key stakeholder alignment. Collaborate with the team to ensure customer expectations are exceeded. Actively contribute to organizational development and process improvement initiatives. Job Requirements Bachelors’ or Masters’ Degree in Electronics/Electrical/Computer Engineering 10 or more years of relevant ASIC product experience in an electronics product or semiconductor company Proficiency in ASIC development workflow including hands-on experience in one or more the following domains: Digital design/RTL, DSP or Physical Design Experience in solving technical problems in pre-silicon or post-silicon environment 5 or more years of experience as an ASIC Program Manager is a plus Experience building new ASIC products in advanced technology nodes ( 10 nm) Experience working on ASICs for PCI-E, memory or data communication products is a plus Technical appreciation of ASIC engineering flows (front end and backend development processes, product and test engineering, char and validation, hardware/firmware/software design) Program management and analytical skills, ability to organize information for internal and external consumption Working knowledge of Microsoft Project, Atlassian Tools and JIRA Scrum Methodologies as well as using work breakdown structure to identify objectives and milestones is a plus Able to motivate and energize teams and lead by influence in a matrixed organization Able to take timely decisions with limited or incomplete information Strong communication skills and the ability to keep calm and make progress in high stress situations Ability to travel to Astera Labs’ sites as required Salary range is $185,000 to $230,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.Role SummaryWe are seeking a technically strong Chief of Staff to the Head of Engineering who will also lead Engineering Program Management across Silicon Engineering. This role is a force-multiplier for Engineering leadership — driving org scale, decision velocity, and execution rigor. The ideal candidate brings deep technical fluency, structured problem-solving, and the ability to drive outcomes through influence rather than hierarchy. The role is fully in person in San Jose. Responsibilities — What You Will Own 1) Chief of Staff to Head of Engineering • Drive operational cadence: engineering all hands, staff meetings, agenda/material prep, tech talks, university engagements, action follow-through, and leadership syncs.• Frame and resolve high-leverage decisions — proactively surface blockers (technical, operational, organizational) before they escalate.• Manage escalations and organizational friction — diagnose root causes, coordinate resolution paths, and ensure durable fixes.• Partner cross-functionally with Hardware, Product, and Quality teams to ensure clarity of communication, alignment on priorities, and disciplined follow-through on decisions.• Support org design, headcount planning, and hiring prioritization for engineering teams.• Maintain alignment across functions through clear messaging and communication, validate exitance and validation of processes• Navigate org dynamics, build trust, and constructively challenge assumptions; maintain psychological safety.• Support the head of engineering with administrative and org related activities 2) Lead ASIC Tape out Management (Silicon Programs) • Status management — collect and track status across functions contributing to ASIC tapeouts.• Milestone tracking — maintain methodology checklists and boundary agreements to ensure schedule adherence.• IP and vendor tracking — own visibility into IP deliveries, version inventory, vendor issues, and escalation loops.• Quality documentation — monitor quality KPIs, ensure engineering documentation completeness.• Requirements tracking — ensure PRDs/features are captured, tracked, baselined.• Resource monitoring — track compute, hardware, storage consumption and thresholds.• Internal reporting — generate status reporting for Silicon Engineering leadership. 3) Influence Without Authority • Drive cross-engineering outcomes through credibility, clarity, and follow-through — not hierarchy.• Create order in ambiguous spaces; shape scope where it is undefined. Qualifications • 10+ years in semiconductor/SoC/ASIC or adjacent high-complexity engineering environment (e.g., CPU/IP/System companies).• Proven success in Chief of Staff, Staff Program Manager, TPM Director, or similar technical leadership-enablement role. • Strong technical acumen — able to understand engineering trade-offs and make decisions with limited information, challenge assumptions, and earn credibility with senior ICs.• Demonstrated experience running program cadence for complex silicon programs (tapeout, IP integration, etc.).• Proven ability to organize complex workflows and drive consistent follow-through.• High EQ and organizational awareness; can navigate tension and align diverse viewpoints.• Exceptional written/verbal communication, structured thinking, and execution discipline.• Prior experience in leading RTL2GDSII chip design is a huge plus. What Success Looks Like • Engineering leadership spends more time on strategic and technical decisions, less on coordination.• Milestones hit with fewer escalations and clearer accountability.• Status, risks, and decisions are crisp — never ad hoc or late.• Teams feel supported, not policed — trust increases, friction decreases without compromising on accountability .• Ambiguity decreases over time as clarity and execution rhythm scale with the org. Salary range is $216,000 to $300,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.Do you live, breathe and dream products? Are you passionate about leading the transformation of products from prototype to mass production? Are you thrilled by seeing the product you worked on succeed in the market? If so - we may be looking for you! Role Overview The Engineering Program Manager – Ethernet AEC Products leads cross-functional execution required for development, qualification, NPI, RTM (release to manufacturing) and sustaining phase of Astera Labs’ Ethernet AEC products. This is a high-impact position that is directly responsible for successful execution of critical revenue goals. Key Responsibilities Be the single point of contact within Astera for all matters relating to Ethernet AEC programs including Firmware, Boards and AEC Cables. Own the delivery of Ethernet AEC products across the full lifecycle from concept through production and lead sustaining phase activities: Align activities across various disciplines to ensure customer needs are met Board: spec, design, build qty. planning, EVT/DVT/PVT AEC cable: spec, design, build qty. planning, EVT/DVT/PVT, customer qualification, ramp AEC FW release roadmap and delivery to customers, prioritization of feedback/issues Manage ODM/CM and supplier relationships, including qualification and ramp readiness Maintain adequate technical depth and managerial skills to address program and product issues Program planning, schedules, budgeting, risk assessment, resource planning and management, and tracking related program activities Manage multiple parallel threads of execution while clearly identifying and tracking dependencies Identify risks and bottlenecks and actively work on resolving them Review, disposition and communicate changes in scope / schedule / expense Conduct regular meetings to ensure cross-functional teams are clear on expectations and problem-solving actions are in place to address issues in a timely manner Be the champion of your programs and maintain management and key stakeholder alignment Actively contribute to organizational development and process improvement initiatives Qualifications: Bachelors’ or Masters’ Degree in Electronics/Electrical/Computer Engineering 5–8 years of total professional experience, 3–5+ years in Technical Program Management, Hardware Program Management, or equivalent Experience delivering hardware products from concept to production Working knowledge of high-speed interconnect technologies, Active Electrical Cables (AEC), DACs, optics, or related systems; PCIe, Ethernet, SerDes, or similar interfaces Knowledge of modern datacenter interconnect technologies such as Ethernet, InfiniBand and PCIe is a plus Experience working with external vendors, ODMs, or CMs Program management and analytical skills, ability to organize information for internal and external consumption Technical appreciation of ASIC and Hardware engineering flows (front end and backend development processes, product and test engineering, char and validation, hardware/firmware/software design) Working knowledge Atlassian Tools and JIRA Scrum Methodologies as well as using work breakdown structure to identify objectives and milestones. Working knowledge of Microsoft Project and other program management tools Strong ability to operate in ambiguous, fast-moving environments Able to motivate and energize teams and lead by influence in a matrixed organization Strong communication skills and the ability to keep calm and make progress in high stress situations Ability to travel to Astera Labs’ and manufacturing sites as required Proficiency in Mandarin or other languages is a plus, particularly for working with global suppliers and partners Salary range is $160,000 to $195,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.The Role and Its Impact OurTaurus product lineincludes Ethernetretimersand gearboxes deployed in active electrical cables and in-system applications, providing critical signal conditioning for high-speed connectivity in AI infrastructure. The firmware you develop will manage complex system and IP integration, SERDES configuration, link training sequences, and diagnostic capabilities for these devices deployed in data centers worldwide. As a Principal Engineer in our Signal Connectivity Engineering group,you'llcontribute tofirmware that directlyimpactsthe performance and reliability of Ethernet connectivity solutions powering AI infrastructure globally. Working closely with the SoC software, transceiver module software, and system validation teams,you'lltake ownership of feature development and rollout, software integration testing, and customer debug activities. Working at the intersection of embedded systems and high-speed Ethernet connectivity,you'llcollaborate closely to bring these systems to production. We'rea startup, and this role reflects that reality.You'llhave responsibilities spanning firmware development, customer engagement,debugand validation support, and cross-functional coordination.We'relooking for someone who thrives wearing multiple hats and is energized by jumping into whatever needs doing. We recognize this breadth and reward it accordingly. This position offers strong mentorship opportunities as you work alongside experienced engineers and help bring products from development through customer deployment. Level is negotiable based on experience and qualifications. Location This is an on-site position based in our San Jose, CA office. Core Responsibilities Firmware Development Debug Develop andmaintainembedded firmware for Ethernetretimersand gearboxes, from low-level hardware abstraction through customer-facing APIs Drive Layer 1 PHY and SERDES debug activities, including link bring-up issues, signal integrity problems, and interoperability failures Support complex IP integration efforts across multiple subsystems within the SoC Implement andoptimizelink training sequences, equalization tuning, and diagnostic features Assistwith software quality gates and validation criteria at each development phase Product Rollout Customer Integration Partner with the softwareleadto drive product rollout activities from development through production deployment Support customer integration efforts through firmware customization, debugassistance, and technical guidance Investigate field-reported issues and coordinate resolution with internal teams Develop andmaintainSDK/API interfaces that enable customer platform integration Cross-Functional Collaboration Work extensively with digital SoC teams to understand hardware behavior, register interfaces, and IP integration requirements Collaborate with field applications engineers to support customer bring-up and resolve deployment issues Partner with platform applications teams to ensure firmware meets system-level requirements Work alongside silicon and system validation teams to develop test plans, automate characterization flows, and verify firmware behavior across corner cases Provide regular project updates on progress, risks, dependencies, and technical challenges What You Bring Required Qualifications: BS/MS in Computer Science, Electrical Engineering, Computer Engineering, or related field 10+ years of embedded C/C++ firmware development in resource-constrained environments Deep understanding of microcontroller architecture, memory-mapped peripherals,interrupthandling, and bare-metal firmware design Experience with Layer 1 PHY firmware, SERDES bring-up, or SDK/API development for networking devices Strongproficiencywith Linux development tools:gcc/clang, make, bash scripting,gdb, and git Excellent verbal and written communication skills; ability to explain complex technical concepts clearly Demonstrated problem-solving ability and systematic debugging approach on real hardware Comfort with ambiguity and a willingness to take on whatever challenges arise in a fast-moving startup environment Highly Valued Skills: Experience with PMA, FEC, or related PHY-layer subsystems beyond the PMD/SERDES Familiarity with NIC or switch management software, for system test purposes Exposure to SAI (Switch Abstraction Interface) orOpenBMC Experience with Python for test automation, data analysis, or general scripting Hands-on experience building andmaintainingJenkins CI/CD pipelines and automated test infrastructure Background inretimeror gearbox firmware/API, active electrical cables, or high-speed Ethernet connectivity Experience with lab equipment: oscilloscopes, power supplies, logic analyzers, BERT, Viavi/Lecroy/Exfo/Keysight/Tektronix or similar Understanding of signal integrity concepts: equalization, channel loss, jitter, eye diagrams, and link margin Familiarity with FPGA emulation, pre-silicon validation, or hardware simulation environments Experience with RTOS, device drivers, or coroutines Prior technical lead, mentorship, or team lead experience Compensation Salary range is $185,000 USD - $203,000 USD depending on experience, level, and business need. This role will include a discretionary bonus, competitive equity package, comprehensive health/dental/vision coverage, professional development opportunities, and a culture that values technical excellence, collaboration, and innovation.We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.