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📍【工作內容】 1. 原料藥有機製程開發與優化。 2. 協助解決製程開發相關問題。 3. 與生產單位討論量產相關事宜，以協助GMP量產所需的相關文件。 4. 協助解決量產時所面臨的製程問題，使順

1. Perform Netlist-to-GDS design flow, including floorplanning, placement, timing optimization, clock tree synthesis and routing. 2. Support STA timing analysis and fixing 3. Perform physical verification, including DRC, LVS, IR drop and DFM analysis.

PhD degree in Polymer chemistry/Chemical Engineering/Chemistry is required Experience in condensation polymerization and organic synthesis are required Experience in design and synthesis charged polymers are a plus Experience in formulation development, DOE experience and industrial working experience is a plus Independent researcher as well as team player Strong interpersonal and communication skills Fluent in English & Mandarin Be able to travel to US and within Asia

1. Perform Netlist-to-GDS design flow, including floorplanning, placement, timing optimization, clock tree synthesis and routing. 2. Support STA timing analysis and fixing 3. Perform physical verification, including DRC, LVS, IR drop and DFM analysis.

1. Perform physical synthesis from RTL or gate-to-gate optimization 2. Take responsibility for netlist, SDC and design quality check with customer 3. Chip I/O arrangement and verification with in-house tool 4. Perform low power structure verification (UPF/CPF) 5. Perform power replay and power analysis 6. Review/check implementation quality in each design stage 7. Cooperate with P&R in timing analysis 8. Planning chip

1. Digital IP design and verification. 2. Architecture design, RTL coding, simulation, linting, CDC, synthesis, LEC and STA.

1. Perform TOP or big-scale sub Top Netlist-to-GDS design flow, including floorplanning, placement, timing optimization, clock tree synthesis and routing 2. Support STA timing analysis and fixing 3. Perform physical verification, including DRC, LVS, IR drop and DFM analysis 4. Be the block coordinator for a hierarchical design 5. Take responsibility for schedule control and awareness about critical issues 6. Training and coaching flash/junior engineers

1. Perform physical synthesis from RTL or gate-to-gate optimization 2. Take responsibility for netlist, SDC and design quality check with customer 3. Chip I/O arrangement and verification with in-house tool 4. Perform low power structure verification (UPF/CPF) 5. Perform power replay and power analysis 6. Review/check implementation quality in each design stage 7. Cooperate with P&R in timing analysis 8. Planning chip

1. Perform TOP or big-scale sub Top Netlist-to-GDS design flow, including floorplanning, placement, timing optimization, clock tree synthesis and routing 2. Support STA timing analysis and fixing 3. Perform physical verification, including DRC, LVS, IR drop and DFM analysis 4. Be the block coordinator for a hierarchical design 5. Take responsibility for schedule control and awareness about critical issues 6. Training and coaching flash/junior engineers

1. Perform Netlist-to-GDS design flow, including floorplanning, placement, timing optimization, clock tree synthesis and routing. 2. Support STA timing analysis and fixing 3. Perform physical verification, including DRC, LVS, IR drop and DFM analysis.