Cake Job Search

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.Role Overview Are you passionate about driving strategic growth through impactful corporate development initiatives in the AI and cloud infrastructure space? Astera Labs is seeking a Senior Manager of Corporate Development to lead and support strategic transactions including acquisitions, investments, and strategic partnerships that will shape the future of AI connectivity. In this high-visibility role, you will report to the Head of Corporate Development and work closely with cross-functional teams including engineering, product management, and executive leadership to identify and evaluate opportunities that align with Astera Labs' long-term growth strategy. You will be at the forefront of emerging AI infrastructure technologies, developing new business models and driving transactions that accelerate our position as the leader in purpose-built connectivity solutions. This is a unique opportunity to join a hyper-growth company at the intersection of semiconductors and AI infrastructure, where your work will directly influence strategic decisions and contribute to building the connectivity backbone powering the next generation of data centers. Key Responsibilities Strategic Transaction Leadership Lead and support corporate development transactions through all phases of the transaction lifecycle, from target identification through close Partner with executive and engineering leaders to evaluate opportunities that address strategic gaps and conduct build/buy/partner analysis Lead deal-oriented project management throughout the entire deal lifecycle, ensuring timely execution and stakeholder alignment Financial Strategic Analysis Conduct detailed financial analyses including valuation, pro forma modeling, and investment assessments to evaluate deal alignment Develop executive presentation materials to provide recommendations to the leadership team and board Research adjacent and new market opportunities, including opportunity sizing, target landscaping, and competitive analysis Cross-Functional Collaboration Integration Collaborate with cross-functional teams to drive diligence and validate key assumptions and value drivers Oversee post-merger integration to ensure deals deliver long-term success and structural enhancement for the company Define and continually enhance the company's strategy to acquire new business opportunities and partnerships Market Intelligence Develop deep expertise in emerging AI infrastructure technologies, companies, and business models Monitor industry trends and competitive dynamics to inform corporate development strategy Basic Qualifications Bachelor's degree in Business Administration, Electrical Engineering, Computer Science, or related field 8+ years of experience in corporate development, investment banking, private equity, venture capital, or related roles Experience in the semiconductor, high-tech, or AI infrastructure industry Demonstrated experience leading strategic transactions and working with executive leadership Strong analytical skills with expertise in valuation, financial modeling, and strategic analysis Excellent communication and presentation skills with the ability to convey complex concepts clearly to diverse audiences Preferred Qualifications MBA or advanced degree Direct experience with MA transactions in the semiconductor or data center infrastructure space Knowledge of AI/ML infrastructure, PCIe, CXL, or Ethernet technologies Proven ability to collaborate effectively across engineering and business functions Experience with post-merger integration planning and execution Willingness to travel as needed for deals, company training, industry events, and conferences Salary range is $170,500 to $230,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com. Role Overview Astera Labs' Taurus product line includes Ethernet retimers and gearboxes deployed in active electrical cables and in-system applications at the heart of AI infrastructure. As AI clusters scale to tens of thousands of GPUs connected by high-speed Ethernet fabrics, the firmware running on these connectivity devices is mission-critical — and so is the ability to debug it fast when something breaks. We're looking for a Firmware Engineer who can bridge our system validation team and firmware development organization. When something goes wrong in the lab or in the field, you won't be waiting on others to dig into the firmware. You'll be the person in the room who understands both sides — can pull up the code, identify the problem, and fix it. If you've worked at a networking company, know how Ethernet actually works from the MAC down through the PHY, have debugged real link failures, and have written or modified firmware or low-level drivers, this role was designed for you. Your primary focus will be debug and system integration. You will be an integral part of the firmware team and work on new feature development, but you will be the point person in the lab helping to unblock other teams — triaging failures, understanding what the firmware is doing, and making targeted fixes without requiring a long handoff loop. Beyond that, you'll contribute to feature development and help bring new products from initial bringup into customer deployment. Key Responsibilities Debug System Integration Work directly with the system validation team to debug firmware behavior across different Ethernet configurations, link states, and failure modes Investigate and fix firmware issues in embedded C, leveraging deep understanding of how Layer 1 PHY, SERDES, FEC/PCS, MAC, and retimer components interact Serve as the connective tissue between firmware and system validation teams, triaging issues and driving them to resolution without long handoff loops Customer Bring-Up Field Support Support customer bring-up and integration activities, including triaging field issues and coordinating fixes with internal teams Partner with field applications engineers to diagnose and resolve deployment issues quickly Firmware Feature Development Contribute to firmware feature development for SERDES configuration, link training, equalization, and diagnostics Partner with SoC, field applications, and platform teams across the full product lifecycle Help bring new Taurus products from initial silicon bringup through customer deployment Basic Qualifications Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field 5+ years of experience in firmware development or embedded systems engineering Hands-on experience with Ethernet at the system or device level: Layer 1 PHY, SERDES, retimers, gearboxes, NICs, switches, or related devices Solid embedded C/C++ skills and comfort working in a firmware codebase on real hardware Ability to debug across the hardware/software boundary: register accesses, embedded SDKs, link state machines, PHY telemetry, debug print logs Familiarity with Linux development tools: gcc/clang, make, bash, gdb, git Strong communication skills and comfort working in a fast-moving environment where the problem in front of you may not have a clean solution Preferred Qualifications Experience with switch or NIC management software, SAI, or OpenBMC Knowledge of PMA, FEC, or other PHY-layer subsystems beyond the SERDES Background with retimer or gearbox firmware or SDK/API development Python scripting for debug, test automation, or data analysis Experience with lab equipment: BERT, oscilloscopes, Viavi/Lecroy/Exfo/Keysight/Tektronix or similar Understanding of signal integrity: equalization, jitter, eye diagrams, link margin Prior experience mentoring engineers or leading debug efforts across teams Salary range is $133,200 to $185,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.About the Role As a Principal Product Applications Engineer on the Leo team, you will sit at the intersection of firmware engineering and customer-facing technical engagement. You will be a key technical resource for enabling Leo CXL Smart Memory Controllers at hyperscale customers and OEM partners — owning firmware bring-up, validation, and customer issue resolution from early silicon through production ramp. Firmware is considered equally important to hardware at Astera Labs, and this role reflects that. You will work directly with customers to ensure their needs are fully understood and translated into firmware solutions, while collaborating closely with the internal firmware, hardware, and systems engineering teams. This position is required onsite in San Jose, CA. Key Responsibilities Lead firmware-focused customer engagements for Leo CXL Smart Memory Controllers, including bring-up support, feature enablement, and issue triage on customer platforms Develop, validate, and debug firmware using C and Python across Leo's PCIe/CXL and DDR memory subsystems Spearhead internal and external discussions on design requirements of DDR4/DDR5 DRAM interfaces, including initialization, training, RAS (Reliability, Availability, Serviceability) features, and performance tuning Serve as the primary firmware technical point of contact for key customer accounts (hyperscalers, OEMs), driving issue resolution and feature demonstrations Interpret and implement requirements from CXL, PCIe, and JEDEC DDR specifications into robust firmware solutions Collaborate with cross-functional teams (FW engineering, HW, systems, product management) to deliver firmware releases and customer collateral on schedule Develop and maintain Python-based test scripts, automation frameworks, and diagnostic tools to support validation and customer debug workflows Contribute to technical documentation including application notes, release notes, design guides, and customer-facing collateral Represent the Leo team in customer technical reviews, design-in engagements, and industry forums Basic Qualifications Bachelor's degree in Electrical Engineering, Computer Science, or a related technical field; Master's degree preferred 8+ years of experience in firmware development, product applications engineering, or a related technical role supporting complex SoC/silicon products for Server, Storage, and/or Networking applications Professional attitude with the ability to prioritize a dynamic list of tasks and work with minimal guidance Entrepreneurial, open-minded behavior and can-do attitude — think and act fast with the customer in mind! Authorized to work in the US and available to start immediately Required Experience High proficiency in C for embedded firmware development in RTOS environments Working knowledge of CXL (Compute Express Link) — CXL 1.1/2.0/3.0 — including memory expansion, pooling, and sharing concepts Proficiency in Python for scripting, test automation, and diagnostic tooling Deep hands-on knowledge of high-speed memory interfaces — DDR4 and/or DDR5 DRAM — including initialization sequences, training algorithms, timing margins, and ECC/RAS features Experience with firmware bring-up, debug, and validation of memory or I/O subsystems on server platforms Strong debugging skills with the ability to triage and root-cause issues in complex embedded systems Familiarity with SoC interfaces including DDR controllers, PCIe controllers, and on-chip memory subsystems Experience working with developer workflows: SCM (preferably Git), code reviews, CI/CD pipelines Preferred Experience Experience with PCIe endpoint firmware at the PHY, Link, and Transaction layers; familiarity with PCIe enumeration, MSI/MSI-X, SR-IOV, and error handling Hands-on experience with PCIe/CXL protocol analyzers, BERT, and other lab debug equipment Familiarity with BIOS/BMC/OS interactions with PCIe/CXL devices and MMIO/RAS concepts Experience with server memory performance tuning — latency and bandwidth optimization Prior customer-facing or field applications experience in a semiconductor or systems company is a strong plus Compensation The base salary range for this role is $175,000 – $230,000 USD. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. Astera Labs is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.As an Astera Labs SeniorLab Validation Engineer, you will take a hands-on role to find the root cause of any customer quality concerns and develop corrective actions. You will: Directly root-cause failures to the circuit, package, firmware, or protocol-level interactions. Collaborate with design, validation, and system engineering teams as needed. Modify device firmware to test out engineering theories leading to potential fixes or production screens. Investigate failures such as link training issues, lane margining failures, eye closure, jitter sensitivity, protocol errors, and interoperability problems. Debug retimer specific failures, including pass-through path issues, clock forwarding problems, equalization settings, and link bring-up reliability. Analyze high speed link failures, including lane mapping, bifurcation errors, hot-plug issues, compliance test failures, and error propagation across multiple ports. Use advanced lab instrumentation (BERT, high-bandwidth oscilloscopes, protocol analyzers, VNAs, TDR, spectrum analyzers) to characterize and isolate failures. Develop and run stress tests and margining experiments to identify weak design or process corners. Provide feedback on system-level integration challenges for retimers and PCIe switches (e.g., board layout, equalization tuning, firmware interactions). Drive physical failure analysis to isolate and image defects using methods such as fault isolation, probing, de-processing, FIB, thermal/voltage stress testing. Document debug findings, propose design/process/test improvements, and contribute to FA methodologies. Participate in new product development process to ensure readiness for customer returns before products are launched. Collaborating in the development of evaluation hardware (boards and sockets, including FA friendly sockets) and scripts. Basic qualifications: Minimum of a Bachelor’s in Electrical Engineering while a Master’s degree is preferred. Minimum of 5 years relevant experience of which 5 years’ is hands-on mixed high-speed lab experience working with equipment such as protocol analyzers, BERT, real-time scopes, sampling scopes, TDR, and VNA. Python programming. Deep understanding of PCIe protocol (up through Gen6), retimer architecture, and SerDes signal integrity. Hands-on experience debugging retimers (equalization tuning, pass-through mode, clocking, reset/link sequencing). Hands-on experience debugging PCIe switches (lane bifurcation, hot-plug, multi-port link stability, compliance failures). Strong background in NRZ/PAM4 architectures, investigating issues with jitter, CDR/PLL behavior, equalization (DFE, CTLE, FFE), crosstalk, and power integrity. Experience in post-silicon validation and bring-up of high-speed PHYs or retimers. Solid problem-solving and analytical skills with ability to narrow down complex multi-layer failures. Strong written and verbal communication skills. Preferred experience (ideal candidate has some of this, but OJT is also possible): C (not C++). Experience with optics. Experience with chip-level security and RAS features. ATE (Automated Test Equipment) Advantest V93K. Understanding of system-level architecture for servers, storage, and AI/ML platforms where PCIe retimers/switches are deployed. Based in San Jose, this position requires an in-person presence, offering a unique opportunity to impact our global operations directly. The base salary range is $160,000 USD - $195,000 USD. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.Role Overview Astera Labs is seeking a Senior Director of Product Marketing to lead go-to-market strategy for our industry-leading fabric switch and memory controller solutions. This is a high-impact leadership role at the intersection of technology and market strategy, where you'll shape how the world's largest hyperscalers and AI infrastructure builders understand and adopt our connectivity products. As a senior leader on the product marketing team, you'll drive positioning, messaging, and competitive strategy for products enabling the next generation of AI and cloud data centers. You'll partner closely with engineering, sales, and executive leadership to translate customers’ needs into competitive roadmaps and compelling value propositions that resonate with decision-makers. This role requires someone who can move fluidly between silicon-level technical discussions and strategic market conversations. With AI infrastructure demand accelerating and Astera Labs at the forefront of solving critical connectivity bottlenecks, this is an opportunity to shape the narrative for technologies like PCIe, UALink, CXL and emerging high-speed protocols that are powering rack-scale AI systems worldwide. Key Responsibilities Go-to-Market Strategy Execution Lead product strategy, positioning, and go-to-market strategy for fabric switch and controller product lines Define and execute product launches that drive awareness, demand, and adoption with hyperscaler and enterprise customers Develop compelling content including presentations, blogs, datasheets, and technical collateral Market Competitive Intelligence Own competitive analysis and market intelligence for fabric switch controller product lines Identify market trends, customer needs, and emerging opportunities in AI infrastructure connectivity Translate market insights into actionable product and positioning recommendations Cross-Functional Leadership Partner with engineering to deeply understand product capabilities and drive roadmap Enable sales teams with training, tools, and competitive positioning to win strategic accounts Collaborate with executive leadership to align product marketing initiatives with corporate strategy Team Stakeholder Management Build and mentor a high-performing product marketing team Serve as a technical spokesperson at industry events, customer meetings, and analyst briefings Drive alignment across marketing, product, and sales organizations Basic Qualifications Bachelor's degree in Electrical Engineering, Computer Engineering, or related technical field 12+ years of experience in product marketing, product management, or technical marketing roles Demonstrated experience with PCIe technology or high-speed switching/interconnect products Strong understanding of semiconductor products and silicon development lifecycle Proven track record of leading successful product launches in the data center or infrastructure market Experience presenting to and influencing technical audiences including engineers and architects Preferred Qualifications MBA or Master's degree in a technical discipline Experience marketing to hyperscaler and enterprise customers (AWS, Google, Microsoft, Meta, etc.) Familiarity with high speed connectivity protocols, such as UALink, PCIe, and CXL Background in AI/ML infrastructure or data center architecture Experience building and leading product marketing teams at high-growth technology companies Strong executive presence and public speaking skills for industry events and analyst engagements Salary range is $240,000 to $300,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.Role Overview Astera Labs is seeking a Director of Product Marketing to leadgo-to-market strategy for our industry-leading connectivity solutions. This is a high-impact leadership role at the intersection of technology and market strategy, whereyou'llshape how the world's largesthyperscalersand AI infrastructure builders understand and adopt our PCIesignal conditioning products. As a senior leader on the product marketing team,you'lldrive positioning, messaging, and competitive strategy for products enabling the next generation of AI and cloud data centers.You'llpartner closely with engineering, sales, and executive leadership to translate deep technical capabilities into compelling value propositions that resonate with technical decision-makers. This role requires someone who can move fluidly between silicon-level technical discussions and strategic market conversations. With AI infrastructure demand accelerating and Astera Labs at the forefront of solving critical connectivity bottlenecks, this is an opportunity to shape the narrative for technologies like PCIe Gen 6/7 andUALink that are powering rack-scale AI systems worldwide. Key Responsibilities Go-to-Market Strategy Execution Lead product positioning, messaging, and go-to-market strategy for PCIe signal conditioning product line Define and execute product launches that drive awareness, demand, and adoption withhyperscalerand enterprise customers Develop compelling content including presentations, white papers, datasheets, and technical collateral Revenue Impact Accountable for revenue delivery through new design wins, flawless execution of active programs, and driving long-term growth across strategic accounts Drive alignment between product positioning and business objectives, ensuring strategies translate into measurable revenue growth Market Competitive Intelligence Own competitive analysis and market intelligence for PCIesignal conditioning markets Identifymarket trends, customer needs, and emerging opportunities in AI infrastructure connectivity Translate market insights into actionableproductand positioning recommendations Cross-Functional Leadership Partner with engineering to deeply understand product capabilities and roadmap Enable sales teams with training, tools, and competitive positioning to win strategic accounts Collaborate with executive leadership to align product marketing initiatives with corporate strategy Team Stakeholder Management Build and mentor a high-performing product marketing team Serve as a technical spokesperson at industry events, customer meetings, and analyst briefings Drive alignment across marketing, product, and sales organizations Basic Qualifications Bachelor’s degree in electrical engineering, Computer Engineering, or related technical field 10+ years of experience in product marketing, product management, or technical marketing roles Demonstrated experience with PCIe technology or high-speed switching/interconnect products Strong understanding of semiconductor products and silicon development lifecycle Proventrack recordof leading successful product launches in the data center or infrastructure market Experience presenting to and influencing technical audiences including engineers and architects Preferred Qualifications MBA ormaster’sdegree ina technicaldiscipline Experience marketing tohyperscalercustomers (AWS, Google, Microsoft, Meta, etc.) Familiarity with emerging standards such asUALink, or PCIe Gen 6/7 Background in AI/ML infrastructure or data center architecture Experience building and leading product marketing teams at high-growth technology companies Strong executive presence and public speaking skills for industry events and analyst engagements Salary range is $180,000 to $250,000 depending on experience, level, and businessneed. This role may be eligible for discretionarybonus,incentivesand benefits.We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com. About Astera Labs Astera Labs is the connectivity backbone of rack-scale AI infrastructure. Our Active Electrical Cables (AEC), Smart Cable Modules (SCM), Silicon Evaluation Platforms, and rack-scale products deliver purpose-built, high-speed connectivity for the world's most demanding AI clusters. As our product portfolio expands in complexity, performance, and volume — and as OEM customers increasingly adopt Astera Labs silicon into their own designs — we need a senior engineering leader to build and scale the hardware design engineering organization that creates industry-defining products and enables our customers' success. We are hiring a Senior Principal Engineer, AEC Product Integration to serve as the senior technical integration leader for Astera Labs' Active Electrical Cable product line. This is a deeply technical, hands-on individual contributor role at the most senior level — responsible for ensuring that every element of an AEC product (silicon, firmware, PCB/substrate, cable assembly, connector, mechanical, thermal, and signal integrity) comes together into a fully validated, production-ready, customer-qualified product. You will be the single technical point of accountability for AEC product integration — the person who sees the complete picture, identifies gaps between disciplines, resolves cross-domain technical conflicts, and drives closure on the hardest integration challenges. You'll work at the intersection of hardware design, firmware, signal integrity, mechanical engineering, test, manufacturing, and customer applications — ensuring that Astera Labs' AEC products meet or exceed performance, quality, and reliability targets at scale. Reporting to the AVP of AEC/SCM Hardware Engineering, you'll partner closely with engineering leads across all disciplines, as well as NPI, QA, validation, manufacturing, and customer engineering teams. You won't manage a large organization — instead, you'll lead through technical depth, cross-functional influence, and the ability to drive complex multi-variable problems to resolution. Key Responsibilities End-to-End Product Integration Own the technical integration of AEC products across all constituent domains: ASIC/retimer silicon, firmware, PCB/flex circuit, cable assembly, connector interface, mechanical housing, thermal management, and signal integrity Define and maintain the AEC product integration plan — identifying all cross-domain interfaces, dependencies, risks, and validation checkpoints from early design through mass production release Serve as the central technical authority who ensures all subsystem specifications are mutually consistent, physically realizable, and collectively deliver the target product performance Drive integration trade-off decisions when competing requirements across domains (e.g., signal integrity vs. mechanical, thermal vs. cost, firmware timing vs. test coverage) require resolution Own the AEC product-level specification, ensuring it flows coherently from system-level customer requirements down to component-level specifications for each engineering team Signal Integrity Electrical Performance Integration Ensure end-to-end channel performance meets target specifications across the full AEC link — from host connector, through PCB/substrate, retimer silicon, flex/cable medium, and far-end connector Partner with Signal Integrity engineers to validate channel models, S-parameter budgets, eye diagram margins, and compliance to relevant standards (IEEE 802.3ck/dj, OIF CEI-112G/224G) Drive resolution of signal integrity issues that span multiple domains — e.g., connector-to-PCB transition optimization, cable-to-substrate impedance matching, crosstalk between differential pairs in dense cable bundles Define and enforce electrical interface specifications at every integration boundary (silicon-to-substrate, substrate-to-cable, cable-to-connector, connector-to-host) Hardware Mechanical Integration Coordinate the physical integration of retimer silicon, passive components, flex circuits or PCBs, cable assemblies, and mechanical housings into a unified AEC product form factor Work with Mechanical Engineering to ensure connector mating, latching, strain relief, bend radius, thermal dissipation, and form factor compliance are achieved within customer and standards requirements Drive resolution of mechanical-electrical conflicts (e.g., routing density vs. housing volume, thermal solution vs. weight/form factor, strain relief vs. cable flexibility) Review and approve mechanical drawings, 3D models, tolerance stacks, and assembly sequences for AEC products Firmware Silicon Integration Partner with Firmware Engineering to ensure retimer/re-driver firmware initialization, link training, equalization, and diagnostic features integrate correctly with the AEC hardware platform Define firmware-hardware interface requirements — including power sequencing, thermal monitoring/throttling, I2C/CMIS register maps, and in-field diagnostic capabilities Drive debug and root-cause analysis of integration issues that span silicon, firmware, and hardware boundaries (e.g., link instability tied to power delivery transients, equalization failures tied to channel asymmetry) Ensure AEC products comply with relevant management interface standards (CMIS, SFF-8636, or proprietary host interfaces) Test Validation Integration Define the AEC product-level validation plan — ensuring comprehensive coverage across electrical performance, mechanical durability, environmental reliability, firmware functionality, and interoperability Partner with Test Engineering to specify end-of-line production test requirements that validate all critical integration parameters without excessive test time Drive cross-domain failure analysis when product-level test failures cannot be attributed to a single subsystem — marshaling resources across SI, hardware, firmware, and mechanical teams to identify root cause Own the integration test phase during NPI — defining entry/exit criteria, managing issue trackers, driving closure, and making go/no-go recommendations for production readiness Customer Integration Interoperability Serve as the senior technical interface for AEC product integration with customer platforms — understanding host ASIC requirements, switch/NIC compatibility, rack-level cabling architectures, and system-level thermal/mechanical constraints Drive interoperability testing and debug with customer hardware, resolving link-level issues that may involve Astera Labs' AEC, customer host silicon, or system-level environmental factors Translate customer integration feedback into actionable engineering requirements and design improvements for current and future AEC generations Support customer qualification activities by providing technical data packages, integration guides, and direct engineering engagement Cross-Functional Technical Leadership Lead cross-domain integration reviews and design reviews — bringing together hardware, firmware, SI, mechanical, test, manufacturing, and quality engineers to assess readiness at each product milestone Identify and escalate integration risks early — proposing mitigation plans and driving pre-emptive resolution before issues reach production or customer sites Establish and document integration best practices, lessons learned, and reusable frameworks that improve efficiency across successive AEC product generations Mentor engineers across disciplines on systems-level thinking and cross-domain integration methodology Manufacturing NPI Integration Partner with Manufacturing Engineering and NPI teams to ensure that the integrated AEC product design is manufacturable, testable, and scalable at volume Participate in DFM/DFA/DFT reviews with a focus on integration-critical process steps (e.g., cable-to-substrate attachment, retimer placement, overmolding, connector alignment) Support production ramp by driving resolution of integration-related yield issues, process excursions, or field failures that span multiple manufacturing operations Define incoming inspection and in-process integration verification checkpoints to catch cross-domain defects early in the production flow Basic Qualifications Bachelor's degree in Electrical Engineering, Computer Engineering, or related technical discipline 15+ years of experience in hardware product development, with substantial focus on high-speed interconnect, cable assembly, transceiver/module, or mixed signal/digital system integration Demonstrated track record as a technical integration leader — owning the full-product convergence across multiple engineering disciplines on complex hardware products Deep understanding of high-speed serial link design (56G/112G PAM4 or above), including signal integrity, channel modeling, equalization, and link budgeting Strong working knowledge of PCB/substrate design, cable assembly construction, connector technology, and mechanical packaging for high-speed interconnects Experience with firmware/hardware integration on products containing retimers, re-drivers, or PHY-layer silicon Proven ability to drive complex cross-functional debug and root-cause analysis spanning electrical, mechanical, firmware, and manufacturing domains Experience supporting customer integration, interoperability testing, and platform-level qualification Excellent communication skills — able to distill complex multi-domain trade-offs for both technical peers and executive audiences Willingness to travel (20–30%) to CM sites in Asia and customer locations as required Preferred Qualifications Master's or Ph.D. in Electrical Engineering with emphasis on high-speed interconnects, signal integrity, or mixed-signal systems Direct hands-on experience with Active Electrical Cables (AEC), Active Copper Cables (ACC), Direct Attach Cables (DAC), or Smart Cable Modules (SCM) Experience integrating products based on retimer or linear re-driver ASICs (e.g., Astera Labs Aries, Broadcom, Marvell, or equivalent) Deep familiarity with relevant standards: IEEE 802.3ck (100G/lane), 802.3dj (200G/lane), OIF CEI-112G, CEI-224G, SFF-8636, CMIS, OSFP, QSFP-DD Experience with 224G/lane (1.6T) interconnect technology and next-generation cable/connector architectures Background in system-level integration for hyperscale data center or AI infrastructure applications Experience with contract manufacturers in Asia for cable assembly or module production Familiarity with environmental/reliability testing standards (GR-468, Telcordia, IEC) for interconnect products Mandarin language proficiency for direct technical engagement with Asian manufacturing partners Experience with simulation tools (HFSS, ADS, CST, or equivalent) and lab measurement equipment (oscilloscopes, BER testers, VNAs, TDR) We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Logitech is the Sweet Spot for people who want their actions to have a positive global impact while having the flexibility to do it in their own way.The RoleWe are seeking a highly experienced Principal Software Technical Program Manager (TPM) tolead and own complex, software-driven programs across the full Software Development Lifecycle (SDLC) for Video Conferencing products. This role operates at the intersection of embedded software, Android/Linux system software and cloud services.As a senior software program leader, you will drive end-to-end software execution from concept through launch and post-deployment ensuring strong technical alignment across Software Engineering, Product Management, Quality Engineering, and Operations. You will be accountable for software delivery outcomes, execution rigor, and cross-functional alignment required to ship high-quality, scalable products at enterprise scale. This role demands deep software technical understanding, excellent communication, and the ability to lead through influence, clarity, and decision-making across global teams.Your ContributionAs a Principal Software Lead and software execution leader, you will:● Lead large-scale, multi-disciplinary software programs spanning firmware, embeddedLinux/Android system software, and cloud-connected services.● Act as the single point of ownership for software program execution, ensuring alignment across Software Engineering, Product Management, Program Management, and Quality Engineering.● Drive clarity of scope, requirements, dependencies, risks, and delivery timelines, holding teams accountable to commitments.● Establish and enforce strong planning, execution, and tracking frameworks, including Jira workflows and operational metrics.● Translate complex technical topics into clear executive-level updates, enabling informed decision-making.● Proactively identify risks, drive mitigation strategies, and resolve execution blockers to maintain schedule, quality, and software readiness.● Champion operational excellence by continuously improving software development processes, communication, and cross-team execution models.Key ResponsibilitiesSoftware Program Leadership Execution● Lead cross-functional execution across firmware, embedded Linux, Android platform engineering, cloud/backend services and QA.● Drive software roadmap alignment, engineering readiness, milestone planning, and release execution.● Own trade-off decisions across scope, schedule, and quality, with a strong bias toward long-term software sustainability and product quality. Planning, Tools, and Process Excellence● Define and maintain Jira workflows, dashboards, boards, and reporting structures forhighly complex, multi-team software programs.● Implement scalable, repeatable execution processes that support distributed global teams.● Establish clear operating rhythms (planning, execution, reviews, and retrospectives) to ensure predictable delivery.Technical Leadership Problem Solving● Maintain a system-level understanding of software architecture for hardware devices running embedded Linux/Android and cloud-connected services.● Engage deeply with architects and senior engineers to validate feasibility, sequencing, and technical risk.● Drive resolution of cross-layer issues spanning hardware, system software, applications, and cloud services.● Ensure engineering quality, integration readiness, and software stability throughout the development lifecycle.Required Qualifications:●10 years of experience in Technical Program Management or Software Program Leadership delivering complex, software-intensive products at scale.● Proven track record of shipping embedded Linux, Android-based, and/or cloud-connected devices.● Strong understanding of hardware-software co-development, including EVT/DVT/PVT cycles and manufacturing readiness (highly desirable).● Expert-level proficiency with Jira, Confluence, and modern program management tools.● Exceptional written and verbal communication skills, with the ability to operate effectively at both engineering and executive levels.● Demonstrated ability to lead through influence, drive alignment, and make decisions in highly ambiguous environments.● Experience leading global, multi-time-zone teams and complex cross-organizational initiativesCompensation:This position offers an annual base salary typically between $ 141,000- $220,000.In certain circumstances, higher compensation will be considered based on the business need, candidate experience, and skills.  #LI-SN1  Across Logitech we empower collaboration and foster play. We help teams collaborate/learn from anywhere, without compromising on productivity or continuity so it should be no surprise that most of our jobs are open to work from home from most locations. Our hybrid work model allows some employees to work remotely while others work on-premises. Within this structure, you may have teams or departments split between working remotely and working in-house.Logitech is an amazing place to work because it is full of authentic people who are inclusive by nature as well as by design. Being a global company, we value our diversity and celebrate all our differences. Don’t meet every single requirement? Not a problem. If you feel you are the right candidate for the opportunity, we strongly recommend that you apply. We want to meet you!We offer comprehensive and competitive benefits packages and working environments that are designed to be flexible and help you to care for yourself and your loved ones, now and in the future. We believe that good health means more than getting medical care when you need it. Logitech supports a culture that encourages individuals to achieve good physical, financial, emotional, intellectual and social wellbeing so we all can create, achieve and enjoy more and support our families. We can’t wait to tell you more about them being that there are too many to list here and they vary based on location.All qualified applicants will receive consideration for employment without regard to race, sex, age, color, religion, sexual orientation, gender identity, national origin, protected veteran status, or on the basis of disability.If you require an accommodation to complete any part of the application process, are limited in the ability, are unable to access or use this online application process and need an alternative method for applying, you may contact us toll free at 1-510-713-4866 for assistance and we will get back to you as soon as possible.

Logitech is the Sweet Spot for people who want their actions to have a positive global impact while having the flexibility to do it in their own way.Location:  Logitech is proud to support a hybrid work culture.  At this time, we are only seeking hybrid candidates based in the San Jose/San Francisco Bay, CA Metro Areas.The Team and Role:Youll be joining our dynamic Global Communications team, a group of passionate storytellers responsible for shaping Logitechs narrative worldwide. We are at the center of the action, working with our innovative product groups in gaming, creativity, and productivity to share how Logitech is helping everyone pursue their passions. We’re seeking a Communications Specialist to help power global storytelling for cross-category communications supporting Logitech Consumer and Business, as well as Logitech G, our Gaming category. In this role, you’ll bring Logitech’s voice to life through product launches, partnerships, and global moments. You’ll work across PR, social, brand, product marketing, and influencer teams to tell stories that feel human, relevant, exciting, and unmistakably Logitech.This is a hands-on, high-visibility role for someone who loves gaming, tech, culture, and storytelling, and is ready to help elevate a brand that’s defining the future of work and play.Your Contribution:Be Yourself. Be Open. Stay Hungry and Humble. Collaborate. Challenge. Decide and just Do. Share our passion for Equality and the Environment. These are the core behaviors and values you’ll need for success at Logitech. In this role, you will responsible for:Communications Storytelling:Manage cross-category and gaming-specific PR campaigns, including receiving/producing briefs, developing plans, and overseeing execution for press, community, and eventsDraft and edit press releases, media pitches, blog posts, executive quotes, and talking pointsServe as a point of contact for inbound PR agencies, including media outreach, media list creation, pitching updates/reviews, and managing incoming media queriesIndependently manage earned media programs (with support of PR agency) for product launches, brand campaigns, and creator culture activationsDraft internal blog posts, Logitech news announcements, media alerts, and local press releases. Monitor and maintain reporting tools for earned mediaSupport cross-category requests, including brand portfolio pitches, Holiday Gift Guides, award compilation, etc. Media Creator Activation:Support outreach to press and partners in gaming, tech, lifestyle, trade and sportsCollaborate with social and creator/influencer leads to execute integrated campaigns Help track coverage, sentiment, reach, and earned media value (EMV)Campaign Event Support:Support planning and execution of global moments (e.g., Logitech G Play, CES, Gamescom, Logi Work, and major partnerships)Coordinate timelines, assets, approvals, and internal communication flowsAssist with press tours, briefings, and creator activationsCross-functional Collaboration:Work closely with Product Marketing, Social, Design, Esports, Partnerships, and Regional teamsSupport briefings and communications alignment with Business Groups (Personal Workspace, Logitech for Business, Logitech G) and external agenciesHelp maintain consistency in voice, messaging, and brand positioning globallyMeasurement Optimization:Track campaign performance using coverage reports, dashboards, and data toolsOptimize and develop processes to increase efficiency, alignment, and impact across global and regional teams.Turn data into insights and recommendations for future campaignsSupport Comms scorecards, KPI tracking, and reportingKey Qualifications:Strong hands-on experience in communications, public relations, marketing, or a related fieldBasic AI fluency, with the ability to use approved AI tools to support research, content development, and workflow efficiency while following brand, legal, and ethical guidelines.Experience in tech, gaming, sports, or consumer electronics preferredStrong writing, editing, and storytelling skills across multiple formatsUnderstanding of media relations and influencer/creator ecosystemsHighly organized, detail-oriented, and able to manage multiple projects at onceComfortable working in fast-paced, high-growth, highly visible environmentsExperience working cross-functionally (Product, Marketing, Social, Design, Agencies)Knowledge of gaming culture, platforms (Twitch, YouTube, TikTok), and esports is a major plusExperience working with global/regional/local teams across the world and developing communication toolkitsPreferred Qualifications:Worked on or managed integrated communications campaignsExperience working with multiple brands (consumer tech, FMCG, lifestyle brands preferred) #LI-CT1This position offers an annual salary of typically between $ 87K and $ 122K dependent on location and experience.  In certain circumstances, higher compensation will be considered based on the business need, candidate experience, and skills,Logitech offers benefits such as Medical Coverage, Dental Coverage, Vision Coverage, Traditional and Roth 401(k) Plans, Flexible Spending Accounts, Employee Share Purchase Plan (ESPP), Basic and Additional Life Insurance, Disability Coverage, Adoption and Surrogacy Assistance, Tuition Reimbursement Plans, Commuter Benefits, Paid Time Off, Paid Holidays, Bereavement Leave, and Paid Parental Leave.  Logitech also offers Wellness Programs, Health Savings Account Plans, access to Expert Medical Opinions, Identity Theft Protection, Breast Milk Delivery to Nursing Mothers on Business Travel, access to a Group Legal Plan, Donations Matching Programs, Employee Product Discounts, and access to Auto, Home, and Pet Insurance. Across Logitech we empower collaboration and foster play. We help teams collaborate/learn from anywhere, without compromising on productivity or continuity so it should be no surprise that most of our jobs are open to work from home from most locations. Our hybrid work model allows some employees to work remotely while others work on-premises. Within this structure, you may have teams or departments split between working remotely and working in-house.Logitech is an amazing place to work because it is full of authentic people who are inclusive by nature as well as by design. Being a global company, we value our diversity and celebrate all our differences. Don’t meet every single requirement? Not a problem. If you feel you are the right candidate for the opportunity, we strongly recommend that you apply. We want to meet you!We offer comprehensive and competitive benefits packages and working environments that are designed to be flexible and help you to care for yourself and your loved ones, now and in the future. We believe that good health means more than getting medical care when you need it. Logitech supports a culture that encourages individuals to achieve good physical, financial, emotional, intellectual and social wellbeing so we all can create, achieve and enjoy more and support our families. We can’t wait to tell you more about them being that there are too many to list here and they vary based on location.All qualified applicants will receive consideration for employment without regard to race, sex, age, color, religion, sexual orientation, gender identity, national origin, protected veteran status, or on the basis of disability.If you require an accommodation to complete any part of the application process, are limited in the ability, are unable to access or use this online application process and need an alternative method for applying, you may contact us toll free at 1-510-713-4866 for assistance and we will get back to you as soon as possible.