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Maintain and integrate PCIe/ USB3.2/USB4/ related IP and peripheral design. Verify PCIe/ USB3.2/USB4 related IP.

1. SoC level and IP level verification methodology 2. Develop a verification plan and Integrated verification environment 3. Integrate VIP into the SOC verification platform.

Maintain and integrate PCIe/ USB3.2/USB4/ related IP and peripheral design. Verify PCIe/ USB3.2/USB4 related IP.

1.Creating verification plans of complex digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios. 2.Create verification environments using SystemVerilog, SystemC or UVM. 3.Identify and write all types of coverage measures for stimulus and corner-cases. 4.Debug tests with design engineers to deliver functionally correct design blocks. 5. Close coverage measures to identify verification holes and to sh

工作內容 Knowledge of System Verilog, digital simulation and debug. Exposure to UVM is desired. Familiar with USB design is a plus. DV Experience: 6~10 years 薪資架構 13個月計算, RSU 另計

Validate digital designs of extensive SoCs using advanced verification methodologies like UVM. Develop reusable bus functional models, monitors, checkers, and scoreboards using coverage-driven techniques. Comprehend design and implementation details, define verification scope, and establish verification infrastructure. Create and execute test plans efficiently to verify designs.

Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Science, or equivalent practical experience. 5 years of experience in the SOC design/verification. 5 years of experience with verification methodologies and languages such as UVM and SystemVerilog. Experience verifying digital logic at the Register Transfer Level (RTL) using SystemVerilog at Subsystem or Full chip level. Preferred qualifications: Experience in mobile SOC performance model development, performance analy

Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, ComputerScience, a related field, or equivalent practical experience. 8 years of experience with verification methodologies and languages such as UVM and SystemVerilog . Experience developing and maintaining verification testbenches, test cases,and test environments. Preferred qualifications: Master’s degree in Electrical Engineering, Computer Science, or equivalent practical experience. Experience with lo

Google welcomes people with disabilities. Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 8 years of experience with verification methodologies and languages such as UVM and SystemVerilog. Experience with functional verification and performance validation of modern mobile processors, microarchitecture, and related technologies. Preferred qualifications: Master's degree or PhD in E

Minimum qualifications: Bachelor's degree in Electrical Engineering or equivalent practical experience. 4 years of experience with verification methodology such as Universal verification methodology (UVM). 2 years of experience in the verification of IP designs such as IP, SoC, vector CPUs, etc. Experience with SystemVerilog, SVA, and functional coverage. Preferred qualifications: Master's degree in Electrical Engineering or a related field. Experience with industry-standard simulators, revision