Cake Job Search

Google welcomes people with disabilities. Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 3 years of experience with verification methodologies and languages such as UVM and SystemVerilog. Experience developing and maintaining verification testbenches, test cases, and test environments. Preferred qualifications: Master’s degree in Electrical Engineering, Computer Science, or relat

Validate digital designs of extensive SoCs using advanced verification methodologies like UVM. Develop reusable bus functional models, monitors, checkers, and scoreboards using coverage-driven techniques. Comprehend design and implementation details, define verification scope, and establish verification infrastructure. Create and execute test plans efficiently to verify designs.

Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Science, or equivalent practical experience. 3 years of experience with verification methodologies and languages (e.g., UVM, SystemVerilog). Experience developing and maintaining verification testbenches, test cases, and test environments. Experience working on main interconnects, DMA, controllers, and power management, and capturing design specifications in a temporal assertion language (e.g., SVA, PSL). Preferred qua

Minimum qualifications: Bachelor's degree in Electrical Engineering or equivalent practical experience. Experience in verification of IP designs (e.g., CPU, Peripherals, PMU, etc.). Experience with SystemVerilog, SVA and functional coverage. Experience with verification methodology (e.g., UVM, OVM, VMM). Preferred qualifications: Master's degree in Electrical Engineering, or a related field. Experience creating and using verification components and environments in standard verification methodolo

Minimum qualifications: Bachelor's degree in Electrical Engineering or Computer Science, or equivalent practical experience. 3 years of experience in Design Verification, verifying digital reasoning at Register-Transfer Level (RTL) level using C/C++, SystemVerilog or Universal Verification Methodology (UVM). Experience in verifying digital systems using standard Internet Protocol (IP) components/interconnects (e.g., microprocessor cores, hierarchical memory subsystems). Experience in creating an

Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or equivalent practical experience. 18 years of experience with digital logic design principles, RTL design concepts or verification methodologies and languages such as Universal Verification Methodology (UVM) and SystemVerilog. Experience in leading design development or functional verification team in Intellectual Property (IP) development for SoCs including Power, Performance and Area

Google welcomes people with disabilities. Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 5 years of experience with verification methodologies and languages such as UVM and SystemVerilog. Experience with hardware description languages like System Verilog and VHDL Experience with full cycle of design verification: plan, env/test developing, bug/cov closure. Preferred qualification

Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. 5 years of experience with verification methodologies and languages such as UVM and System Verilog. Experience developing and maintaining verification testbenches, test cases, and test environments. Preferred qualifications: Experience with Security IP and subsystems. Experienced in ARM or RISC-V CPU based subsystem verification. Experi

Minimum qualifications: Bachelor's degree in Electrical Engineering or equivalent practical experience. 2 years of experience in SOC/IP DV. Experience with verification methodology such as SV and UVM. Experience in ARM security architecture. Preferred qualifications: Familiarity with SoC level DV/UVM environment. Knowledge of JTAG/APB/AHB/AXI based protocols. HDL (Verilog/VHDL), HVL (System Verilog, OVM, ARM-C), and SVA (System Verilog Assertions) and experience with

Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or in a related field, or equivalent practical experience. 8 years of experience with verification methodologies and languages such as UVM and SystemVerilog. Experience in developing and maintaining Design Verification (DV) testbenches, test cases, and test environments. Preferred qualifications: Master's degree in Electrical Engineering, Computer Engineering or Computer Science, with an