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* Design and develop RTL for Big Data platform.  * Defines and documents RTL changes required for emulation/FPGA.  * Tests and debugs the emulation/FPGA model and collaterals.  * Develops improvements to usability by RTL validation and debugging of failing RTL tests on the emulation platform.  *You will join a growing team of IC design engineering professionals  and have a real opportunity to have your hardware solutions embraced and  to demonstrate

* Design and develop OpenCL/HLS/CUDA algorithms for HPC platform.  * Defines and documents OpenCL/HLS/CUDA algorithms required for emulation/FPGA.  * Tests and debugs the emulation/FPGA model and collaterals.  * Develops improvements to usability by digital circuit validation and debugging of failing tests on the emulation platform.  *You will join a growing team of digital IC design engineering professionals  and have a real opportunity to have your hardw

This internship shall last at least 4 months at full-time or 2-4 days per week part-time. Please make sure you will be able to complete this period before sending your application. * Studying and developing RTL code using Verilog to accelerate kernels for Big Data platforms  * System debug & Validation of FPGA prototype systems * Performance analysis and tuning of workloads on heterogeneous platform

Minimum qualifications: Bachelor's degree in Computer Engineering, Electrical Engineering, Computer Science, or related field, or equivalent practical experience. 5 years of experience with ML/AI frameworks and libraries (e.g., TensorFlow, PyTorch, scikit-learn). Experience with hardware description languages (e.g., Verilog, SystemVerilog, VHDL). Experience with applying ML/AI techniques. Preferred qualifications: Experie

Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 8 years of experience in ASIC development with Verilog/SystemVerilog, VHDL. Experience in ASIC design verification, synthesis, timing/power analysis, and Design for Testing (DFT). Experience in micro-architecture and design of IPs and Subsystems in Networking domain such as Packet processin

Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience 5 years of experience in ASIC development with Verilog/SystemVerilog, Vhsic Hardware Description Language (VHDL), or Chisel. Experience with ASIC design verification, synthesis, timing/power analysis, and Design for Testing (DFT). Experience in micro-architecture and design of IPs and subsy

Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience 5 years of experience in Application-specific integrated circuit (ASIC) development with Verilog/SystemVerilog, Vhsic Hardware Description Language (VHDL), or Chisel. Experience in ASIC design verification, synthesis, timing/power analysis, and Design for Testing (DFT). Experience in micro-