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Logo of WASAI Technology.
* Design and develop RTL for Big Data platform.  * Defines and documents RTL changes required for emulation/FPGA.  * Tests and debugs the emulation/FPGA model and collaterals.  * Develops improvements to usability by RTL validation and debugging of failing RTL tests on the emulation platform.  *You will join a growing team of IC design engineering professionals  and have a real opportunity to have your hardware solutions embraced and  to demonstrate
台灣
台北
VHDL
80 rb ~ 200 rb TWD / bulan
Tidak ada persyaratan pengalaman kerja terkait
Tidak ada tanggung jawab manajemen
Logo of 智易科技.
General Requirements1. RFSoC Multi-Domain Platform Bring-UpResponsible for bringing up Xilinx RFSoC platforms with multi-domain (A53/R5) coherence and external memory integration, running on PetaLinux.2. Comprehensive Toolchain ExpertiseProficient in the full development toolchain, including Vivado, Vitis, and PetaLinux, with practical experience following standard operating procedures (SOPs) for development, debugging, and deployment.3. EVM Simulation and An
"Windows 10"
"VHDL"
"Verilog"
Negotiable
Diperlukan pengalaman selama 3 tahun
Tidak ada tanggung jawab manajemen
Logo of WASAI Technology.
* Design and develop OpenCL/HLS/CUDA algorithms for HPC platform.  * Defines and documents OpenCL/HLS/CUDA algorithms required for emulation/FPGA.  * Tests and debugs the emulation/FPGA model and collaterals.  * Develops improvements to usability by digital circuit validation and debugging of failing tests on the emulation platform.  *You will join a growing team of digital IC design engineering professionals  and have a real opportunity to have your hardw
韌體/電子電路
VHDL
Verilog
80 rb ~ 150 rb TWD / bulan
Tidak ada persyaratan pengalaman kerja terkait
Tidak ada tanggung jawab manajemen
Logo of WASAI Technology.
This internship shall last at least 4 months at full-time or 2-4 days per week part-time. Please make sure you will be able to complete this period before sending your application. * Studying and developing RTL code using Verilog to accelerate kernels for Big Data platforms  * System debug & Validation of FPGA prototype systems * Performance analysis and tuning of workloads on heterogeneous platform
200 ~ 500 TWD / jam
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Tidak ada tanggung jawab manajemen
Logo of Google.
Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 1 year of experience with digital logic design, computer architecture, and circuit theory. Experience in scripting language (e.g., Python, Perl) or a hardware description language (e.g., Verilog, VHDL). Preferred qualifications: Master's degree or PhD in Electrical Eng
Negotiable
Tidak ada persyaratan pengalaman kerja terkait
Logo of Google.
Minimum qualifications: Bachelor's degree in Computer Engineering, Electrical Engineering, Computer Science, or related field, or equivalent practical experience. 5 years of experience with ML/AI frameworks and libraries (e.g., TensorFlow, PyTorch, scikit-learn). Experience with hardware description languages (e.g., Verilog, SystemVerilog, VHDL). Experience with applying ML/AI techniques. Preferred qualifications: Experie
Negotiable
Tidak ada persyaratan pengalaman kerja terkait
Logo of Google.
Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. 5 years of experience in ASIC development with Verilog/SystemVerilog, VHDL. Experience with ASIC design verification, synthesis, timing/power analysis, and Design for Testing (DFT). Experience in micro-architecture and design of subsystems. Preferred qualifications:
Negotiable
Tidak ada persyaratan pengalaman kerja terkait

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