Cake 找工作

* Design and develop RTL for Big Data platform. * Defines and documents RTL changes required for emulation/FPGA. * Tests and debugs the emulation/FPGA model and collaterals. * Develops improvements to usability by RTL validation and debugging of failing RTL tests on the emulation platform. *You will join a growing team of IC design engineering professionals and have a real opportunity to have your hardware solutions embraced and to demonstrate your coaching and mentoring skills

* Design and develop OpenCL/HLS/CUDA algorithms for HPC platform. * Defines and documents OpenCL/HLS/CUDA algorithms required for emulation/FPGA. * Tests and debugs the emulation/FPGA model and collaterals. * Develops improvements to usability by digital circuit validation and debugging of failing tests on the emulation platform. *You will join a growing team of digital IC design engineering professionals and have a real opportunity to have your hardware solutions

This internship shall last at least 4 months at full-time or 2-4 days per week part-time. Please make sure you will be able to complete this period before sending your application. * Studying and developing RTL code using Verilog to accelerate kernels for Big Data platforms * System debug & Validation of FPGA prototype systems * Performance analysis and tuning of workloads on heterogeneous platform

Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience 5 years of experience in Application-specific integrated circuit (ASIC) development with Verilog/SystemVerilog, Vhsic Hardware Description Language (VHDL), or Chisel. Experience in ASIC design verification, synthesis, timing/power analysis, and Design for Testing (DFT). Experience in micro-architecture and designing IPs and subsystems. P

Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. 8 years of experience in ASIC development with Verilog/SystemVerilog, VHDL. 5 years of experience in micro-architecture and design of IPs and Subsystems in networking domain such as packet processing, bandwidth management, congestion control etc. Experience in ASIC design verification, synthesis, timing/power analysis, and Design for Te

Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. 5 years of experience in ASIC development with Verilog/SystemVerilog, VHDL. Experience with ASIC design verification, synthesis, timing/power analysis, and Design for Testing (DFT). Experience in micro-architecture and design of subsystems. Preferred qualifications: Experience in SoC designs and integration flows. Experience with script

Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. 3 years of experience in ASIC development with Verilog/SystemVerilog, VHDL, or Chisel. Experience in ASIC design verification, synthesis, timing/power analysis, and Design for Testing (DFT). Experience in one or more SoC integration domains and flows (e.g., clocking, debug, fabrics, security, or low power methodologies). Preferred quali

Minimum qualifications: Bachelor's degree in Computer Engineering, Electrical Engineering, Computer Science, or related field, or equivalent practical experience. 5 years of experience with ML/AI frameworks and libraries (e.g., TensorFlow, PyTorch, scikit-learn). Experience with hardware description languages (e.g., Verilog, SystemVerilog, VHDL). Experience with applying ML/AI techniques. Preferred qualifications: Experience with ML/AI applications in hardware design, verification and Low Power

Google welcomes people with disabilities. Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 5 years of experience in high-performance CPU or AI accelerator logic/RTL design/integration including microarchitecture definition and PPA optimizations. Experience with a HDL language and front-end design methodology. Experience with CPU, cache subsystem integration with SOC. Experience wit