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Logo of NVIDIA.
We're now looking for a Senior Digital Design Verification Engineer! NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI — the next era of computing. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can
India Talents
Negotiable
5 years of experience required
No management responsibility
Logo of 創意電子股份有限公司.
1. Design verification 2. Generate models for PI/SI simulation (CPM/IBIS etc...) 3. Testchip testing 4. Edit testing program (python)
Digital IC
Design Verification
Negotiable
No requirement for relevant working experience
No management responsibility
Logo of Google.
Google welcomes people with disabilities. Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 3 years of experience with verification methodologies and languages such as UVM and SystemVerilog. Experience developing and maintaining verification testbenches, test cases, and test environments. Preferred qualifications: Master’s degree in Electrical Engineering, Computer Science, or relat
Logo of Cake Recruitment Consulting.
1. SoC level and IP level verification methodology 2. Develop a verification plan and Integrated verification environment 3. Integrate VIP into the SOC verification platform.
UVM
Verification
PCIe
2M ~ 4M TWD / year
5 years of experience required
No management responsibility
Logo of Cake Recruitment Consulting.
工作內容 Knowledge of System Verilog, digital simulation and debug. Exposure to UVM is desired. Familiar with USB design is a plus. DV Experience: 6~10 years 薪資架構 13個月計算, RSU 另計
Design Verification
DV
Systemverilog
4M ~ 5M TWD / year
6 years of experience required
Managing 1-5 staff
Logo of Cake Recruitment Consulting.
Validate digital designs of extensive SoCs using advanced verification methodologies like UVM. Develop reusable bus functional models, monitors, checkers, and scoreboards using coverage-driven techniques. Comprehend design and implementation details, define verification scope, and establish verification infrastructure. Create and execute test plans efficiently to verify designs.
DV
Design Validation
Firmware
Negotiable
5 years of experience required
No management responsibility
Logo of AMD.
THE ROLE: The Unified Memory Controller(UMC) is an IP that delivers into all SOCs that are shipped by AMD's Radeon Technology Group. We deliver discrete graphics, Data Center GPUs and Game Console APUs using a flexible controller design as the base for all our IP. We are looking for a design verification engineer in the Dram Controller IP at AMD's Santa Clara Design Center. You will be working in a fast-paced, complex environment
Negotiable
8 years of experience required
No management responsibility
Logo of Google.
Google welcomes people with disabilities. Minimum qualifications: Bachelor's degree in Electrical Engineering or Computer Science, or related field, or equivalent practical experience. 10 years of industry experience in Design Verification. Experience leading a team completing the full functional verification and performance validation cycle of subsystems such as multimedia, communication, or processors, or at the SOC level. Experience constructing reusable verification components and environmen
Logo of Google.
Google welcomes people with disabilities. Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 5 years of experience in functional verification, performance validation, developing test plans, and diagnostic codes of modern processors. Experience with processor microarchitecture. Preferred qualifications: Master’s degree in Electrical Engineering, Computer Science, or related field. Exp
Logo of Google.
Minimum qualifications: Bachelor's degree in Electrical Engineering or equivalent practical experience. 4 years of experience with verification methodology such as Universal verification methodology (UVM). 2 years of experience in the verification of IP designs such as IP, SoC, vector CPUs, etc. Experience with SystemVerilog, SVA, and functional coverage. Preferred qualifications: Master's degree in Electrical Engineering or a related field. Experience with industry-standard simulators, revision

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