Tìm kiếm việc làm online mới nhất!

Google welcomes people with disabilities.Minimum qualifications: Bachelor’s degree in Electrical Engineering, Mechanical Engineering, Industrial Engineering, Power related field, or equivalent practical experience. 5 years of experience in the power technology and manufacturing process. Experience in statistical product quality control, process capability, reliability, failure analysis, and process improvement. Preferred qualifications: Master's degree in Electrical Engineering, Mechanical Engineering, Industrial Engineering, or power related field, equivalent practical experience. Certifications in Quality (CQE, CQM, CRE, CQA, 6 Sigma). 7 years of experience in quality, reliability, or supplier quality management. Understanding of power supply technology. Ability to travel as needed. About the jobGoogles custom-designed machines make up one of the largest and most powerful computing infrastructures in the world. The Hardware Testing Engineering team ensures that this cutting-edge equipment is reliable. In the RD lab, you design test equipment for prototypes of our machinery and develop the protocols used to scale these tests for the entire global team. Working closely with design engineers, you give input on designs to improve our hardware until youre sure it meets Googles standards of quality and reliability. In this role, you work directly with supplier partners managing all aspects of power supplier quality. You collaborate with hardware designers, commodity managers, manufacturing engineers and drive supplier failure analysis. You establish true root causes, and drive systemic corrective actions with demonstrated preventative solutions. You extract and analyze data from supplier facilities, Google production lines, and the data centers to measure product performance and drive improvementsThe AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide. We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.Responsibilities Oversee the supplier quality and reliability of power deliverables throughout the lifecycle. Drive cross-functional activities in the supply chain for overall NPI phases and Mass Production. Provide consultation to the design, manufacturing and commodity teams in qualification, and application of thermal technologies. Conduct quality and manufacturing process audits for current and potential suppliers. Define and ensure processes in place to provide the data required to manage quality and reliability. Share Parts Per Million (PPM) feedback from the fleet and drive Return Material Authorization (RMA), Corrective Action Requests (CAR), Root Cause and Corrective Action (RCCA) and Failure Analysis (FA). Establish quality programs and process controls for detection of issues and to ensure the quality is delivered (e.g., gauge RandR, Cpk's, 8D's). Utilize Design of Experiments (DOE’s), Failure Modes and Effects Analysis (FMEA). Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.

Google will be prioritizing applicants who have valid working rights in Thailand and do not require Google’s sponsorship of a visa.Note: Google's hybrid workplace includes remote roles.Remote location: Thailand.Minimum qualifications: Bachelor's degree in Engineering (e.g., Quality, Electrical), or equivalent practical experience. 8 years of experience as a Quality, Reliability or Product Engineering. 4 years of experience in OCS manufacturing processes. Experience with the manufacturing and test processes, defects, and quality standards for optical components (e.g., lasers, photodetectors, lenses, filters, fiber assemblies, waveguides, ASIC and PCBs with optical interfaces). Experience with hardware in industries such as servers, automotive, or aerospace. Ability to travel up to 20% of the time as required. Preferred qualifications: 7 years of experience in Supply Chain Management, Procurement, or Operations roles within a high-volume, complex manufacturing or technology environment. Experience in material readiness, production control, and supplier performance management. Experience across all phases of a product life-cycle from prototype to mass production to end-of-life. Ability to manage Bills of Materials (BOMs) and complex production schedules. Excellent investigative thinking and problem-solving skills, with experience in data-driven decision-making. Excellent verbal and written communication and presentation skills, with the ability to communicate status and risks to cross-functional audiences. About the jobBe part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide. We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.Responsibilities Manage the supplier quality and reliability for Optical Circuit Switch (OCS) components, from New Product Introduction (NPI) through end-of-life. Lead cross-functional initiatives to ensure the OCS supply chain's technical and operational readiness for mass production. Drive supplier selection and qualification by conducting on-site audits and serving as the subject matter expert to influence product roadmaps. Resolve critical fleet and factory issues by leading suppliers through Root Cause and Corrective Action (RCCA) and Failure Analysis (FA) processes. Develop, implement, and monitor advanced quality plans and process controls (e.g., FMEA, Cpk, etc.) to drive continuous improvement and maintain supplier partnerships. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.

Minimum qualifications: Bachelor's degree in Electrical Engineering, a related field, or equivalent practical experience. 5 years of experience in DFT specification definition architecture and insertion. 3 years of experience using electronic design automation (EDA) test tools (e.g., Spyglass, Tessent). Experience with ASIC DFT synthesis, STA, simulation, and verification flow. Experience working with ATE engineers (e.g., silicon bring-up, patterns generation, debug, validation on automatic test equipment, and debug of silicon issues, etc.). Preferred qualifications: Master's degree in Electrical Engineering, or a related field. Experience in IP integration (e.g., memories, test controllers, TAP, and MBIST). Experience in SoC cycles, including silicon bring-up and silicon debug activities. Experience in fault modeling. About the jobBe part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. In this role, you will be responsible for defining, implementing, and deploying advanced Design for Testing (DFT) methodologies for digital, mixed-signal chips, or IPs. You will define silicon test strategies, DFT architecture, and create DFT specifications for next generation SoCs. You will design, insert, and verify the DFT logic. You will prepare for post-silicon and co-work/debug with test engineers. You will be responsible for reducing test cost, increasing production quality, and enhancing yield.Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.Responsibilities Develop DFT strategy and architecture, including hierarchical DFT/Memory Built-In Self Test (MBIST), IJTAG/TAP, and Hi-Speed IO. Demonstrate ownership from DFT logic, pre-silicon verification, to co-work with test engineers post silicon. Insert DFT logic, including boundary scan, scan chains, DFT Compression, Logic Built-In Self Test (BIST), Test Access Point (TAP) controller, Clock Control block, and other DFT IP blocks. Insert and hook up MBIST logic including test collar around memories, MBIST controllers, eFuse logic, and connect to core and TAP interfaces. Document DFT architecture and test sequences, including boot-up sequence associated with test pins. Complete all Test Design Rule Checks (TDRC) and design changes to fix TDRC violations to achieve high test quality and support post-silicon test team. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.

我們正在尋找一位擁有豐富伺服器硬體研發經驗的技術領導者， 帶領團隊從概念設計、電路開發、到產品量產， 打造符合雲端運算與資料中心高效能需求的次世代硬體產品。 🔧 主要職責 主導或指導團隊 進行伺服器與主機板之電子電路設計、開發與驗證。 探索並導入新一代晶片技術、架構概念與硬體設計方法， 將創新想法轉化為具市場競爭力的產品。 規劃與執行板級設計（包括零件選型、Layout 設計與電源架構整合）。 進行 電路設計審查（Self-review / Cross-review）， 並與跨部門工程團隊協作進行端到端設計檢核（End-to-End Review）。 負責硬體除錯與問題分析，提供完整的問題報告與改善建議。 規劃與執行 訊號量測、電源驗證、效能測試， 撰寫量測計畫與報告，確保設計品質符合規範。 協助製造端產品導入量產 (NPI)，支援量產測試與生產問題排除。 與 PM、ME、FW、驗證及供應鏈團隊協作， 共同推動產品從設計、驗證到量產全流程落地。

部門簡介 先進工業電腦視覺解決方案新事業發展部(Advanced Industrial Computer Vision Solution BD, AICBD) 致力於解決製造業中的人工作業問題，提供全面且靈活的解決方案，幫助企業在市場競爭中脫穎而出。AICBD專注於利用人工智慧（AI）和深度學習技術，為製造業提供高效且精確的電腦視覺解決方案，旨在提升生產效率和產品品質。 核心目標： 1. 提升組裝直通率：通過AI管理平台蒐集和分析工站影像資料，減少錯、漏、反造成品質不良的因素和降低重工率，提高生產效率。 2. 提高產品品質：在關鍵步驟應用AI電腦視覺技術，確保產品出貨後穩定可靠，增強競爭力。 3. 縮短新產品導入時間：利用AI技術，加快新產品導入流程，協助工廠提升競爭力。 主要職責 1. 硬體規格制定與選型： 根據產品需求與智能製造應用，制定硬體規格（如CPU、GPU、儲存空間、網路配置、報工設備、條碼相關設備等），確保效能與系統整合需求相符。 評估不同硬體組合（如: 最新 CPU、記憶體模組、I/O 介面等）的適配性、製造現場硬體架構、預防性維護計畫，確保硬體選型符合性能、成本和功耗等要求。 持續追蹤新世代硬體技術（如: CPU、GPU、Server、Storage等）之應用價值，並評估其在智能製造及工業自動化中的潛力。 2. 供應商管理評估與維運服務： 評估全球及區域供應商，確保供貨和維護服務符合需求；與供應商溝通技術細節，建立維護和故障排除體系。 3. 跨部門與跨單位協作： 與不同部門的產品經理、研發、測試部門合作，整合硬體選型需求，推進產品的硬體配置和規格落實，確保硬體方案符合市場競爭力。 4. 硬體測試與驗證： 協助硬體元件的測試、驗證，進行性能評估，並提供測試結果的技術建議，以確保硬體選擇符合產品需求。 5. 技術文件撰寫： 撰寫並維護硬體規格書、技術報告及測試文件，確保技術文件完整、準確且可追溯。 工作範疇 1. FA Software產線現場相關硬體管理： 覆蓋產線現場的相關硬體（如操作員報工設備、列印機、E-SOP、IPC、平板等）之標準化規格。 2. 機房內運算資源和網路架構配置： 包括伺服器、儲存設備、網路（LAN、Network/Infra）等，制定標準化硬體規格和配備。 其他需求 熟悉CPU/GPU架構（如Intel、AMD、NVIDIA），具備硬體診斷和故障排除能力。 熟悉IPC維運流程，並具備AI加速卡、網路連接技術（如5G、WiFi 6）及IoT接口相關知識。 熟悉工業自動化標準：如 OPC-UA、MODBUS，對工業物聯網（IIoT）有經驗者尤佳。 具備良好的供應商管理與評估能力，能針對性能和成本提出平衡方案。 具備技術文件撰寫與測試驗證能力，能清楚記錄並傳達技術需求。

[Responsibilities]Basic Debugging by Operator:- Upon new package release, execute diagnostic scripts and review failure logs to identify whether issues are related to hardware, software, or the test environment.- Hardware Issues: Provide relevant logs and update the failure status in the test unit sheet. The responsible owner will further analyze the root cause.- Software Issues: Attempt initial debugging. If the package contains errors, resolve them independently or consult the owner. Ensure the script runs error-free and upload any necessary modifications.- Environment Issues: Most environment-related issues can be resolved by rerunning the test or resetting the system.Log Management and Reporting:- Save all relevant logs and report results promptly to the designated owner.Script Modification:- Modify scripts as needed based on system type and testing requirements.Firmware Validation:- Manually execute commands to verify that firmware flashing and upgrades complete successfully. Check and confirm device status.On-Site Customer Support (Hsinchu):- Occasionally travel with the customer to Hsinchu for on-site support, as needed.[Requirement]- BS Degree in EE, with 3 to 4 years of Experience - Knowledge of Servers/PCs- Basic HW troubleshooting skills, first level of triage- Familiar with Hardware board bring and Test development on PCIe Interface- Scripting: Familiarity with scripting language like: Python and Linux Shell- Protocols: Like PCIE, USB and I2C/SPI- Operating Systems: Windows, Linux- Familiarity with Test Equipment (CRO, Power supply etc.) - Practical experience in high-tech environment, especially in NPI environment- Good Communication Skills, basic knowledge of common office software (Outlook, Excel, Word)- Ability to read schematics- Experience with installing FW/OS

透過https://forms.gle/d4Q9xUcuwRMZ97VV6表單回覆的履歷會優先處理哦 ! 【關於張量科技】張量科技成立於 2019 年，專注於衛星的姿態判定與控制系統 (Attitude Determination and Control Sub-system, ADCS)，致力於提供客戶更輕、更小、更省電的解決方案，使客戶降低任務成本、提升衛星的商業價值。我們的定位是一太空業的 Design Test house，主攻衛星相關產品的研發、設計、試組裝、校正與測試。目前，公司的客戶與合作夥伴包括了美國、歐洲與亞州的民間企業與研究機構。【為什麼你該選擇 張量科技】除了基本勞基法保障內容，我們還提供- 彈性上班：彈性上下班制度，上班不趕車、不用人擠人。- 遠端工作：依據職位提供部分遠端工作。- 分享活動：每月定期舉辦學術交流會議。- 週休二日：免補班。(優於勞基法)- 身體健康檢查補助 【工作內容】- 以理論分析、有限元素分析與實驗實測等手段，進行馬達、姿態控制用磁力棒（Magnetorquer）與衛星本體的磁路設計與優化- 進行馬達與磁力棒產品的電氣與機械規格的可行性評估- 藉由學術文獻、產業技術文件研究同類型的磁路設計，並針對產品需求提出合適的磁路設計。也歡迎應用公司資源研究新方法、新技術- 評估、尋商合適的磁性材料與供應商，並進行參數與特性的驗證- 與機構工程師和供應商協調產品結構考量與磁場效果，合作設計、優化具可靠度與可生產性的產品- 研究合適的產品磁路設計驗證方法或測試設備，並與及機構工程師合作開發量測工具與治具- 設計產品磁路驗證方法，並與組裝測試工程師 (Assembly, Integration, and Test Engineer, AIT) 合作建立產品 Quality Chack (QC) / Quality Assurance (QA) 的標準作業流程 (Standard Operation Procedure, SOP)- 撰寫設計與規格文件、整理與紀錄實驗和測試的數據- 建立磁場設計的數學模型，並與韌體和硬體工程師溝通驅動法與驅動器的設計與驗證手法

[電源研發工程師] 工作內容 1. DC/DC或AC/DC電源開發設計 2. 依產品設計規格需求挑選電子元件 3. 開發樣品製作/組裝/測試及設計開發資料撰寫 4. 電源EMC、安規驗證問題解決 5. 問題分析與解決 6. 主管交辦事項 [電源研發主管] 工作內容 1. 電源產品規格可行性評估及架構規劃。 2. 客戶應用問題的分析及處理。 3. 產品技術開發探討與產品規劃。 4. 開發人員的管理、輔導、培訓及進度掌控。 5. 各項開發設計資料的審核及知識管理。 6. 跨部門溝通。 7. 主管交辦事項。

【Job Description】 1. General tasks of EE engineers 2. In-depth research and optimization of Optical and SerDes systems 3. Advanced artificial intelligence research and automated test development 4. Optical transceiver design and verification 5. SI (signal integrity) and PI (power integrity) simulation 6. Able to cooperate with business trips abroad and participation in exhibitions

1.This engineer will be responsible for the Systems/HW development and validation of our Advanced Battery Management products. 2.Power and MCU schematic design. 3.System design and prototyping, including component selection, schematic design, and PCB layout design. 4.Design test setups for bench evaluation and application-level testing: automate test sequences, implement regression suites, and result analysis. 5.Create and execute plans to bring-up, debug, and validate HW designs to achieve functional and performance goals. 6.Collaborate with HW, FW and SW teams to debug and resolve any technical issue found via test. 7.Write technical specifications, requirement documents, application notes, user guides, and datasheet manuscripts for internal/external publication.