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Established in 1987 and headquartered in Taiwan, TSMC pioneered the pure-play foundry business model with an exclusive focus on manufacturing its customers’ products. As of 2024, TSMC serves more than 500 customers and manufactures over 11,000 products for high-performance computing, smartphones, the Internet of Things (IoT), automotive, and digital consumer electronics. It is the world’s largest provider of logic ICs, with an annual capacity of 16 million 12-inch equivalent wafers. TSMC operates fabs in Taiwan as well as manufacturing subsidiaries in Washington State, Japan and China, and the Company began construction on a specialty technology fab in Dresden, Germany, in 2024. In Arizona, TSMC is building three fabs, with the first starting 4nm production in 2025, the second by 2028, and the third by the end of the decade.We are seeking a highly motivated and talented RD Engineer to join our team in developing advanced IC packaging technologies. This position offers an exciting opportunity to work on cutting-edge solutions, such as CoWoS (Chip-on-Wafer-on-Substrate), Fan-Out Wafer Level Packaging (FOWLP), and 3DIC (Three-Dimensional Integrated Circuits). The ideal candidate will have strong technical expertise and a passion for innovation in semiconductor packaging design and analysis.Join us in shaping the future of advanced IC packaging technologies and contributing to groundbreaking innovations in the semiconductor industry. This role provides a unique opportunity to work in a dynamic environment, solve challenging engineering problems, and make a meaningful impact on next-generation packaging solutions.Responsibilities:1. Conduct risk assessments and provide mitigation plans for IC packages through simulation and experiment, interpreting experimental data and simulation to provide insights into material selection and design improvements.2. Practice FEM and DOE in problem solving and path finding particularly on packaging. Conduct mechanical or thermal simulations using finite element analysis (FEA) techniques to evaluate and optimize packaging performance, and analyze stress, deformation, and heat dissipation characteristics to ensure reliability and efficiency of packaging designs.3. Continuously improve simulation methodology, refine material modeling, and enhance script automation capabilities.

1. 進行流力、熱流、熱傳的建模分析，或結構應力、應變、疲勞的建模分析2. 電性模擬、量測、優化及相關需求對應3. 熟悉模擬軟體Flotherm/ ANSYS4. 產品前期模擬評估

【工作內容】1.具TSV相關之蝕刻、薄膜沉積、電鍍、化學機械平坦化(CMP)製程或設備經驗2.5D/3D封裝技術、TSV、TGV與封裝後段等製程評估3.晶圓/晶片/封裝製程異質整合開發4.具封裝產品開發經驗，熟悉半導體封裝製程 5.具系統級封裝經驗為佳6.具扇形封裝經驗後段經驗- SMT 製程、 Molding 製程、 SiP 製程相關站點7.新產品製程評估與開發 8.NPI良率改善與生產力提高9.具DOE實驗規劃能力【工作班制】．班別：週一至週五，週休二日．時間：08:30-17:30【工作地區】湖口光復廠：新竹縣湖口鄉光復路12號【薪資說明】◎依學經歷、科系、經驗相關性、特殊需求證照及專長等條件核敘個人薪資。

【工作內容】1.新製程/新材料/新機台評估及量產2.品質良率改善 3.製程流程簡化/產能提升/材料人力減少等cost down專案4.特殊工程品handle 5.相關生產的製程系統改善6.FEMEA管理與維護 7.製程相關機台及生產參數維護與改善 8.主管交辦事項※ 無經驗可，提供完整在職訓練【工作班制】．班別：作三休三 OR 作四休二 ．時間：日班07:20-19:20／夜班19:20-07:20（實際工時10小時，休息2小時）．輪調：每3個月日夜輪調一次【工作地區】湖口光復廠：新竹縣湖口鄉光復路12號【薪資說明】．依學經歷、科系、經驗相關性、特殊需求證照及專長等條件核敘個人薪資。．輪班人員之輪班津貼班制津貼另計