Cake 找工作

Established in 1987 and headquartered in Taiwan, TSMC pioneered the pure-play foundry business model with an exclusive focus on manufacturing its customers’ products. As of 2024, TSMC serves more than 500 customers and manufactures over 11,000 products for high-performance computing, smartphones, the Internet of Things (IoT), automotive, and digital consumer electronics. It is the world’s largest provider of logic ICs, with an annual capacity of 16 million 12-inch equivalent wafers. TSMC operates fabs in Taiwan as well as manufacturing subsidiaries in Washington State, Japan and China, and the Company began construction on a specialty technology fab in Dresden, Germany, in 2024. In Arizona, TSMC is building three fabs, with the first starting 4nm production in 2025, the second by 2028, and the third by the end of the decade.We are seeking a highly motivated and talented RD Engineer to join our team in developing advanced IC packaging technologies. This position offers an exciting opportunity to work on cutting-edge solutions, such as CoWoS (Chip-on-Wafer-on-Substrate), Fan-Out Wafer Level Packaging (FOWLP), and 3DIC (Three-Dimensional Integrated Circuits). The ideal candidate will have strong technical expertise and a passion for innovation in semiconductor packaging design and analysis.Join us in shaping the future of advanced IC packaging technologies and contributing to groundbreaking innovations in the semiconductor industry. This role provides a unique opportunity to work in a dynamic environment, solve challenging engineering problems, and make a meaningful impact on next-generation packaging solutions.Responsibilities:1. Conduct risk assessments and provide mitigation plans for IC packages through simulation and experiment, interpreting experimental data and simulation to provide insights into material selection and design improvements.2. Practice FEM and DOE in problem solving and path finding particularly on packaging. Conduct mechanical or thermal simulations using finite element analysis (FEA) techniques to evaluate and optimize packaging performance, and analyze stress, deformation, and heat dissipation characteristics to ensure reliability and efficiency of packaging designs.3. Continuously improve simulation methodology, refine material modeling, and enhance script automation capabilities.

1.製程開發執行, 新技術開發之時程掌控，以符合製程整合新製程開發之需求，提高客戶之滿意度2.開發模組製程, 使先進製程良率達到量產需求3.維持製程穩定度, 降低製程缺陷數目及提高機台妥善率4.線上異常處理及後續成效追蹤5.建立標準規範(SOP)，改善現行系統漏洞6.突破性製程研發改善，提高公司競爭力

1.Drive RD and process integration for 2.5D and 3DIC packaging platforms.2.Lead the development and qualification of new unit modules and device structures.3.Establish and validate new process flows in Design Start Modules (DSM) to support custom product platforms.4.Collaborate directly with customers on product requirements, verification testing, and technical solutions.5.Apply structured methodologies such as FMEA, DOE, and control plans to optimize performance and mitigate risks.

製程技術開發與優化1. 研究與導入新製程技術，包括嵌入式銅導線、埋入式無源元件、EMI屏蔽等技術。2. 評估與選定適合的材料（如高導熱介電材料、高可靠性封裝材料等）。3. 設計並驗證新製程方案，確保符合品質與量產要求。4. 新設備/材料評估與導入5. 評估新設備（如激光鑽孔機、選擇性電鍍設備、微細線路製造設備）與新材料的可行性。6. 建立設備參數最佳化與導入標準，確保符合生產需求。7. 與供應商合作進行設備與材料試產測試，推動正式導入。8. 製程良率提升與成本優化9. 監控與分析製程數據，找出良率瓶頸並推動改善專案。10. 訂定 SPC（統計製程管制）方案，確保生產品質穩定。11. 進行 Cost Down 方案，包括材料替代、工序最佳化、自動化導入等。12. 新產品失效分析與可靠性測試13. 建立與優化內埋式製程的失效分析方法，如掃描式電子顯微鏡（SEM）、X-ray、FIB（聚焦離子束）等。14. 制定可靠性測試流程，確保產品符合 AEC-Q100 / Q200 等汽車級認證標準。15. 主導客戶端品質問題處理，提供技術支援與對策方案。16. 跨部門協作與技術文件管理17. 與研發、設備、品保、製造等單位協作，確保製程技術順利導入與量產。18. 撰寫技術報告、標準作業流程（SOP），確保知識累積與可追溯性。19. 培訓生產與品質團隊，確保製程技術正確執行。

1.封裝設計開發 2.研究、評估與建立封裝工程的技術 3.封裝材料的驗證與選用 4.試產、量產時的產品異常分析與改善

1. 進行流力、熱流、熱傳的建模分析，或結構應力、應變、疲勞的建模分析2. 電性模擬、量測、優化及相關需求對應3. 熟悉模擬軟體Flotherm/ ANSYS4. 產品前期模擬評估

1. 新製程開發/新設備,材料評估導入2. 開發先進材料測技術與原理3. 製程良率改善/Cost Down專案/品質問題處理等4. 新產品失效分析流程建立

1. SI/PI 模擬分析及參數優化2. S-parameter與 RLCG 莘取3. PDK資料維護，確保封裝設計符合系統需求4. 新技術前期的模擬評估及設計規劃

1. New process/ capability research development2. New tool/ material evaluation3. Transfer new technology to mass production

【工作內容】1.具TSV相關之蝕刻、薄膜沉積、電鍍、化學機械平坦化(CMP)製程或設備經驗2.5D/3D封裝技術、TSV、TGV與封裝後段等製程評估3.晶圓/晶片/封裝製程異質整合開發4.具封裝產品開發經驗，熟悉半導體封裝製程 5.具系統級封裝經驗為佳6.具扇形封裝經驗後段經驗- SMT 製程、 Molding 製程、 SiP 製程相關站點7.新產品製程評估與開發 8.NPI良率改善與生產力提高9.具DOE實驗規劃能力【工作班制】．班別：週一至週五，週休二日．時間：08:30-17:30【工作地區】湖口光復廠：新竹縣湖口鄉光復路12號【薪資說明】◎依學經歷、科系、經驗相關性、特殊需求證照及專長等條件核敘個人薪資。